feat(mpmm): add support for MPMM
MPMM - the Maximum Power Mitigation Mechanism - is an optional
microarchitectural feature present on some Armv9-A cores, introduced
with the Cortex-X2, Cortex-A710 and Cortex-A510 cores.
MPMM allows the SoC firmware to detect and limit high activity events
to assist in SoC processor power domain dynamic power budgeting and
limit the triggering of whole-rail (i.e. clock chopping) responses to
overcurrent conditions.
This feature is enabled via the `ENABLE_MPMM` build option.
Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or
by via the plaform-implemented `plat_mpmm_topology` function.
Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167
Signed-off-by: Chris Kay <chris.kay@arm.com>
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
index f712520..35efd21 100644
--- a/lib/extensions/amu/aarch64/amu.c
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -23,6 +23,10 @@
# include <lib/fconf/fconf_amu_getter.h>
#endif
+#if ENABLE_MPMM
+# include <lib/mpmm/mpmm.h>
+#endif
+
struct amu_ctx {
uint64_t group0_cnts[AMU_GROUP0_MAX_COUNTERS];
#if ENABLE_AMU_AUXILIARY_COUNTERS
@@ -273,26 +277,31 @@
/* Initialize FEAT_AMUv1p1 features if present. */
if (id_aa64pfr0_el1_amu >= ID_AA64PFR0_AMU_V1P1) {
- return;
- }
-
- if (el2_unused) {
- /* Make sure virtual offsets are disabled if EL2 not used. */
- write_hcr_el2_amvoffen(0U);
- }
+ if (el2_unused) {
+ /*
+ * Make sure virtual offsets are disabled if EL2 not
+ * used.
+ */
+ write_hcr_el2_amvoffen(0U);
+ }
#if AMU_RESTRICT_COUNTERS
- /*
- * FEAT_AMUv1p1 adds a register field to restrict access to group 1
- * counters at all but the highest implemented EL. This is controlled
- * with the AMU_RESTRICT_COUNTERS compile time flag, when set, system
- * register reads at lower ELs return zero. Reads from the memory
- * mapped view are unaffected.
- */
- VERBOSE("AMU group 1 counter access restricted.\n");
- write_amcr_el0_cg1rz(1U);
+ /*
+ * FEAT_AMUv1p1 adds a register field to restrict access to
+ * group 1 counters at all but the highest implemented EL. This
+ * is controlled with the `AMU_RESTRICT_COUNTERS` compile time
+ * flag, when set, system register reads at lower ELs return
+ * zero. Reads from the memory mapped view are unaffected.
+ */
+ VERBOSE("AMU group 1 counter access restricted.\n");
+ write_amcr_el0_cg1rz(1U);
#else
- write_amcr_el0_cg1rz(0U);
+ write_amcr_el0_cg1rz(0U);
+#endif
+ }
+
+#if ENABLE_MPMM
+ mpmm_enable();
#endif
}
@@ -616,6 +625,10 @@
}
#endif
+#if ENABLE_MPMM
+ mpmm_enable();
+#endif
+
return (void *)0;
}