Merge changes from topic "mb/lfa-core-work" into integration
* changes:
docs(maintainers): add myself as code owner for LFA service
docs(lfa): update porting guide with LFA platform APIs
feat(lfa): add LFA holding pen logic
feat(lfa): add initial implementation for LFA_ACTIVATE
feat(lfa): add initial implementation for LFA_PRIME
feat(fvp): implement platform API for load and auth image
feat(lfa): implement LFA_CANCEL SMC
feat(fvp): implement platform API for LFA cancel operation
feat(lfa): implement LFA_GET_INVENTORY SMC
feat(fvp): implement platform API for LFA activation pending check
feat(lfa): implement LFA_GET_INFO SMC and integrate LFA build
feat(fvp): initialize LFA component activators in platform layer
feat(rmm): add placeholder activator callbacks for LFA
feat(bl31): add placeholder activator implementation for LFA
feat(lfa): add activation handler interface for component activation
feat(fvp): implement LFA get components API
feat(lfa): create LFA SMC handler template
diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index f6a27dc..30caeba 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c
@@ -227,6 +227,8 @@
*xfertype |= XFERTYPE_CICEN;
*xfertype |= XFERTYPE_CCCEN;
break;
+ case MMC_RESPONSE_NONE:
+ break;
default:
ERROR("Invalid CMD response: %u\n", cmd->resp_type);
return -EINVAL;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index b51e744..93a958c 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -437,7 +437,7 @@
int ret;
/* CMD0: reset to IDLE */
- ret = mmc_send_cmd(MMC_CMD(0), 0, 0, NULL);
+ ret = mmc_send_cmd(MMC_CMD(0), 0, MMC_RESPONSE_NONE, NULL);
if (ret != 0) {
return ret;
}
diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h
index f8d616f..895a705 100644
--- a/include/drivers/cadence/cdns_sdmmc.h
+++ b/include/drivers/cadence/cdns_sdmmc.h
@@ -342,7 +342,6 @@
/* MMC Peripheral Definition */
#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000)
-#define MMC_RESPONSE_NONE 0
#define SDHC_CDNS_SRS03_VALUE 0x01020013
/* Value randomly chosen for eMMC RCA, it should be > 1 */
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index 454a85a..55ed35c 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -52,6 +52,7 @@
#define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
#define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
#define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
+#define MMC_RESPONSE_NONE 0U
/* Value randomly chosen for eMMC RCA, it should be > 1 */
#define MMC_FIX_RCA 6
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c
index a95eb36..5e2d9e4 100644
--- a/plat/imx/imx8m/imx8mp/gpc.c
+++ b/plat/imx/imx8m/imx8mp/gpc.c
@@ -268,23 +268,6 @@
/* set the PGC bit */
mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
- /*
- * leave the G1, G2, H1 power domain on until VPUMIX power off,
- * otherwise system will hang due to VPUMIX ACK
- */
- if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) {
- return;
- }
-
- if (domain_id == VPUMIX) {
- mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ |
- VPU_G2_PWR_REQ | VPU_H1_PWR_REQ);
-
- while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ |
- VPU_G2_PWR_REQ | VPU_H1_PWR_REQ))
- ;
- }
-
/* power down the domain */
mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
diff --git a/plat/nxp/s32/s32g274ardb2/include/platform_def.h b/plat/nxp/s32/s32g274ardb2/include/platform_def.h
index cb16658..227c8e6 100644
--- a/plat/nxp/s32/s32g274ardb2/include/platform_def.h
+++ b/plat/nxp/s32/s32g274ardb2/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,24 +44,34 @@
#define BL33_BASE UL(0x34500000)
#define BL33_LIMIT UL(0x345FF000)
+/* IO buffer used to copy images from storage */
+#define IO_BUFFER_BASE BL33_LIMIT
+#define IO_BUFFER_SIZE U(0x13000)
+
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36)
/* We'll be doing a 1:1 mapping anyway */
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 36)
-#define MAX_MMAP_REGIONS U(18)
-#define MAX_XLAT_TABLES U(32)
+#define MAX_MMAP_REGIONS U(21)
+#define MAX_XLAT_TABLES U(33)
/* Console settings */
#define UART_BASE UL(0x401C8000)
#define UART_BAUDRATE U(115200)
#define UART_CLOCK_HZ U(125000000)
+/* uSDHC */
+#define S32G_USDHC_BASE UL(0x402F0000)
+
#define S32G_FIP_BASE UL(0x34100000)
#define S32G_FIP_SIZE UL(0x100000)
#define MAX_IO_HANDLES U(2)
#define MAX_IO_DEVICES U(2)
+/* uSDHC as block device */
+#define MAX_IO_BLOCK_DEVICES U(1)
+
/* GIC settings */
#define S32G_GIC_BASE UL(0x50800000)
#define PLAT_GICD_BASE S32G_GIC_BASE
diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
index 0929f9d..810b7bb 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
+++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,7 +8,10 @@
#include <common/debug.h>
#include <common/desc_image_load.h>
+#include <drivers/generic_delay_timer.h>
+#include <imx_usdhc.h>
#include <lib/mmio.h>
+#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <plat_console.h>
@@ -70,6 +73,29 @@
mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG);
}
+static void init_s32g_usdhc(void)
+{
+ static struct mmc_device_info sd_device_info = {
+ .mmc_dev_type = MMC_IS_SD_HC,
+ .ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4,
+ };
+ imx_usdhc_params_t params;
+
+ zeromem(¶ms, sizeof(imx_usdhc_params_t));
+
+ params.reg_base = S32G_USDHC_BASE;
+ params.clk_rate = 25000000;
+ params.bus_width = MMC_BUS_WIDTH_4;
+ params.flags = MMC_FLAG_SD_CMD6;
+
+ imx_usdhc_init(¶ms, &sd_device_info);
+}
+
+static void plat_s32_mmc_setup(void)
+{
+ init_s32g_usdhc();
+}
+
void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
@@ -103,9 +129,18 @@
panic();
}
+ generic_delay_timer_init();
+
+ /* Configure the generic timer frequency to ensure proper operation
+ * of the architectural timer in BL2.
+ */
+ write_cntfrq_el0(plat_get_syscnt_freq2());
+
linflex_config_pinctrl();
console_s32g2_register();
+ plat_s32_mmc_setup();
+
plat_s32g2_io_setup();
}
diff --git a/plat/nxp/s32/s32g274ardb2/plat_helpers.S b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
index a7dda0d..924808b 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_helpers.S
+++ b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -121,6 +121,9 @@
mov_imm x1, BL33_LIMIT
sub x1, x1, x0
bl zeromem
+ mov_imm x0, IO_BUFFER_BASE
+ mov_imm x1, IO_BUFFER_SIZE
+ bl zeromem
mov x30, x10
ret
endfunc platform_mem_init
diff --git a/plat/nxp/s32/s32g274ardb2/plat_io_storage.c b/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
index db6bcc5..c4efe01 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
+++ b/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
@@ -1,14 +1,19 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
+#include <drivers/io/io_block.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_fip.h>
#include <drivers/io/io_memmap.h>
+#include <drivers/mmc.h>
+#include <drivers/partition/partition.h>
+#include <lib/utils.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <tools_share/firmware_image_package.h>
@@ -20,24 +25,23 @@
int (*check)(const uintptr_t spec);
};
-static int open_memmap(const uintptr_t spec);
-static int open_fip(const uintptr_t spec);
-
static uintptr_t fip_dev_handle;
-static uintptr_t memmap_dev_handle;
+static io_block_spec_t fip_mmc_spec;
-static int open_memmap(const uintptr_t spec)
+static uintptr_t mmc_dev_handle;
+
+static int open_mmc(const uintptr_t spec)
{
- uintptr_t temp_handle = 0U;
+ uintptr_t temp_handle;
int result;
- result = io_dev_init(memmap_dev_handle, (uintptr_t)0);
+ result = io_dev_init(mmc_dev_handle, (uintptr_t)0U);
if (result != 0) {
return result;
}
- result = io_open(memmap_dev_handle, spec, &temp_handle);
+ result = io_open(mmc_dev_handle, spec, &temp_handle);
if (result == 0) {
(void)io_close(temp_handle);
}
@@ -66,16 +70,43 @@
void plat_s32g2_io_setup(void)
{
- static const io_dev_connector_t *memmap_dev_con;
+ static const io_block_dev_spec_t mmc_dev_spec = {
+ /* It's used as temp buffer in block driver. */
+ .buffer = {
+ .offset = IO_BUFFER_BASE,
+ .length = IO_BUFFER_SIZE,
+ },
+ .ops = {
+ .read = mmc_read_blocks,
+ .write = mmc_write_blocks,
+ },
+ .block_size = MMC_BLOCK_SIZE,
+ };
static const io_dev_connector_t *fip_dev_con;
+ static const io_dev_connector_t *mmc_dev_con;
+ partition_entry_t fip_part;
+ uintptr_t io_buf_base;
int result __unused;
+ size_t io_buf_size;
+ int ret;
- result = register_io_dev_memmap(&memmap_dev_con);
+ io_buf_base = mmc_dev_spec.buffer.offset;
+ io_buf_size = mmc_dev_spec.buffer.length;
+
+ ret = mmap_add_dynamic_region(io_buf_base, io_buf_base,
+ io_buf_size,
+ MT_MEMORY | MT_RW | MT_SECURE);
+ if (ret != 0) {
+ ERROR("Failed to map the IO buffer\n");
+ panic();
+ }
+
+ result = register_io_dev_block(&mmc_dev_con);
assert(result == 0);
- result = io_dev_open(memmap_dev_con, (uintptr_t)0,
- &memmap_dev_handle);
+ result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
+ &mmc_dev_handle);
assert(result == 0);
result = register_io_dev_fip(&fip_dev_con);
@@ -84,14 +115,24 @@
result = io_dev_open(fip_dev_con, (uintptr_t)0,
&fip_dev_handle);
assert(result == 0);
+
+ ret = gpt_partition_init();
+ if (ret != 0) {
+ ERROR("Could not load MBR partition table\n");
+ panic();
+ }
+
+ fip_part = get_partition_entry_list()->list[FIP_PART];
+ fip_mmc_spec.offset = fip_part.start;
+ fip_mmc_spec.length = fip_part.length;
}
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
- static const io_block_spec_t fip_block_spec = {
- .offset = S32G_FIP_BASE,
- .length = S32G_FIP_SIZE,
+ static const io_block_spec_t mbr_spec = {
+ .offset = 0,
+ .length = PLAT_PARTITION_BLOCK_SIZE,
};
static const io_uuid_spec_t bl31_uuid_spec = {
@@ -102,11 +143,11 @@
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
- static const struct plat_io_policy policies[BL33_IMAGE_ID + 1] = {
+ static const struct plat_io_policy policies[GPT_IMAGE_ID + 1] = {
[FIP_IMAGE_ID] = {
- .dev_handle = &memmap_dev_handle,
- .image_spec = (uintptr_t)&fip_block_spec,
- .check = open_memmap,
+ .dev_handle = &mmc_dev_handle,
+ .image_spec = (uintptr_t)&fip_mmc_spec,
+ .check = open_mmc,
},
[BL31_IMAGE_ID] = {
.dev_handle = &fip_dev_handle,
@@ -118,6 +159,11 @@
.image_spec = (uintptr_t)&bl33_uuid_spec,
.check = open_fip,
},
+ [GPT_IMAGE_ID] = {
+ .dev_handle = &mmc_dev_handle,
+ .image_spec = (uintptr_t)&mbr_spec,
+ .check = open_mmc,
+ },
};
const struct plat_io_policy *policy;
int result;
diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
index 4ec7cd0..25e9ebd 100644
--- a/plat/nxp/s32/s32g274ardb2/platform.mk
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -20,7 +20,8 @@
S32_ERRATA_LIST += ERRATA_S32_051700
PLAT_INCLUDES = \
- -I${PLAT_S32G274ARDB2}/include
+ -I${PLAT_S32G274ARDB2}/include \
+ -Idrivers/imx/usdhc \
PROGRAMMABLE_RESET_ADDRESS := 1
@@ -41,12 +42,19 @@
PLAT_XLAT_TABLES_DYNAMIC := 1
$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+NXP_ESDHC_LE := 1
+$(eval $(call add_define,NXP_ESDHC_LE))
+
# Selecting Drivers for SoC
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
$(eval $(call SET_NXP_MAKE_FLAG,CLK_NEEDED,BL_COMM))
include ${PLAT_DRIVERS_PATH}/drivers.mk
+# Selecting the raw partition where the FIP image is stored
+FIP_PART ?= 0
+$(eval $(call add_define,FIP_PART))
+
BL_COMMON_SOURCES += \
${PLAT_S32G274ARDB2}/plat_console.c \
${PLAT_S32G274ARDB2}/plat_helpers.S \
@@ -60,11 +68,21 @@
${PLAT_S32G274ARDB2}/plat_io_storage.c \
${PLAT_S32G274ARDB2}/s32cc_ncore.c \
common/desc_image_load.c \
+ common/tf_crc32.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/imx/usdhc/imx_usdhc.c \
+ drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
+ drivers/mmc/mmc.c \
+ drivers/partition/gpt.c \
+ drivers/partition/partition.c \
lib/cpus/aarch64/cortex_a53.S \
+BL2_CPPFLAGS += -march=armv8-a+crc
+
BL31_SOURCES += \
${GICV3_SOURCES} \
${PLAT_S32G274ARDB2}/plat_bl31_setup.c \
diff --git a/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c b/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c
index 4664438..eb903c5 100644
--- a/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c
+++ b/plat/nxp/s32/s32g274ardb2/s32cc_bl_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,7 @@
#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
#include <s32cc-bl-common.h>
@@ -38,3 +39,8 @@
return 0;
}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return COUNTER_FREQUENCY;
+}
diff --git a/plat/nxp/s32/s32g274ardb2/s32g2_soc.c b/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
index 0001352..c005bad 100644
--- a/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
+++ b/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,8 +45,3 @@
return (int)core_id;
}
-
-unsigned int plat_get_syscnt_freq2(void)
-{
- return COUNTER_FREQUENCY;
-}