Juno: Reserve some DDR-DRAM for secure use
This patch configures the TrustZone Controller in Juno to split
the 2GB DDR-DRAM memory at 0x80000000 into Secure and Non-Secure
regions:
- Secure DDR-DRAM: top 16 MB, except for the last 2 MB which are
used by the SCP for DDR retraining
- Non-Secure DDR-DRAM: remaining DRAM starting at base address
Build option PLAT_TSP_LOCATION selects the location of the secure
payload (BL3-2):
- 'tsram' : Trusted SRAM (default option)
- 'dram' : Secure region in the DDR-DRAM (set by the TrustZone
controller)
The MMU memory map has been updated to give BL2 permission to load
BL3-2 into the DDR-DRAM secure region.
Fixes ARM-software/tf-issues#233
Change-Id: I6843fc32ef90aadd3ea6ac4c7f314f8ecbd5d07b
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index ff8b49a..d62e67b 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -126,9 +126,12 @@
#define FAIL_ID_ID_SHIFT 0
/* Used along with 'tzc_region_attributes_t' below */
-#define REGION_ATTRIBUTES_SEC_SHIFT 30
-#define REGION_ATTRIBUTES_F_EN_SHIFT 0
-#define REGION_ATTRIBUTES_F_EN_MASK 0xf
+#define REG_ATTR_SEC_SHIFT 30
+#define REG_ATTR_F_EN_SHIFT 0
+#define REG_ATTR_F_EN_MASK 0xf
+#define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT)
+#define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \
+ REG_ATTR_F_EN_SHIFT)
#define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16
#define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0