Merge "intel: Remove un-needed checks for qspi driver r/w" into integration
diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst
index 41cd4d1..893aba2 100644
--- a/docs/getting_started/initial-build.rst
+++ b/docs/getting_started/initial-build.rst
@@ -8,13 +8,13 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
For AArch32:
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
+ export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-none-eabi-
It is possible to build TF-A using Clang or Arm Compiler 6. To do so
``CC`` needs to point to the clang or armclang binary, which will
@@ -32,7 +32,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
Clang will be selected when the base name of the path assigned to ``CC``
@@ -43,7 +43,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
make CC=<path-to-clang>/bin/clang PLAT=<platform> all
- Change to the root directory of the TF-A source tree and build.
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 27ad0ed..3e0c8ff 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -26,7 +26,7 @@
|TF-A| can be built with any of the following *cross-compiler* toolchains that
target the Armv7-A or Armv8-A architectures:
-- GCC >= 8.3-2019.03 (from the `Arm Developer website`_)
+- GCC >= 9.2-2019.12 (from the `Arm Developer website`_)
- Clang >= 4.0
- Arm Compiler >= 6.0
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index b6396b9..37010e1 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -223,7 +223,7 @@
.. code:: shell
- CROSS_COMPILE=aarch64-linux-gnu- \
+ CROSS_COMPILE=aarch64-none-elf- \
make PLAT=fvp DEBUG=1 \
RESET_TO_BL31=1 \
ARM_LINUX_KERNEL_AS_BL33=1 \
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index 6429ede..cf328fa 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -136,7 +136,7 @@
.. code:: shell
- export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+ export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf-
- The following parameters should be used to build BL1 and BL2 in AArch64
and point to the BL32 file.
diff --git a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
index 0d1e405..a0d02c9 100644
--- a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
+++ b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
@@ -1,11 +1,12 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __BPMP_IPC_H__
-#define __BPMP_IPC_H__
+#ifndef BPMP_IPC_H
+#define BPMP_IPC_H
#include <lib/utils_def.h>
#include <stdbool.h>
@@ -44,4 +45,4 @@
*/
int tegra_bpmp_ipc_disable_clock(uint32_t clk_id);
-#endif /* __BPMP_IPC_H__ */
+#endif /* BPMP_IPC_H */
diff --git a/plat/nvidia/tegra/include/drivers/gpcdma.h b/plat/nvidia/tegra/include/drivers/gpcdma.h
index fb5486a..a59df37 100644
--- a/plat/nvidia/tegra/include/drivers/gpcdma.h
+++ b/plat/nvidia/tegra/include/drivers/gpcdma.h
@@ -1,11 +1,12 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __GPCDMA_H__
-#define __GPCDMA_H__
+#ifndef GPCDMA_H
+#define GPCDMA_H
#include <stdint.h>
@@ -13,4 +14,4 @@
uint32_t num_bytes);
void tegra_gpcdma_zeromem(uint64_t dst_addr, uint32_t num_bytes);
-#endif /* __GPCDMA_H__ */
+#endif /* GPCDMA_H */
diff --git a/plat/nvidia/tegra/include/drivers/tegra_gic.h b/plat/nvidia/tegra/include/drivers/tegra_gic.h
index 6106b40..6661dff 100644
--- a/plat/nvidia/tegra/include/drivers/tegra_gic.h
+++ b/plat/nvidia/tegra/include/drivers/tegra_gic.h
@@ -1,11 +1,12 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TEGRA_GIC_H__
-#define __TEGRA_GIC_H__
+#ifndef TEGRA_GIC_H
+#define TEGRA_GIC_H
#include <common/interrupt_props.h>
@@ -26,4 +27,4 @@
void tegra_gic_setup(const interrupt_prop_t *interrupt_props,
unsigned int interrupt_props_num);
-#endif /* __TEGRA_GIC_H__ */
+#endif /* TEGRA_GIC_H */
diff --git a/plat/nvidia/tegra/include/lib/profiler.h b/plat/nvidia/tegra/include/lib/profiler.h
index 60f8d80..684c872 100644
--- a/plat/nvidia/tegra/include/lib/profiler.h
+++ b/plat/nvidia/tegra/include/lib/profiler.h
@@ -1,11 +1,12 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __PROFILER_H__
-#define __PROFILER_H__
+#ifndef PROFILER_H
+#define PROFILER_H
/*******************************************************************************
* Number of bytes of memory used by the profiler on Tegra
@@ -16,4 +17,4 @@
void boot_profiler_add_record(const char *str);
void boot_profiler_deinit(void);
-#endif /* __PROFILER_H__ */
+#endif /* PROFILER_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra194_private.h b/plat/nvidia/tegra/include/t194/tegra194_private.h
index e519cdc..8f1deb2 100644
--- a/plat/nvidia/tegra/include/t194/tegra194_private.h
+++ b/plat/nvidia/tegra/include/t194/tegra194_private.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TEGRA194_PRIVATE_H__
-#define __TEGRA194_PRIVATE_H__
+#ifndef TEGRA194_PRIVATE_H
+#define TEGRA194_PRIVATE_H
void tegra194_cpu_reset_handler(void);
uint64_t tegra194_get_cpu_reset_handler_base(void);
@@ -13,4 +13,4 @@
uint64_t tegra194_get_smmu_ctx_offset(void);
void tegra194_set_system_suspend_entry(void);
-#endif /* __TEGRA194_PRIVATE_H__ */
+#endif /* TEGRA194_PRIVATE_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 67f5abb..e20b2c6 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TEGRA_DEF_H__
-#define __TEGRA_DEF_H__
+#ifndef TEGRA_DEF_H
+#define TEGRA_DEF_H
#include <lib/utils_def.h>
@@ -237,4 +237,4 @@
#define TEGRA_SID_XUSB_VF2 U(0x5f)
#define TEGRA_SID_XUSB_VF3 U(0x60)
-#endif /* __TEGRA_DEF_H__ */
+#endif /* TEGRA_DEF_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
index e0444c1..1433a2e 100644
--- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __TEGRA_MC_DEF_H__
-#define __TEGRA_MC_DEF_H__
+#ifndef TEGRA_MC_DEF_H
+#define TEGRA_MC_DEF_H
/*******************************************************************************
* Memory Controller Order_id registers
@@ -647,4 +647,4 @@
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11)
-#endif /* __TEGRA_MC_DEF_H__ */
+#endif /* TEGRA_MC_DEF_H */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index 7dcfd84..226ab5b 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __MCE_PRIVATE_H__
-#define __MCE_PRIVATE_H__
+#ifndef MCE_PRIVATE_H
+#define MCE_PRIVATE_H
#include <tegra_def.h>
@@ -71,4 +71,4 @@
/* MCE helper functions */
void mce_enable_strict_checking(void);
-#endif /* __MCE_PRIVATE_H__ */
+#endif /* MCE_PRIVATE_H */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/se.h b/plat/nvidia/tegra/soc/t194/drivers/include/se.h
index 6e656f6..e7cf88d 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/se.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/se.h
@@ -1,13 +1,13 @@
/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __SE_H__
-#define __SE_H__
+#ifndef SE_H
+#define SE_H
int32_t tegra_se_suspend(void);
void tegra_se_resume(void);
-#endif /* __SE_H__ */
+#endif /* SE_H */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
index f5c0045..a2c5d1c 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
@@ -1,12 +1,12 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __SE_PRIVATE_H__
-#define __SE_PRIVATE_H__
+#ifndef SE_PRIVATE_H
+#define SE_PRIVATE_H
#include <lib/utils_def.h>
@@ -82,4 +82,4 @@
mmio_write_32(TEGRA_SE0_BASE + offset, val);
}
-#endif /* __SE_PRIVATE_H__ */
+#endif /* SE_PRIVATE_H */