Merge "xilinx: common: Move ATF handover to common file" into integration
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 2d672dd..665a05e 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -110,17 +110,13 @@
* caches and participate in coherency.
* --------------------------------------------------------------------
*/
- adrp x0, __DATA_START__
- add x0, x0, :lo12:__DATA_START__
- adrp x1, __DATA_END__
- add x1, x1, :lo12:__DATA_END__
+ adr x0, __DATA_START__
+ adr x1, __DATA_END__
sub x1, x1, x0
bl clean_dcache_range
- adrp x0, __BSS_START__
- add x0, x0, :lo12:__BSS_START__
- adrp x1, __BSS_END__
- add x1, x1, :lo12:__BSS_END__
+ adr x0, __BSS_START__
+ adr x1, __BSS_END__
sub x1, x1, x0
bl clean_dcache_range
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 1619914..51f5b7b 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -414,8 +414,7 @@
orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
/* Load descriptor index from array of indices */
- adrp x14, rt_svc_descs_indices
- add x14, x14, :lo12:rt_svc_descs_indices
+ adr x14, rt_svc_descs_indices
ldrb w15, [x14, x16]
/* Any index greater than 127 is invalid. Check bit 7. */
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 86fe236..42227f0 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -208,7 +208,6 @@
* Define a linker symbol to mark end of the RW memory area for this
* image.
*/
- . = ALIGN(PAGE_SIZE);
__RW_END__ = .;
__BL31_END__ = .;
diff --git a/docs/components/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst
index 9aba954..52b1c03 100644
--- a/docs/components/secure-partition-manager-design.rst
+++ b/docs/components/secure-partition-manager-design.rst
@@ -119,7 +119,7 @@
the rest of this document.
To enable SPM support in TF-A, the source code must be compiled with the build
-flag ``ENABLE_SPM=1``, along with ``EL3_EXCEPTION_HANDLING=1``. On Arm
+flag ``SPM_MM=1``, along with ``EL3_EXCEPTION_HANDLING=1``. On Arm
platforms the build option ``ARM_BL31_IN_DRAM`` must be set to 1. Also, the
location of the binary that contains the BL32 image
(``BL32=path/to/image.bin``) must be specified.
@@ -133,7 +133,7 @@
.. code:: shell
BL32=path/to/standalone/mm/sp BL33=path/to/bl33.bin \
- make PLAT=fvp ENABLE_SPM=1 ARM_BL31_IN_DRAM=1 fip all
+ make PLAT=fvp SPM_MM=1 EL3_EXCEPTION_HANDLING=1 ARM_BL31_IN_DRAM=1 all fip
Describing Secure Partition resources
-------------------------------------
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 5bd53f3..b419c85 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -395,21 +395,13 @@
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
-#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION
+#if ARM_BL31_IN_DRAM
/*
* Put BL31 at the bottom of TZC secured DRAM
*/
#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
PLAT_ARM_MAX_BL31_SIZE)
-/*
- * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM.
- * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten.
- */
-#if SEPARATE_NOBITS_REGION
-#define BL31_NOBITS_BASE BL2_BASE
-#define BL31_NOBITS_LIMIT BL2_LIMIT
-#endif /* SEPARATE_NOBITS_REGION */
#elif (RESET_TO_BL31)
/* Ensure Position Independent support (PIE) is enabled for this config.*/
# if !ENABLE_PIE
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index c9b9b38..398edf9 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -240,7 +240,7 @@
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
-ERRATA_N1_1043202 ?=1
+ERRATA_N1_1043202 ?=0
# Flag to apply erratum 1073348 workaround during reset. This erratum applies
# only to revision r0p0 and r1p0 of the Neoverse N1 cpu.
@@ -280,7 +280,7 @@
# Flag to apply erratum 1315703 workaround during reset. This erratum applies
# to revisions before r3p1 of the Neoverse N1 cpu.
-ERRATA_N1_1315703 ?=1
+ERRATA_N1_1315703 ?=0
# Flag to apply erratum 1542419 workaround during reset. This erratum applies
# to revisions r3p0 - r4p0 of the Neoverse N1 cpu.
diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S
index 2392d6b..2edf225 100644
--- a/lib/el3_runtime/aarch64/cpu_data.S
+++ b/lib/el3_runtime/aarch64/cpu_data.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -41,8 +41,7 @@
func _cpu_data_by_index
mov_imm x1, CPU_DATA_SIZE
mul x0, x0, x1
- adrp x1, percpu_data
- add x1, x1, :lo12:percpu_data
+ adr x1, percpu_data
add x0, x0, x1
ret
endfunc _cpu_data_by_index
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 7a3ca71..939885f 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -56,14 +56,6 @@
MT_CODE | MT_SECURE)
#endif
-#if SEPARATE_NOBITS_REGION
-#define MAP_BL31_NOBITS MAP_REGION_FLAT( \
- BL31_NOBITS_BASE, \
- BL31_NOBITS_LIMIT \
- - BL31_NOBITS_BASE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-
-#endif
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for the
* security state specified. BL33 corresponds to the non-secure image type
@@ -303,9 +295,6 @@
#if RECLAIM_INIT_CODE
MAP_BL_INIT_CODE,
#endif
-#if SEPARATE_NOBITS_REGION
- MAP_BL31_NOBITS,
-#endif
ARM_MAP_BL_RO,
#if USE_ROMLIB
ARM_MAP_ROMLIB_CODE,
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index ab33e1d..9d4f05e 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -125,23 +125,6 @@
# mapping the former as executable and the latter as execute-never.
SEPARATE_CODE_AND_RODATA := 1
-# On ARM platforms, disable SEPARATE_NOBITS_REGION by default. Both PROGBITS
-# and NOBITS sections of BL31 image are adjacent to each other and loaded
-# into Trusted SRAM.
-SEPARATE_NOBITS_REGION := 0
-
-# In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
-# BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
-# the build to require that ARM_BL31_IN_DRAM is enabled as well.
-ifeq ($(SEPARATE_NOBITS_REGION),1)
- ifneq ($(ARM_BL31_IN_DRAM),1)
- $(error For SEPARATE_NOBITS_REGION, ARM_BL31_IN_DRAM must be enabled)
- endif
- ifneq ($(RECLAIM_INIT_CODE),0)
- $(error For SEPARATE_NOBITS_REGION, RECLAIM_INIT_CODE cannot be supported)
- endif
-endif
-
# Disable ARM Cryptocell by default
ARM_CRYPTOCELL_INTEG := 0
$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))