qemu: support ARMv7/Cortex-A15
Define Qemu AArch32 implementation for some platform functions
(core position, secondary boot cores, crash console). These are
derived from the AArch64 implementation.
BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is
the first executable image after BL2.
Support SP_MIN and OP-TEE as BL32: create a sp_min make script target
in Qemu, define mapping for IMAGE_BL32
Minor fix Qemu return value type for plat_get_ns_image_entrypoint().
Qemu model for the Cortex-A15 does not support the virtualization
extension although the core expects it. To overcome the issue, Qemu
ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0.
Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform
used by the Qemu platform.
Qemu Cortex-A15 model integrates a single cluster with up to 4 cores.
Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index 60d9623..9e4a4a0 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -9,10 +9,9 @@
#include <console.h>
#include <debug.h>
#include <desc_image_load.h>
-#ifdef SPD_opteed
#include <optee_utils.h>
-#endif
#include <libfdt.h>
+#include <platform.h>
#include <platform_def.h>
#include <string.h>
#include <utils.h>
@@ -183,9 +182,15 @@
/* TODO Initialize timer */
}
+#ifdef AARCH32
+#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_secure(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
+#endif
+
void bl2_plat_arch_setup(void)
{
- qemu_configure_mmu_el1(bl2_tzram_layout.total_base,
+ QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE, BL2_RO_LIMIT,
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
@@ -196,11 +201,16 @@
******************************************************************************/
static uint32_t qemu_get_spsr_for_bl32_entry(void)
{
+#ifdef AARCH64
/*
* The Secure Payload Dispatcher service is responsible for
* setting the SPSR prior to entry into the BL3-2 image.
*/
return 0;
+#else
+ return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
+ DISABLE_ALL_EXCEPTIONS);
+#endif
}
/*******************************************************************************
@@ -208,8 +218,9 @@
******************************************************************************/
static uint32_t qemu_get_spsr_for_bl33_entry(void)
{
- unsigned int mode;
uint32_t spsr;
+#ifdef AARCH64
+ unsigned int mode;
/* Figure out what mode we enter the non-secure world in */
mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
@@ -220,6 +231,11 @@
* well.
*/
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+#else
+ spsr = SPSR_MODE32(MODE32_svc,
+ plat_get_ns_image_entrypoint() & 0x1,
+ SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+#endif
return spsr;
}
@@ -228,7 +244,7 @@
{
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
-#ifdef SPD_opteed
+#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
bl_mem_params_node_t *pager_mem_params = NULL;
bl_mem_params_node_t *paged_mem_params = NULL;
#endif
@@ -236,9 +252,8 @@
assert(bl_mem_params);
switch (image_id) {
-# ifdef AARCH64
case BL32_IMAGE_ID:
-#ifdef SPD_opteed
+#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
assert(pager_mem_params);
@@ -252,16 +267,31 @@
WARN("OPTEE header parse error.\n");
}
+#if defined(SPD_opteed)
/*
* OP-TEE expect to receive DTB address in x2.
* This will be copied into x2 by dispatcher.
*/
bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
+#else /* case AARCH32_SP_OPTEE */
+ bl_mem_params->ep_info.args.arg0 =
+ bl_mem_params->ep_info.args.arg1;
+ bl_mem_params->ep_info.args.arg1 = 0;
+ bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE;
+ bl_mem_params->ep_info.args.arg3 = 0;
+#endif
#endif
bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
break;
-# endif
+
case BL33_IMAGE_ID:
+#ifdef AARCH32_SP_OPTEE
+ /* AArch32 only core: OP-TEE expects NSec EP in register LR */
+ pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
+ assert(pager_mem_params);
+ pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
+#endif
+
/* BL33 expects to receive the primary CPU MPID (through r0) */
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
@@ -349,7 +379,7 @@
}
#endif /* !LOAD_IMAGE_V2 */
-unsigned long plat_get_ns_image_entrypoint(void)
+uintptr_t plat_get_ns_image_entrypoint(void)
{
return NS_IMAGE_OFFSET;
}