diff --git a/Makefile b/Makefile
index c740993..bd52c0b 100644
--- a/Makefile
+++ b/Makefile
@@ -452,18 +452,30 @@
 include make_helpers/armv7-a-cpus.mk
 endif
 
-ifeq ($(ENABLE_PIE),1)
-    TF_CFLAGS		+=	-fpie
-	ifneq ($(findstring gcc,$(notdir $(LD))),)
-		TF_LDFLAGS	+=	-Wl,-pie -Wl,--no-dynamic-linker
-	else
-		TF_LDFLAGS	+=	-pie --no-dynamic-linker
-	endif
+PIE_FOUND		:=	$(findstring --enable-default-pie,${GCC_V_OUTPUT})
+ifneq ($(PIE_FOUND),)
+	TF_CFLAGS	+=	-fno-PIE
+endif
+
+ifneq ($(findstring gcc,$(notdir $(LD))),)
+	PIE_LDFLAGS	+=	-Wl,-pie -Wl,--no-dynamic-linker
 else
-    PIE_FOUND		:=	$(findstring --enable-default-pie,${GCC_V_OUTPUT})
-    ifneq ($(PIE_FOUND),)
-        TF_CFLAGS		+=	-fno-PIE
-    endif
+	PIE_LDFLAGS	+=	-pie --no-dynamic-linker
+endif
+
+ifeq ($(ENABLE_PIE),1)
+ifeq ($(BL2_AT_EL3),1)
+ifneq ($(BL2_IN_XIP_MEM),1)
+	BL2_CFLAGS	+=	-fpie
+	BL2_LDFLAGS	+=	$(PIE_LDFLAGS)
+endif
+endif
+	BL31_CFLAGS	+=	-fpie
+	BL31_LDFLAGS	+=	$(PIE_LDFLAGS)
+ifeq ($(ARCH),aarch64)
+	BL32_CFLAGS	+=	-fpie
+	BL32_LDFLAGS	+=	$(PIE_LDFLAGS)
+endif
 endif
 
 # Include the CPU specific operations makefile, which provides default
diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S
index 2ca6acf..4eab39c 100644
--- a/bl2/aarch64/bl2_el3_entrypoint.S
+++ b/bl2/aarch64/bl2_el3_entrypoint.S
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <platform_def.h>
+
 #include <arch.h>
 #include <asm_macros.S>
 #include <common/bl_common.h>
@@ -13,6 +15,12 @@
 	.globl	bl2_el3_run_image
 	.globl	bl2_run_next_image
 
+#if BL2_IN_XIP_MEM
+#define FIXUP_SIZE	0
+#else
+#define FIXUP_SIZE	((BL2_LIMIT) - (BL2_BASE))
+#endif
+
 func bl2_entrypoint
 	/* Save arguments x0-x3 from previous Boot loader */
 	mov	x20, x0
@@ -27,7 +35,7 @@
 		_init_memory=1                                  \
 		_init_c_runtime=1                               \
 		_exception_vectors=bl2_el3_exceptions		\
-		_pie_fixup_size=0
+		_pie_fixup_size=FIXUP_SIZE
 
 	/* ---------------------------------------------
 	 * Restore parameters of boot rom
diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S
index dc398eb..b6570ee 100644
--- a/bl2/bl2_el3.ld.S
+++ b/bl2/bl2_el3.ld.S
@@ -69,6 +69,16 @@
         KEEP(*(cpu_ops))
         __CPU_OPS_END__ = .;
 
+        /*
+         * Keep the .got section in the RO section as it is patched
+         * prior to enabling the MMU and having the .got in RO is better for
+         * security. GOT is a table of addresses so ensure 8-byte alignment.
+         */
+        . = ALIGN(8);
+        __GOT_START__ = .;
+        *(.got)
+        __GOT_END__ = .;
+
         . = ALIGN(PAGE_SIZE);
         __RODATA_END__ = .;
     } >ROM
@@ -100,6 +110,16 @@
         KEEP(*(.img_parser_lib_descs))
         __PARSER_LIB_DESCS_END__ = .;
 
+        /*
+         * Keep the .got section in the RO section as it is patched
+         * prior to enabling the MMU and having the .got in RO is better for
+         * security. GOT is a table of addresses so ensure 8-byte alignment.
+         */
+        . = ALIGN(8);
+        __GOT_START__ = .;
+        *(.got)
+        __GOT_END__ = .;
+
         *(.vectors)
         __RO_END_UNALIGNED__ = .;
         /*
@@ -139,6 +159,17 @@
         __DATA_RAM_END__ = .;
     } >RAM AT>ROM
 
+    /*
+     * .rela.dyn needs to come after .data for the read-elf utility to parse
+     * this section correctly. Ensure 8-byte alignment so that the fields of
+     * RELA data structure are aligned.
+     */
+    . = ALIGN(8);
+    __RELA_START__ = .;
+    .rela.dyn . : {
+    } >RAM
+    __RELA_END__ = .;
+
     stacks (NOLOAD) : {
         __STACKS_START__ = .;
         *(tzfw_normal_stacks)
@@ -195,6 +226,10 @@
     __RW_END__ = .;
     __BL2_END__ = .;
 
+    /DISCARD/ : {
+        *(.dynsym .dynstr .hash .gnu.hash)
+    }
+
 #if BL2_IN_XIP_MEM
     __BL2_RAM_START__ = ADDR(.data);
     __BL2_RAM_END__ = .;
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 42227f0..c7185a8 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -339,6 +339,10 @@
     __RW_END__ = .;
     __BL31_END__ = .;
 
+    /DISCARD/ : {
+        *(.dynsym .dynstr .hash .gnu.hash)
+    }
+
     ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
 #endif
 }
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index 1d3ec21..ebc5c2c 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -1,9 +1,11 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <platform_def.h>
+
 #include <arch.h>
 #include <asm_macros.S>
 #include <bl32/tsp/tsp.h>
@@ -46,6 +48,24 @@
 
 func tsp_entrypoint _align=3
 
+#if ENABLE_PIE
+		/*
+		 * ------------------------------------------------------------
+		 * If PIE is enabled fixup the Global descriptor Table only
+		 * once during primary core cold boot path.
+		 *
+		 * Compile time base address, required for fixup, is calculated
+		 * using "pie_fixup" label present within first page.
+		 * ------------------------------------------------------------
+		 */
+	pie_fixup:
+		ldr	x0, =pie_fixup
+		and	x0, x0, #~(PAGE_SIZE - 1)
+		mov_imm	x1, (BL32_LIMIT - BL32_BASE)
+		add	x1, x1, x0
+		bl	fixup_gdt_reloc
+#endif /* ENABLE_PIE */
+
 	/* ---------------------------------------------
 	 * Set the exception vector to something sane.
 	 * ---------------------------------------------
diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S
index e9a1df1..592e245 100644
--- a/bl32/tsp/tsp.ld.S
+++ b/bl32/tsp/tsp.ld.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -36,6 +36,17 @@
     .rodata . : {
         __RODATA_START__ = .;
         *(.rodata*)
+
+        /*
+         * Keep the .got section in the RO section as it is patched
+         * prior to enabling the MMU and having the .got in RO is better for
+         * security. GOT is a table of addresses so ensure 8-byte alignment.
+         */
+        . = ALIGN(8);
+        __GOT_START__ = .;
+        *(.got)
+        __GOT_END__ = .;
+
         . = ALIGN(PAGE_SIZE);
         __RODATA_END__ = .;
     } >RAM
@@ -45,7 +56,19 @@
         *tsp_entrypoint.o(.text*)
         *(.text*)
         *(.rodata*)
+
+        /*
+         * Keep the .got section in the RO section as it is patched
+         * prior to enabling the MMU and having the .got in RO is better for
+         * security. GOT is a table of addresses so ensure 8-byte alignment.
+         */
+        . = ALIGN(8);
+        __GOT_START__ = .;
+        *(.got)
+        __GOT_END__ = .;
+
         *(.vectors)
+
         __RO_END_UNALIGNED__ = .;
         /*
          * Memory page(s) mapped to this section will be marked as
@@ -69,6 +92,17 @@
         __DATA_END__ = .;
     } >RAM
 
+    /*
+     * .rela.dyn needs to come after .data for the read-elf utility to parse
+     * this section correctly. Ensure 8-byte alignment so that the fields of
+     * RELA data structure are aligned.
+     */
+    . = ALIGN(8);
+    __RELA_START__ = .;
+    .rela.dyn . : {
+    } >RAM
+    __RELA_END__ = .;
+
 #ifdef TSP_PROGBITS_LIMIT
     ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
 #endif
@@ -129,6 +163,10 @@
     __RW_END__ = .;
     __BL32_END__ = .;
 
+    /DISCARD/ : {
+        *(.dynsym .dynstr .hash .gnu.hash)
+    }
+
     __BSS_SIZE__ = SIZEOF(.bss);
 #if USE_COHERENT_MEM
     __COHERENT_RAM_UNALIGNED_SIZE__ =
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 7fa027f..f3096b4 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -324,6 +324,11 @@
    as recommended in section "4.7 Non-Temporal Loads/Stores" of the
    `Cortex-A57 Software Optimization Guide`_.
 
+-  ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
+   level cache(LLC) is present in the system, and that the DataSource field
+   on the master CHI interface indicates when data is returned from the LLC.
+   This is used to control how the LL_CACHE* PMU events count.
+
 --------------
 
 *Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index d7bb044..fc45455 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -213,7 +213,7 @@
 
 -  ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
    support within generic code in TF-A. This option is currently only supported
-   in BL31. Default is 0.
+   in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0.
 
 -  ``ENABLE_PMF``: Boolean option to enable support for optional Performance
    Measurement Framework(PMF). Default is 0.
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 896a03f..77fb1f6 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -106,6 +106,7 @@
 IMPORT_SYM(uintptr_t, __RO_START__,		BL_CODE_BASE);
 IMPORT_SYM(uintptr_t, __RO_END__,		BL_CODE_END);
 #endif
+IMPORT_SYM(uintptr_t, __RW_END__,		BL_END);
 
 #if defined(IMAGE_BL1)
 IMPORT_SYM(uintptr_t, __BL1_ROM_END__,		BL1_ROM_END);
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index fa733ce..b50befa 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -35,6 +35,7 @@
 
 #define NEOVERSE_N1_WS_THR_L2_MASK	(ULL(3) << 24)
 #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT	(ULL(1) << 51)
+#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT		(ULL(1) << 0)
 
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index d058d98..d537ed6 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -465,6 +465,13 @@
 	msr	CPUAMCNTENSET_EL0, x0
 #endif
 
+#if NEOVERSE_N1_EXTERNAL_LLC
+	/* Some system may have External LLC, core needs to be made aware */
+	mrs     x0, NEOVERSE_N1_CPUECTLR_EL1
+	orr     x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
+	msr     NEOVERSE_N1_CPUECTLR_EL1, x0
+#endif
+
 #if ERRATA_DSU_936184
 	bl	errata_dsu_936184_wa
 #endif
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 398edf9..e3bfc2f 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -20,6 +20,10 @@
 WORKAROUND_CVE_2018_3639	?=1
 DYNAMIC_WORKAROUND_CVE_2018_3639	?=0
 
+# Flag to indicate internal or external Last level cache
+# By default internal
+NEOVERSE_N1_EXTERNAL_LLC	?=0
+
 # Process SKIP_A57_L1_FLUSH_PWR_DWN flag
 $(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
 $(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
@@ -43,6 +47,9 @@
 $(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
 $(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
 
+$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC))
+$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC))
+
 ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
     ifeq (${WORKAROUND_CVE_2018_3639},0)
         $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 6b72cfd..1fa26cc 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -412,6 +412,7 @@
 
 $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES),$(1)))
 $(eval $(call MAKE_LD,$(LINKERFILE),$(BL_LINKERFILE),$(1)))
+$(eval BL_LDFLAGS := $(BL$(call uppercase,$(1))_LDFLAGS))
 
 ifeq ($(USE_ROMLIB),1)
 $(ELF): romlib.bin
@@ -427,7 +428,7 @@
 		$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -xc -c - -o $(BUILD_DIR)/build_message.o
 endif
 ifneq ($(findstring armlink,$(notdir $(LD))),)
-	$$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) --entry=bl${1}_entrypoint \
+	$$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) --entry=bl${1}_entrypoint \
 		--predefine="-D__LINKER__=$(__LINKER__)" \
 		--predefine="-DTF_CFLAGS=$(TF_CFLAGS)" \
 		--map --list="$(MAPFILE)" --scatter=${PLAT_DIR}/scat/bl${1}.scat \
@@ -438,7 +439,7 @@
 		-Wl,-T$(LINKERFILE) $(BUILD_DIR)/build_message.o \
 		$(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS)
 else
-	$$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) -Map=$(MAPFILE) \
+	$$(Q)$$(LD) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) -Map=$(MAPFILE) \
 		--script $(LINKERFILE) $(BUILD_DIR)/build_message.o \
 		$(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS)
 endif
diff --git a/plat/arm/css/sgm/sgm-common.mk b/plat/arm/css/sgm/sgm-common.mk
index 34e78b2..ac34450 100644
--- a/plat/arm/css/sgm/sgm-common.mk
+++ b/plat/arm/css/sgm/sgm-common.mk
@@ -4,6 +4,8 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+CSS_USE_SCMI_SDS_DRIVER	:=	1
+
 CSS_SGM_BASE		:=	plat/arm/css/sgm
 
 PLAT_INCLUDES		:=	-I${CSS_SGM_BASE}/include
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 1e49e51..78766fc 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -5,7 +5,7 @@
 #
 
 # platform configs
-ENABLE_CONSOLE_SPE			:= 0
+ENABLE_CONSOLE_SPE			:= 1
 $(eval $(call add_define,ENABLE_CONSOLE_SPE))
 
 ENABLE_STRICT_CHECKING_MODE		:= 1
diff --git a/plat/socionext/uniphier/include/platform_def.h b/plat/socionext/uniphier/include/platform_def.h
index f5e7611..7c6341d 100644
--- a/plat/socionext/uniphier/include/platform_def.h
+++ b/plat/socionext/uniphier/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,28 +28,43 @@
 #define PLAT_MAX_OFF_STATE		U(2)
 #define PLAT_MAX_RET_STATE		U(1)
 
-#define BL2_BASE			ULL(0x80000000)
-#define BL2_LIMIT			ULL(0x80080000)
+#define UNIPHIER_BL2_OFFSET		UL(0x00000000)
+#define UNIPHIER_BL2_MAX_SIZE		UL(0x00080000)
 
-/* 0x80080000-0x81000000: reserved for DSP */
+/* 0x00080000-0x01000000: reserved for DSP */
 
-#define UNIPHIER_SEC_DRAM_BASE		0x81000000ULL
-#define UNIPHIER_SEC_DRAM_LIMIT		0x82000000ULL
-#define UNIPHIER_SEC_DRAM_SIZE		((UNIPHIER_SEC_DRAM_LIMIT) - \
-					 (UNIPHIER_SEC_DRAM_BASE))
+#define UNIPHIER_BL31_OFFSET		UL(0x01000000)
+#define UNIPHIER_BL31_MAX_SIZE		UL(0x00080000)
 
-#define BL31_BASE			ULL(0x81000000)
-#define BL31_LIMIT			ULL(0x81080000)
+#define UNIPHIER_BL32_OFFSET		UL(0x01080000)
+#define UNIPHIER_BL32_MAX_SIZE		UL(0x00100000)
 
-#define BL32_BASE			ULL(0x81080000)
-#define BL32_LIMIT			ULL(0x81180000)
+/*
+ * The link addresses are determined by UNIPHIER_MEM_BASE + offset.
+ * When ENABLE_PIE is set, all the TF images can be loaded anywhere, so
+ * UNIPHIER_MEM_BASE is arbitrary.
+ *
+ * When ENABLE_PIE is unset, UNIPHIER_MEM_BASE should be chosen so that
+ * BL2_BASE matches to the physical address where BL2 is loaded, that is,
+ * UNIPHIER_MEM_BASE should be the base address of the DRAM region.
+ */
+#define UNIPHIER_MEM_BASE		UL(0x00000000)
+
+#define BL2_BASE		(UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET)
+#define BL2_LIMIT		(BL2_BASE + UNIPHIER_BL2_MAX_SIZE)
+
+#define BL31_BASE		(UNIPHIER_MEM_BASE + UNIPHIER_BL31_OFFSET)
+#define BL31_LIMIT		(BL31_BASE + UNIPHIER_BL31_MAX_SIZE)
+
+#define BL32_BASE		(UNIPHIER_MEM_BASE + UNIPHIER_BL32_OFFSET)
+#define BL32_LIMIT		(BL32_BASE + UNIPHIER_BL32_MAX_SIZE)
 
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
 
 #define PLAT_XLAT_TABLES_DYNAMIC	1
-#define MAX_XLAT_TABLES			7
-#define MAX_MMAP_REGIONS		7
+#define MAX_XLAT_TABLES			9
+#define MAX_MMAP_REGIONS		13
 
 #define MAX_IO_HANDLES			2
 #define MAX_IO_DEVICES			2
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index d31fbe8..8e96b68 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -10,6 +10,10 @@
 override USE_COHERENT_MEM		:= 1
 override ENABLE_SVE_FOR_NS		:= 0
 
+# Disabling ENABLE_PIE saves memory footprint a lot, but you need to adjust
+# UNIPHIER_MEM_BASE so that all TF images are loaded at their link addresses.
+override ENABLE_PIE			:= 1
+
 # Cortex-A53 revision r0p4-51rel0
 # needed for LD20, unneeded for LD11, PXs3 (no ACE)
 ERRATA_A53_855873		:= 1
diff --git a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
index 0b232e0..4f58b68 100644
--- a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
+++ b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,8 +11,6 @@
 
 #include "../uniphier.h"
 
-#define BL32_SIZE		((BL32_END) - (BL32_BASE))
-
 void tsp_early_platform_setup(void)
 {
 	uniphier_console_setup();
@@ -24,6 +22,6 @@
 
 void tsp_plat_arch_setup(void)
 {
-	uniphier_mmap_setup(BL32_BASE, BL32_SIZE, NULL);
+	uniphier_mmap_setup();
 	enable_mmu_el1(0);
 }
diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h
index 648c2b9..729dc5c 100644
--- a/plat/socionext/uniphier/uniphier.h
+++ b/plat/socionext/uniphier/uniphier.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -36,24 +36,25 @@
 
 void uniphier_console_setup(void);
 
-int uniphier_emmc_init(uintptr_t *block_dev_spec);
-int uniphier_nand_init(uintptr_t *block_dev_spec);
-int uniphier_usb_init(unsigned int soc, uintptr_t *block_dev_spec);
+struct io_block_dev_spec;
+int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec);
+int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec);
+int uniphier_usb_init(unsigned int soc,
+		      struct io_block_dev_spec **block_dev_spec);
 
-int uniphier_io_setup(unsigned int soc);
+int uniphier_io_setup(unsigned int soc, uintptr_t mem_base);
 
+void uniphier_init_image_descs(uintptr_t mem_base);
 struct image_info;
 struct image_info *uniphier_get_image_info(unsigned int image_id);
 
 int uniphier_scp_is_running(void);
-void uniphier_scp_start(void);
+void uniphier_scp_start(uint32_t scp_base);
 void uniphier_scp_open_com(void);
 void uniphier_scp_system_off(void);
 void uniphier_scp_system_reset(void);
 
-struct mmap_region;
-void uniphier_mmap_setup(uintptr_t total_base, size_t total_size,
-			 const struct mmap_region *mmap);
+void uniphier_mmap_setup(void);
 
 void uniphier_cci_init(unsigned int soc);
 void uniphier_cci_enable(void);
@@ -67,25 +68,4 @@
 
 unsigned int uniphier_calc_core_pos(u_register_t mpidr);
 
-#define UNIPHIER_NS_DRAM_BASE		0x84000000
-#define UNIPHIER_NS_DRAM_LIMIT		0x85000000
-#define UNIPHIER_NS_DRAM_SIZE		((UNIPHIER_NS_DRAM_LIMIT) - \
-					 (UNIPHIER_NS_DRAM_BASE))
-
-#define UNIPHIER_BL33_BASE		(UNIPHIER_NS_DRAM_BASE)
-#define UNIPHIER_BL33_MAX_SIZE		0x00100000
-
-#define UNIPHIER_SCP_BASE		((UNIPHIER_BL33_BASE) + \
-					 (UNIPHIER_BL33_MAX_SIZE))
-#define UNIPHIER_SCP_MAX_SIZE		0x00020000
-
-#define UNIPHIER_BLOCK_BUF_BASE		((UNIPHIER_SCP_BASE) + \
-					 (UNIPHIER_SCP_MAX_SIZE))
-#define UNIPHIER_BLOCK_BUF_SIZE		0x00100000
-
-#define UNIPHIER_IMAGE_BUF_BASE		((UNIPHIER_BLOCK_BUF_BASE) + \
-					 (UNIPHIER_BLOCK_BUF_SIZE))
-#define UNIPHIER_IMAGE_BUF_SIZE		((UNIPHIER_NS_DRAM_LIMIT) - \
-					 (UNIPHIER_IMAGE_BUF_BASE))
-
 #endif /* UNIPHIER_H */
diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c
index 787b3ac..11d837c 100644
--- a/plat/socionext/uniphier/uniphier_bl2_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl2_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,8 +21,10 @@
 
 #include "uniphier.h"
 
-#define BL2_SIZE		((BL2_END) - (BL2_BASE))
+#define UNIPHIER_IMAGE_BUF_OFFSET	0x04300000UL
+#define UNIPHIER_IMAGE_BUF_SIZE		0x00100000UL
 
+static uintptr_t uniphier_mem_base = UNIPHIER_MEM_BASE;
 static int uniphier_bl2_kick_scp;
 
 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
@@ -31,32 +33,25 @@
 	uniphier_console_setup();
 }
 
-static const struct mmap_region uniphier_bl2_mmap[] = {
-	/* for BL31, BL32 */
-	MAP_REGION_FLAT(UNIPHIER_SEC_DRAM_BASE, UNIPHIER_SEC_DRAM_SIZE,
-			MT_MEMORY | MT_RW | MT_SECURE),
-	/* for SCP, BL33 */
-	MAP_REGION_FLAT(UNIPHIER_NS_DRAM_BASE, UNIPHIER_NS_DRAM_SIZE,
-			MT_MEMORY | MT_RW | MT_NS),
-	{ .size = 0 },
-};
-
 void bl2_el3_plat_arch_setup(void)
 {
 	unsigned int soc;
 	int skip_scp = 0;
 	int ret;
 
-	uniphier_mmap_setup(BL2_BASE, BL2_SIZE, uniphier_bl2_mmap);
+	uniphier_mmap_setup();
 	enable_mmu_el3(0);
 
+	/* add relocation offset (run-time-address - link-address) */
+	uniphier_mem_base += BL_CODE_BASE - BL2_BASE;
+
 	soc = uniphier_get_soc_id();
 	if (soc == UNIPHIER_SOC_UNKNOWN) {
 		ERROR("unsupported SoC\n");
 		plat_error_handler(-ENOTSUP);
 	}
 
-	ret = uniphier_io_setup(soc);
+	ret = uniphier_io_setup(soc, uniphier_mem_base);
 	if (ret) {
 		ERROR("failed to setup io devices\n");
 		plat_error_handler(ret);
@@ -119,28 +114,47 @@
 void bl2_plat_preload_setup(void)
 {
 #ifdef UNIPHIER_DECOMPRESS_GZIP
-	image_decompress_init(UNIPHIER_IMAGE_BUF_BASE,
-			      UNIPHIER_IMAGE_BUF_SIZE,
-			      gunzip);
+	uintptr_t buf_base = uniphier_mem_base + UNIPHIER_IMAGE_BUF_OFFSET;
+	int ret;
+
+	ret = mmap_add_dynamic_region(buf_base, buf_base,
+				      UNIPHIER_IMAGE_BUF_SIZE,
+				      MT_MEMORY | MT_RW | MT_NS);
+	if (ret)
+		plat_error_handler(ret);
+
+	image_decompress_init(buf_base, UNIPHIER_IMAGE_BUF_SIZE, gunzip);
 #endif
+
+	uniphier_init_image_descs(uniphier_mem_base);
 }
 
 int bl2_plat_handle_pre_image_load(unsigned int image_id)
 {
+	struct image_info *image_info;
+	int ret;
+
+	image_info = uniphier_get_image_info(image_id);
+
+	ret = mmap_add_dynamic_region(image_info->image_base,
+				      image_info->image_base,
+				      image_info->image_max_size,
+				      MT_MEMORY | MT_RW | MT_NS);
+	if (ret)
+		return ret;
+
 #ifdef UNIPHIER_DECOMPRESS_GZIP
-	image_decompress_prepare(uniphier_get_image_info(image_id));
+	image_decompress_prepare(image_info);
 #endif
 	return 0;
 }
 
 int bl2_plat_handle_post_image_load(unsigned int image_id)
 {
+	struct image_info *image_info = uniphier_get_image_info(image_id);
 #ifdef UNIPHIER_DECOMPRESS_GZIP
-	struct image_info *image_info;
 	int ret;
 
-	image_info = uniphier_get_image_info(image_id);
-
 	if (!(image_info->h.attr & IMAGE_ATTRIB_SKIP_LOADING)) {
 		ret = image_decompress(uniphier_get_image_info(image_id));
 		if (ret)
@@ -149,7 +163,7 @@
 #endif
 
 	if (image_id == SCP_BL2_IMAGE_ID && uniphier_bl2_kick_scp)
-		uniphier_scp_start();
+		uniphier_scp_start(image_info->image_base);
 
 	return 0;
 }
diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c
index 440e6aa..47f2378 100644
--- a/plat/socionext/uniphier/uniphier_bl31_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,8 +19,6 @@
 
 #include "uniphier.h"
 
-#define BL31_SIZE		((BL31_END) - (BL31_BASE))
-
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
 
@@ -81,6 +79,6 @@
 
 void bl31_plat_arch_setup(void)
 {
-	uniphier_mmap_setup(BL31_BASE, BL31_SIZE, NULL);
+	uniphier_mmap_setup();
 	enable_mmu_el3(0);
 }
diff --git a/plat/socionext/uniphier/uniphier_emmc.c b/plat/socionext/uniphier/uniphier_emmc.c
index 4ac1f51..d666ba7 100644
--- a/plat/socionext/uniphier/uniphier_emmc.c
+++ b/plat/socionext/uniphier/uniphier_emmc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -225,11 +225,7 @@
 	return ret ? 0 : size;
 }
 
-static const struct io_block_dev_spec uniphier_emmc_dev_spec = {
-	.buffer = {
-		.offset = UNIPHIER_BLOCK_BUF_BASE,
-		.length = UNIPHIER_BLOCK_BUF_SIZE,
-	},
+static struct io_block_dev_spec uniphier_emmc_dev_spec = {
 	.ops = {
 		.read = uniphier_emmc_read,
 	},
@@ -278,7 +274,7 @@
 	return 0;
 }
 
-int uniphier_emmc_init(uintptr_t *block_dev_spec)
+int uniphier_emmc_init(struct io_block_dev_spec **block_dev_spec)
 {
 	int ret;
 
@@ -286,7 +282,7 @@
 	if (ret)
 		return ret;
 
-	*block_dev_spec = (uintptr_t)&uniphier_emmc_dev_spec;
+	*block_dev_spec = &uniphier_emmc_dev_spec;
 
 	return 0;
 }
diff --git a/plat/socionext/uniphier/uniphier_image_desc.c b/plat/socionext/uniphier/uniphier_image_desc.c
index 817029a..8c232ba 100644
--- a/plat/socionext/uniphier/uniphier_image_desc.c
+++ b/plat/socionext/uniphier/uniphier_image_desc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,13 +13,19 @@
 
 #include "uniphier.h"
 
+#define UNIPHIER_BL33_OFFSET		0x04000000UL
+#define UNIPHIER_BL33_MAX_SIZE		0x00100000UL
+
+#define UNIPHIER_SCP_OFFSET		0x04100000UL
+#define UNIPHIER_SCP_MAX_SIZE		0x00020000UL
+
 static struct bl_mem_params_node uniphier_image_descs[] = {
 	{
 		.image_id = SCP_BL2_IMAGE_ID,
 
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 				      VERSION_2, image_info_t, 0),
-		.image_info.image_base = UNIPHIER_SCP_BASE,
+		.image_info.image_base = UNIPHIER_SCP_OFFSET,
 		.image_info.image_max_size = UNIPHIER_SCP_MAX_SIZE,
 
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
@@ -33,13 +39,13 @@
 
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 				      VERSION_2, image_info_t, 0),
-		.image_info.image_base = BL31_BASE,
-		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		.image_info.image_base = UNIPHIER_BL31_OFFSET,
+		.image_info.image_max_size = UNIPHIER_BL31_MAX_SIZE,
 
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
 				      VERSION_2, entry_point_info_t,
 				      SECURE | EXECUTABLE | EP_FIRST_EXE),
-		.ep_info.pc = BL31_BASE,
+		.ep_info.pc = UNIPHIER_BL31_OFFSET,
 		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
 					DISABLE_ALL_EXCEPTIONS),
 
@@ -55,13 +61,13 @@
 
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 				      VERSION_2, image_info_t, 0),
-		.image_info.image_base = BL32_BASE,
-		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		.image_info.image_base = UNIPHIER_BL32_OFFSET,
+		.image_info.image_max_size = UNIPHIER_BL32_MAX_SIZE,
 
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
 				      VERSION_2, entry_point_info_t,
 				      SECURE | EXECUTABLE),
-		.ep_info.pc = BL32_BASE,
+		.ep_info.pc = UNIPHIER_BL32_OFFSET,
 		.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
 					DISABLE_ALL_EXCEPTIONS),
 
@@ -73,13 +79,13 @@
 
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 				      VERSION_2, image_info_t, 0),
-		.image_info.image_base = UNIPHIER_BL33_BASE,
+		.image_info.image_base = UNIPHIER_BL33_OFFSET,
 		.image_info.image_max_size = UNIPHIER_BL33_MAX_SIZE,
 
 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
 				      VERSION_2, entry_point_info_t,
 				      NON_SECURE | EXECUTABLE),
-		.ep_info.pc = UNIPHIER_BL33_BASE,
+		.ep_info.pc = UNIPHIER_BL33_OFFSET,
 		.ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
 					DISABLE_ALL_EXCEPTIONS),
 
@@ -88,6 +94,21 @@
 };
 REGISTER_BL_IMAGE_DESCS(uniphier_image_descs)
 
+/*
+ * image_info.image_base and ep_info.pc are the offset from the memory base.
+ * When ENABLE_PIE is set, we never know the real memory base at link-time.
+ * Fix-up the addresses by adding the run-time detected base.
+ */
+void uniphier_init_image_descs(uintptr_t mem_base)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(uniphier_image_descs); i++) {
+		uniphier_image_descs[i].image_info.image_base += mem_base;
+		uniphier_image_descs[i].ep_info.pc += mem_base;
+	}
+}
+
 struct image_info *uniphier_get_image_info(unsigned int image_id)
 {
 	struct bl_mem_params_node *desc;
diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c
index b456bc5..89c8718 100644
--- a/plat/socionext/uniphier/uniphier_io_storage.c
+++ b/plat/socionext/uniphier/uniphier_io_storage.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,6 +26,9 @@
 #define UNIPHIER_OCM_REGION_BASE	0x30000000ULL
 #define UNIPHIER_OCM_REGION_SIZE	0x00040000ULL
 
+#define UNIPHIER_BLOCK_BUF_OFFSET	0x04200000UL
+#define UNIPHIER_BLOCK_BUF_SIZE		0x00100000UL
+
 static const io_dev_connector_t *uniphier_fip_dev_con;
 static uintptr_t uniphier_fip_dev_handle;
 
@@ -189,17 +192,29 @@
 #endif
 };
 
-static int uniphier_io_block_setup(size_t fip_offset, uintptr_t block_dev_spec)
+static int uniphier_io_block_setup(size_t fip_offset,
+				   struct io_block_dev_spec *block_dev_spec,
+				   size_t buffer_offset)
 {
 	int ret;
 
 	uniphier_fip_spec.offset = fip_offset;
 
+	block_dev_spec->buffer.offset = buffer_offset;
+	block_dev_spec->buffer.length = UNIPHIER_BLOCK_BUF_SIZE;
+
+	ret = mmap_add_dynamic_region(block_dev_spec->buffer.offset,
+				      block_dev_spec->buffer.offset,
+				      block_dev_spec->buffer.length,
+				      MT_MEMORY | MT_RW | MT_NS);
+	if (ret)
+		return ret;
+
 	ret = register_io_dev_block(&uniphier_backend_dev_con);
 	if (ret)
 		return ret;
 
-	return io_dev_open(uniphier_backend_dev_con, block_dev_spec,
+	return io_dev_open(uniphier_backend_dev_con, (uintptr_t)block_dev_spec,
 			   &uniphier_backend_dev_handle);
 }
 
@@ -234,38 +249,38 @@
 	return io_dev_open(uniphier_fip_dev_con, 0, &uniphier_fip_dev_handle);
 }
 
-static int uniphier_io_emmc_setup(unsigned int soc_id)
+static int uniphier_io_emmc_setup(unsigned int soc_id, size_t buffer_offset)
 {
-	uintptr_t block_dev_spec;
+	struct io_block_dev_spec *block_dev_spec;
 	int ret;
 
 	ret = uniphier_emmc_init(&block_dev_spec);
 	if (ret)
 		return ret;
 
-	return uniphier_io_block_setup(0x20000, block_dev_spec);
+	return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset);
 }
 
-static int uniphier_io_nand_setup(unsigned int soc_id)
+static int uniphier_io_nand_setup(unsigned int soc_id, size_t buffer_offset)
 {
-	uintptr_t block_dev_spec;
+	struct io_block_dev_spec *block_dev_spec;
 	int ret;
 
 	ret = uniphier_nand_init(&block_dev_spec);
 	if (ret)
 		return ret;
 
-	return uniphier_io_block_setup(0x20000, block_dev_spec);
+	return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset);
 }
 
-static int uniphier_io_nor_setup(unsigned int soc_id)
+static int uniphier_io_nor_setup(unsigned int soc_id, size_t buffer_offset)
 {
 	return uniphier_io_memmap_setup(0x70000);
 }
 
-static int uniphier_io_usb_setup(unsigned int soc_id)
+static int uniphier_io_usb_setup(unsigned int soc_id, size_t buffer_offset)
 {
-	uintptr_t block_dev_spec;
+	struct io_block_dev_spec *block_dev_spec;
 	int ret;
 
 	/* use ROM API for loading images from USB storage */
@@ -292,19 +307,19 @@
 	if (ret)
 		return ret;
 
-	return uniphier_io_block_setup(0x20000, block_dev_spec);
+	return uniphier_io_block_setup(0x20000, block_dev_spec, buffer_offset);
 }
 
-static int (* const uniphier_io_setup_table[])(unsigned int) = {
+static int (* const uniphier_io_setup_table[])(unsigned int, size_t) = {
 	[UNIPHIER_BOOT_DEVICE_EMMC] = uniphier_io_emmc_setup,
 	[UNIPHIER_BOOT_DEVICE_NAND] = uniphier_io_nand_setup,
 	[UNIPHIER_BOOT_DEVICE_NOR] = uniphier_io_nor_setup,
 	[UNIPHIER_BOOT_DEVICE_USB] = uniphier_io_usb_setup,
 };
 
-int uniphier_io_setup(unsigned int soc_id)
+int uniphier_io_setup(unsigned int soc_id, uintptr_t mem_base)
 {
-	int (*io_setup)(unsigned int soc_id);
+	int (*io_setup)(unsigned int soc_id, size_t buffer_offset);
 	unsigned int boot_dev;
 	int ret;
 
@@ -313,7 +328,7 @@
 		return -EINVAL;
 
 	io_setup = uniphier_io_setup_table[boot_dev];
-	ret = io_setup(soc_id);
+	ret = io_setup(soc_id, mem_base + UNIPHIER_BLOCK_BUF_OFFSET);
 	if (ret)
 		return ret;
 
diff --git a/plat/socionext/uniphier/uniphier_nand.c b/plat/socionext/uniphier/uniphier_nand.c
index 27e10e4..3925177 100644
--- a/plat/socionext/uniphier/uniphier_nand.c
+++ b/plat/socionext/uniphier/uniphier_nand.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -224,10 +224,6 @@
 }
 
 static struct io_block_dev_spec uniphier_nand_dev_spec = {
-	.buffer = {
-		.offset = UNIPHIER_BLOCK_BUF_BASE,
-		.length = UNIPHIER_BLOCK_BUF_SIZE,
-	},
 	.ops = {
 		.read = uniphier_nand_read,
 	},
@@ -259,7 +255,7 @@
 	return 0;
 }
 
-int uniphier_nand_init(uintptr_t *block_dev_spec)
+int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec)
 {
 	int ret;
 
@@ -269,7 +265,7 @@
 
 	uniphier_nand_dev_spec.block_size = uniphier_nand.page_size;
 
-	*block_dev_spec = (uintptr_t)&uniphier_nand_dev_spec;
+	*block_dev_spec = &uniphier_nand_dev_spec;
 
 	return 0;
 }
diff --git a/plat/socionext/uniphier/uniphier_scp.c b/plat/socionext/uniphier/uniphier_scp.c
index c608a25..8a12d5d 100644
--- a/plat/socionext/uniphier/uniphier_scp.c
+++ b/plat/socionext/uniphier/uniphier_scp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -28,11 +28,11 @@
 	return mmio_read_32(UNIPHIER_STMBE2COM) == UNIPHIER_SCP_READY_MAGIC;
 }
 
-void uniphier_scp_start(void)
+void uniphier_scp_start(uint32_t scp_base)
 {
 	uint32_t tmp;
 
-	mmio_write_32(UNIPHIER_STMBE2COM + 4, UNIPHIER_SCP_BASE);
+	mmio_write_32(UNIPHIER_STMBE2COM + 4, scp_base);
 	mmio_write_32(UNIPHIER_STMBE2COM, UNIPHIER_SCP_READY_MAGIC);
 
 	do {
diff --git a/plat/socionext/uniphier/uniphier_usb.c b/plat/socionext/uniphier/uniphier_usb.c
index ef7079a..7469ad1 100644
--- a/plat/socionext/uniphier/uniphier_usb.c
+++ b/plat/socionext/uniphier/uniphier_usb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -158,17 +158,14 @@
 }
 
 static struct io_block_dev_spec uniphier_usb_dev_spec = {
-	.buffer = {
-		.offset = UNIPHIER_BLOCK_BUF_BASE,
-		.length = UNIPHIER_BLOCK_BUF_SIZE,
-	},
 	.ops = {
 		.read = uniphier_usb_read,
 	},
 	.block_size = 512,
 };
 
-int uniphier_usb_init(unsigned int soc, uintptr_t *block_dev_spec)
+int uniphier_usb_init(unsigned int soc,
+		      struct io_block_dev_spec **block_dev_spec)
 {
 	const struct uniphier_usb_rom_param *param;
 
@@ -180,7 +177,7 @@
 
 	__uniphier_usb_read = param->read;
 
-	*block_dev_spec = (uintptr_t)&uniphier_usb_dev_spec;
+	*block_dev_spec = &uniphier_usb_dev_spec;
 
 	return 0;
 }
diff --git a/plat/socionext/uniphier/uniphier_xlat_setup.c b/plat/socionext/uniphier/uniphier_xlat_setup.c
index 0faebc9..18d2f9e 100644
--- a/plat/socionext/uniphier/uniphier_xlat_setup.c
+++ b/plat/socionext/uniphier/uniphier_xlat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,13 +12,12 @@
 #define UNIPHIER_REG_REGION_BASE	0x50000000ULL
 #define UNIPHIER_REG_REGION_SIZE	0x20000000ULL
 
-void uniphier_mmap_setup(uintptr_t total_base, size_t total_size,
-			 const struct mmap_region *mmap)
+void uniphier_mmap_setup(void)
 {
 	VERBOSE("Trusted RAM seen by this BL image: %p - %p\n",
-		(void *)total_base, (void *)(total_base + total_size));
-	mmap_add_region(total_base, total_base,
-			total_size,
+		(void *)BL_CODE_BASE, (void *)BL_END);
+	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
+			round_up(BL_END, PAGE_SIZE) - BL_CODE_BASE,
 			MT_MEMORY | MT_RW | MT_SECURE);
 
 	/* remap the code section */
@@ -40,9 +39,5 @@
 			UNIPHIER_REG_REGION_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE);
 
-	/* additional regions if needed */
-	if (mmap)
-		mmap_add(mmap);
-
 	init_xlat_tables();
 }