Merge changes I366740a9,I533abdd6,I6aa3b6dc into integration
* changes:
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
fix(n1sdp): add numa node id for pcie controllers
fix(n1sdp): replace non-inclusive terms from dts file
diff --git a/fdts/n1sdp-multi-chip.dts b/fdts/n1sdp-multi-chip.dts
index 8932dfc..852b899 100644
--- a/fdts/n1sdp-multi-chip.dts
+++ b/fdts/n1sdp-multi-chip.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
/*
- * Copyright (c) 2019-2020, Arm Limited.
+ * Copyright (c) 2019-2022, Arm Limited.
*/
#include "n1sdp-single-chip.dts"
@@ -54,19 +54,19 @@
<1 1 10>;
};
- smmu_slave_pcie: iommu@4004f400000 {
+ smmu_secondary_pcie: iommu@4004f400000 {
compatible = "arm,smmu-v3";
reg = <0x400 0x4f400000 0 0x40000>;
interrupts = <GIC_SPI 715 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 716 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 717 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
- msi-parent = <&its2_slave 0>;
+ msi-parent = <&its2_secondary 0>;
#iommu-cells = <1>;
dma-coherent;
};
- pcie_slave_ctlr: pcie@40070000000 {
+ pcie_secondary_ctlr: pcie@40070000000 {
compatible = "arm,n1sdp-pcie";
device_type = "pci";
reg = <0x400 0x70000000 0 0x1200000>;
@@ -84,8 +84,9 @@
<0 0 0 2 &gic 0 0 0 650 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic 0 0 0 651 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic 0 0 0 652 IRQ_TYPE_LEVEL_HIGH>;
- msi-map = <0 &its_slave_pcie 0 0x10000>;
- iommu-map = <0 &smmu_slave_pcie 0 0x10000>;
+ msi-map = <0 &its_secondary_pcie 0 0x10000>;
+ iommu-map = <0 &smmu_secondary_pcie 0 0x10000>;
+ numa-node-id = <1>;
status = "okay";
};
@@ -97,17 +98,25 @@
<0x0 0x300c0000 0 0x80000>, /* GICR */
<0x400 0x300c0000 0 0x80000>; /* GICR */
- its2_slave: its@40030060000 {
+ its2_secondary: its@40030060000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0x30060000 0x0 0x20000>;
};
- its_slave_pcie: its@400300a0000 {
+ its_secondary_pcie: its@400300a0000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0x300a0000 0x0 0x20000>;
};
};
+
+&pcie_ctlr {
+ numa-node-id = <0>;
+};
+
+&ccix_pcie_ctlr {
+ numa-node-id = <0>;
+};
diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
index 7d78a29..b3799a7 100644
--- a/plat/arm/board/n1sdp/include/platform_def.h
+++ b/plat/arm/board/n1sdp/include/platform_def.h
@@ -15,8 +15,9 @@
#define PLAT_ARM_BOOT_UART_BASE 0x2A400000
#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000
-#define PLAT_ARM_RUN_UART_BASE 0x2A410000
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000
+/* IOFPGA UART0 */
+#define PLAT_ARM_RUN_UART_BASE 0x1C090000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000
#define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000