Merge changes from topic "clk_fixed_divider" into integration
* changes:
feat(nxp-clk): set rate for clock fixed divider
feat(nxp-clk): add A53 clock objects
feat(nxp-clk): set rate for PLL divider objects
feat(nxp-clk): set rate for PLL objects
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index 69a9d21..f35a469 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -152,6 +152,7 @@
ret = -ENOTSUP;
break;
case s32cc_pll_out_div_t:
+ case s32cc_fixed_div_t:
ret = -ENOTSUP;
break;
default:
@@ -245,6 +246,100 @@
return -EINVAL;
}
+static int set_pll_freq(const struct s32cc_clk_obj *module, unsigned long rate,
+ unsigned long *orate, unsigned int *depth)
+{
+ struct s32cc_pll *pll = s32cc_obj2pll(module);
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if ((pll->vco_freq != 0UL) && (pll->vco_freq != rate)) {
+ ERROR("PLL frequency was already set\n");
+ return -EINVAL;
+ }
+
+ pll->vco_freq = rate;
+ *orate = pll->vco_freq;
+
+ return 0;
+}
+
+static int set_pll_div_freq(const struct s32cc_clk_obj *module, unsigned long rate,
+ unsigned long *orate, unsigned int *depth)
+{
+ struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
+ const struct s32cc_pll *pll;
+ unsigned long prate, dc;
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (pdiv->parent == NULL) {
+ ERROR("Failed to identify PLL divider's parent\n");
+ return -EINVAL;
+ }
+
+ pll = s32cc_obj2pll(pdiv->parent);
+ if (pll == NULL) {
+ ERROR("The parent of the PLL DIV is invalid\n");
+ return -EINVAL;
+ }
+
+ prate = pll->vco_freq;
+
+ /**
+ * The PLL is not initialized yet, so let's take a risk
+ * and accept the proposed rate.
+ */
+ if (prate == 0UL) {
+ pdiv->freq = rate;
+ *orate = rate;
+ return 0;
+ }
+
+ /* Decline in case the rate cannot fit PLL's requirements. */
+ dc = prate / rate;
+ if ((prate / dc) != rate) {
+ return -EINVAL;
+ }
+
+ pdiv->freq = rate;
+ *orate = pdiv->freq;
+
+ return 0;
+}
+
+static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long rate,
+ unsigned long *orate, unsigned int *depth)
+{
+ const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module);
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (fdiv->parent == NULL) {
+ ERROR("The divider doesn't have a valid parent\b");
+ return -EINVAL;
+ }
+
+ ret = set_module_rate(fdiv->parent, rate * fdiv->rate_div, orate, depth);
+
+ /* Update the output rate based on the parent's rate */
+ *orate /= fdiv->rate_div;
+
+ return ret;
+}
+
static int set_module_rate(const struct s32cc_clk_obj *module,
unsigned long rate, unsigned long *orate,
unsigned int *depth)
@@ -263,10 +358,17 @@
case s32cc_osc_t:
ret = set_osc_freq(module, rate, orate, depth);
break;
+ case s32cc_pll_t:
+ ret = set_pll_freq(module, rate, orate, depth);
+ break;
+ case s32cc_pll_out_div_t:
+ ret = set_pll_div_freq(module, rate, orate, depth);
+ break;
+ case s32cc_fixed_div_t:
+ ret = set_fixed_div_freq(module, rate, orate, depth);
+ break;
case s32cc_clkmux_t:
case s32cc_shared_clkmux_t:
- case s32cc_pll_t:
- case s32cc_pll_out_div_t:
ret = -ENOTSUP;
break;
default:
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
index 1f381b6..039db2a 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
@@ -7,6 +7,9 @@
#include <s32cc-clk-modules.h>
#include <s32cc-clk-utils.h>
+#define S32CC_A53_MIN_FREQ (48UL * MHZ)
+#define S32CC_A53_MAX_FREQ (1000UL * MHZ)
+
/* Oscillators */
static struct s32cc_osc fxosc =
S32CC_OSC_INIT(S32CC_FXOSC);
@@ -48,6 +51,23 @@
S32CC_CLK_ARM_PLL_DFS2, 0, 0);
static struct s32cc_clk cgm1_mux0_clk = S32CC_MODULE_CLK(cgm1_mux0);
+/* A53_CORE */
+static struct s32cc_clk a53_core_clk =
+ S32CC_FREQ_MODULE_CLK(cgm1_mux0_clk, S32CC_A53_MIN_FREQ,
+ S32CC_A53_MAX_FREQ);
+/* A53_CORE_DIV2 */
+static struct s32cc_fixed_div a53_core_div2 =
+ S32CC_FIXED_DIV_INIT(cgm1_mux0_clk, 2);
+static struct s32cc_clk a53_core_div2_clk =
+ S32CC_FREQ_MODULE_CLK(a53_core_div2, S32CC_A53_MIN_FREQ / 2,
+ S32CC_A53_MAX_FREQ / 2);
+/* A53_CORE_DIV10 */
+static struct s32cc_fixed_div a53_core_div10 =
+ S32CC_FIXED_DIV_INIT(cgm1_mux0_clk, 10);
+static struct s32cc_clk a53_core_div10_clk =
+ S32CC_FREQ_MODULE_CLK(a53_core_div10, S32CC_A53_MIN_FREQ / 10,
+ S32CC_A53_MAX_FREQ / 10);
+
static struct s32cc_clk *s32cc_hw_clk_list[5] = {
/* Oscillators */
[S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
@@ -63,12 +83,16 @@
.n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
};
-static struct s32cc_clk *s32cc_arch_clk_list[3] = {
+static struct s32cc_clk *s32cc_arch_clk_list[6] = {
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
/* MC_CGM1 */
[S32CC_CLK_ID(S32CC_CLK_MC_CGM1_MUX0)] = &cgm1_mux0_clk,
+ /* A53 */
+ [S32CC_CLK_ID(S32CC_CLK_A53_CORE)] = &a53_core_clk,
+ [S32CC_CLK_ID(S32CC_CLK_A53_CORE_DIV2)] = &a53_core_div2_clk,
+ [S32CC_CLK_ID(S32CC_CLK_A53_CORE_DIV10)] = &a53_core_div10_clk,
};
static struct s32cc_clk_array s32cc_arch_clocks = {
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 98f30d8..ac1f7d0 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -9,6 +9,8 @@
#include <s32cc-clk-utils.h>
#define S32CC_FXOSC_FREQ (40U * MHZ)
+#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
+#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
int s32cc_init_early_clks(void)
{
@@ -31,6 +33,16 @@
return ret;
}
+ ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
ret = clk_enable(S32CC_CLK_FXOSC);
if (ret != 0) {
return ret;
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
index 6ffe321..41fc6f4 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
@@ -19,6 +19,7 @@
s32cc_pll_out_div_t,
s32cc_clkmux_t,
s32cc_shared_clkmux_t,
+ s32cc_fixed_div_t,
};
enum s32cc_clk_source {
@@ -112,6 +113,30 @@
.index = (INDEX), \
}
+#define S32CC_PLL_OUT_DIV_INIT(PARENT, INDEX) \
+{ \
+ .desc = { \
+ .type = s32cc_pll_out_div_t, \
+ }, \
+ .parent = &(PARENT).desc, \
+ .index = (INDEX), \
+}
+
+struct s32cc_fixed_div {
+ struct s32cc_clk_obj desc;
+ struct s32cc_clk_obj *parent;
+ uint32_t rate_div;
+};
+
+#define S32CC_FIXED_DIV_INIT(PARENT, RATE_DIV) \
+{ \
+ .desc = { \
+ .type = s32cc_fixed_div_t, \
+ }, \
+ .parent = &(PARENT).desc, \
+ .rate_div = (RATE_DIV), \
+}
+
struct s32cc_clk {
struct s32cc_clk_obj desc;
struct s32cc_clk_obj *module;
@@ -188,4 +213,28 @@
return s32cc_obj2clkmux(clk->module);
}
+static inline struct s32cc_pll *s32cc_obj2pll(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t pll_addr;
+
+ pll_addr = ((uintptr_t)mod) - offsetof(struct s32cc_pll, desc);
+ return (struct s32cc_pll *)pll_addr;
+}
+
+static inline struct s32cc_pll_out_div *s32cc_obj2plldiv(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t plldiv_addr;
+
+ plldiv_addr = ((uintptr_t)mod) - offsetof(struct s32cc_pll_out_div, desc);
+ return (struct s32cc_pll_out_div *)plldiv_addr;
+}
+
+static inline struct s32cc_fixed_div *s32cc_obj2fixeddiv(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t fdiv_addr;
+
+ fdiv_addr = ((uintptr_t)mod) - offsetof(struct s32cc_fixed_div, desc);
+ return (struct s32cc_fixed_div *)fdiv_addr;
+}
+
#endif /* S32CC_CLK_MODULES_H */