diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index 925d1c2..02ffa02 100644
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -12,37 +12,37 @@
  ******************************************************************************/
 
 /* Interrupt group definitions */
-#define GICV2_INTR_GROUP0	0
-#define GICV2_INTR_GROUP1	1
+#define GICV2_INTR_GROUP0	U(0)
+#define GICV2_INTR_GROUP1	U(1)
 
 /* Interrupt IDs reported by the HPPIR and IAR registers */
-#define PENDING_G1_INTID	1022
+#define PENDING_G1_INTID	U(1022)
 
 /* GICv2 can only target up to 8 PEs */
-#define GICV2_MAX_TARGET_PE	8
+#define GICV2_MAX_TARGET_PE	U(8)
 
 /*******************************************************************************
  * GICv2 specific Distributor interface register offsets and constants.
  ******************************************************************************/
-#define GICD_ITARGETSR		0x800
-#define GICD_SGIR		0xF00
-#define GICD_CPENDSGIR		0xF10
-#define GICD_SPENDSGIR		0xF20
-#define GICD_PIDR2_GICV2	0xFE8
+#define GICD_ITARGETSR		U(0x800)
+#define GICD_SGIR		U(0xF00)
+#define GICD_CPENDSGIR		U(0xF10)
+#define GICD_SPENDSGIR		U(0xF20)
+#define GICD_PIDR2_GICV2	U(0xFE8)
 
 #define ITARGETSR_SHIFT		2
-#define GIC_TARGET_CPU_MASK	0xff
+#define GIC_TARGET_CPU_MASK	U(0xff)
 
 #define CPENDSGIR_SHIFT		2
 #define SPENDSGIR_SHIFT		CPENDSGIR_SHIFT
 
 #define SGIR_TGTLSTFLT_SHIFT	24
-#define SGIR_TGTLSTFLT_MASK	0x3
+#define SGIR_TGTLSTFLT_MASK	U(0x3)
 #define SGIR_TGTLST_SHIFT	16
-#define SGIR_TGTLST_MASK	0xff
-#define SGIR_INTID_MASK		0xf
+#define SGIR_TGTLST_MASK	U(0xff)
+#define SGIR_INTID_MASK		ULL(0xf)
 
-#define SGIR_TGT_SPECIFIC	0
+#define SGIR_TGT_SPECIFIC	U(0)
 
 #define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \
 	((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \
@@ -53,29 +53,29 @@
  * GICv2 specific CPU interface register offsets and constants.
  ******************************************************************************/
 /* Physical CPU Interface registers */
-#define GICC_CTLR		0x0
-#define GICC_PMR		0x4
-#define GICC_BPR		0x8
-#define GICC_IAR		0xC
-#define GICC_EOIR		0x10
-#define GICC_RPR		0x14
-#define GICC_HPPIR		0x18
-#define GICC_AHPPIR		0x28
-#define GICC_IIDR		0xFC
-#define GICC_DIR		0x1000
+#define GICC_CTLR		U(0x0)
+#define GICC_PMR		U(0x4)
+#define GICC_BPR		U(0x8)
+#define GICC_IAR		U(0xC)
+#define GICC_EOIR		U(0x10)
+#define GICC_RPR		U(0x14)
+#define GICC_HPPIR		U(0x18)
+#define GICC_AHPPIR		U(0x28)
+#define GICC_IIDR		U(0xFC)
+#define GICC_DIR		U(0x1000)
 #define GICC_PRIODROP		GICC_EOIR
 
 /* GICC_CTLR bit definitions */
-#define EOI_MODE_NS		(1 << 10)
-#define EOI_MODE_S		(1 << 9)
-#define IRQ_BYP_DIS_GRP1	(1 << 8)
-#define FIQ_BYP_DIS_GRP1	(1 << 7)
-#define IRQ_BYP_DIS_GRP0	(1 << 6)
-#define FIQ_BYP_DIS_GRP0	(1 << 5)
-#define CBPR			(1 << 4)
+#define EOI_MODE_NS		BIT_32(10)
+#define EOI_MODE_S		BIT_32(9)
+#define IRQ_BYP_DIS_GRP1	BIT_32(8)
+#define FIQ_BYP_DIS_GRP1	BIT_32(7)
+#define IRQ_BYP_DIS_GRP0	BIT_32(6)
+#define FIQ_BYP_DIS_GRP0	BIT_32(5)
+#define CBPR			BIT_32(4)
 #define FIQ_EN_SHIFT		3
-#define FIQ_EN_BIT		(1 << FIQ_EN_SHIFT)
-#define ACK_CTL			(1 << 2)
+#define FIQ_EN_BIT		BIT_32(FIQ_EN_SHIFT)
+#define ACK_CTL			BIT_32(2)
 
 /* GICC_IIDR bit masks and shifts */
 #define GICC_IIDR_PID_SHIFT	20
@@ -83,36 +83,36 @@
 #define GICC_IIDR_REV_SHIFT	12
 #define GICC_IIDR_IMP_SHIFT	0
 
-#define GICC_IIDR_PID_MASK	0xfff
-#define GICC_IIDR_ARCH_MASK	0xf
-#define GICC_IIDR_REV_MASK	0xf
-#define GICC_IIDR_IMP_MASK	0xfff
+#define GICC_IIDR_PID_MASK	U(0xfff)
+#define GICC_IIDR_ARCH_MASK	U(0xf)
+#define GICC_IIDR_REV_MASK	U(0xf)
+#define GICC_IIDR_IMP_MASK	U(0xfff)
 
 /* HYP view virtual CPU Interface registers */
-#define GICH_CTL		0x0
-#define GICH_VTR		0x4
-#define GICH_ELRSR0		0x30
-#define GICH_ELRSR1		0x34
-#define GICH_APR0		0xF0
-#define GICH_LR_BASE		0x100
+#define GICH_CTL		U(0x0)
+#define GICH_VTR		U(0x4)
+#define GICH_ELRSR0		U(0x30)
+#define GICH_ELRSR1		U(0x34)
+#define GICH_APR0		U(0xF0)
+#define GICH_LR_BASE		U(0x100)
 
 /* Virtual CPU Interface registers */
-#define GICV_CTL		0x0
-#define GICV_PRIMASK		0x4
-#define GICV_BP			0x8
-#define GICV_INTACK		0xC
-#define GICV_EOI		0x10
-#define GICV_RUNNINGPRI		0x14
-#define GICV_HIGHESTPEND	0x18
-#define GICV_DEACTIVATE		0x1000
+#define GICV_CTL		U(0x0)
+#define GICV_PRIMASK		U(0x4)
+#define GICV_BP			U(0x8)
+#define GICV_INTACK		U(0xC)
+#define GICV_EOI		U(0x10)
+#define GICV_RUNNINGPRI		U(0x14)
+#define GICV_HIGHESTPEND	U(0x18)
+#define GICV_DEACTIVATE		U(0x1000)
 
 /* GICD_CTLR bit definitions */
 #define CTLR_ENABLE_G1_SHIFT		1
-#define CTLR_ENABLE_G1_MASK		0x1
-#define CTLR_ENABLE_G1_BIT		(1 << CTLR_ENABLE_G1_SHIFT)
+#define CTLR_ENABLE_G1_MASK		U(0x1)
+#define CTLR_ENABLE_G1_BIT		BIT_32(CTLR_ENABLE_G1_SHIFT)
 
 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
-#define INT_ID_MASK		0x3ff
+#define INT_ID_MASK		U(0x3ff)
 
 #ifndef __ASSEMBLY__