Tegra186: helper functions for CPU rst handler and SMMU ctx offset
This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.
Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index 3ed2940..d609a14 100644
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -69,6 +69,8 @@
__tegra186_cpu_reset_handler_data:
.quad tegra_secure_entrypoint
.quad __BL31_END__ - BL31_BASE
+
+ .align 4
.globl __tegra186_smmu_context
__tegra186_smmu_context:
.rept TEGRA186_SMMU_CTX_SIZE
@@ -83,6 +85,7 @@
.globl tegra186_get_cpu_reset_handler_size
.globl tegra186_get_cpu_reset_handler_base
+ .globl tegra186_get_smmu_ctx_offset
/* return size of the CPU reset handler */
func tegra186_get_cpu_reset_handler_size
@@ -97,3 +100,11 @@
adr x0, tegra186_cpu_reset_handler
ret
endfunc tegra186_get_cpu_reset_handler_base
+
+/* return the size of the SMMU context */
+func tegra186_get_smmu_ctx_offset
+ adr x0, __tegra186_smmu_context
+ adr x1, tegra186_cpu_reset_handler
+ sub x0, x0, x1
+ ret
+endfunc tegra186_get_smmu_ctx_offset