| commit | 8a0a006af3362a114ed899f2cfe6c2ef0ec84061 | [log] [tgz] |
|---|---|---|
| author | Jit Loon Lim <jit.loon.lim@intel.com> | Tue Dec 24 10:50:58 2024 +0800 |
| committer | Jit Loon Lim <jit.loon.lim@altera.com> | Mon Feb 10 12:22:06 2025 +0800 |
| tree | f0f0f3e732db1711d38cc5b897167674b1fb4863 | |
| parent | 03a7a43e18927c876ef5f554e54fa11d252d4f7e [diff] |
fix(altera): add in support for agilex5 b0 jtag id Support Agilex5 B0 jtag id for fpga reconfig. Change-Id: I4efb5a046a0f11009a1f08412ff0e48f376c94e1 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>