tree f319247f7d10d65586d0eeae250de76f6d2c40dd
parent f68bc8a1c210bbdb36201a74528a96e93707eb45
author Chandni Cherukuri <chandni.cherukuri@arm.com> 1533193147 +0530
committer Chandni Cherukuri <chandni.cherukuri@arm.com> 1533293253 +0530

sgi: disable CPU power down bit in reset handler

On SGI platforms, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1'
register requires an explicit write to clear it for hotplug and
idle to function correctly. The reset value of this bit is zero
but it still requires this explicit clear to zero. This indicates
that this could be a model related issue but for now this issue can
be fixed be clearing the CORE_PWRDN_EN in the platform specific
reset handler function.

Change-Id: I4222930daa9a3abacdace6b7c3f4a5472ac0cb19
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>