)]}' { "commit": "91ffc1deffa2c1c64efe4dfaf27b78f2621a8b0b", "tree": "645977aec9eba2308e097af14ae5edfe21fb4fb1", "parents": [ "c1ad41fbf7d62b639b4aae387532b3a9f74851ed" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Thu Sep 24 16:01:12 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Jul 13 18:16:55 2021 +0200" }, "message": "fix(plat/st): improve DDR get size function\n\nAvoid parsing device tree every time when returning\nthe DDR size.\nA cache flush on this size is also added because TZC400 configuration\nis applied at the end of BL2 after MMU and data cache being turned off.\nConfiguration needs to retrieve the DDR size to generate the correct\nregion. Access to the size fails because the value is still in the data\ncache. Flushing the size is mandatory.\n\nChange-Id: I3dd1958f37d806f9c15a5d4151968935f6fe642e\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "6465c10e838031b3cdfe0b2cc4869e416e05b127", "old_mode": 33188, "old_path": "plat/st/common/stm32mp_dt.c", "new_id": "0b35646926f3b76628c99bbc63c928121f2b53ba", "new_mode": 33188, "new_path": "plat/st/common/stm32mp_dt.c" } ] }