)]}' { "commit": "95c26d6489bd8b2fc8b8e14bc2da5d2918055acc", "tree": "b0da6f86a7da0e387a7a11e864d394294c3b6711", "parents": [ "4d01bfe66522b13f0d9042206e986551c94fc01e" ], "author": { "name": "Marek Behún", "email": "marek.behun@nic.cz", "time": "Wed Dec 01 18:11:44 2021 +0100" }, "committer": { "name": "Marek Behún", "email": "marek.behun@nic.cz", "time": "Thu Dec 09 01:29:07 2021 +0100" }, "message": "fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics\n\nCurrently reg_set() and reg_set16() are implemented via\nmmio_clrsetbits_32(), meaning that first bits from mask are cleared,\nthen data bits are set.\n\nBut these function are used everywhere according to update semantics,\nwhere only those bits that are in mask are allowed to be changed.\n\nExample from phy-comphy-cp110.c\n mask \u003d HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;\n data \u003d 0x1 \u003c\u003c HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;\n /* Set PHY datapath width mode for V0 */\n mask |\u003d HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;\n data |\u003d 0x0 \u003c\u003c HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;\n /* Set Data bus width USB mode for V0 */\n mask |\u003d HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;\n data |\u003d 0x0 \u003c\u003c HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;\n /* Set CORE_CLK output frequency for 250Mhz */\n mask |\u003d HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;\n data |\u003d 0x0 \u003c\u003c HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;\n reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);\n\nChange the implementation to update semantics by anding data with mask.\n\nSigned-off-by: Marek Behún \u003cmarek.behun@nic.cz\u003e\nChange-Id: Ic72a8f64916274e08baef0b3f4c44a4fa07c1a6c\n", "tree_diff": [ { "type": "modify", "old_id": "c599437a3257b8acd1bf1735c6f8680ba49825d8", "old_mode": 33188, "old_path": "drivers/marvell/comphy/phy-comphy-common.h", "new_id": "ba5d255e881430c8360edd1848769c7f9b7e1f3c", "new_mode": 33188, "new_path": "drivers/marvell/comphy/phy-comphy-common.h" } ] }