plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
diff --git a/maintainers.rst b/maintainers.rst
index f53dda5..1f7d03e 100644
--- a/maintainers.rst
+++ b/maintainers.rst
@@ -93,6 +93,12 @@
:F: docs/plat/poplar.rst
:F: plat/hisilicon/poplar/
+Intel SocFPGA platform ports
+----------------------------
+:M: Tien Hock Loh <tien.hock.loh@intel.com>
+:G: `thloh85-intel`
+:F: plat/intel/soc
+
MediaTek platform ports
-----------------------
:M: Yidi Lin (林以廸) <yidi.lin@mediatek.com>