tree 37e91b6220d389baf4276e9c0ea05fea10c284f4
parent f0bfe15b81e50c6561a3a9a8e269db0267778910
author Loh Tien Hock <tien.hock.loh@intel.com> 1549268244 +0800
committer Loh Tien Hock <tien.hock.loh@intel.com> 1549268244 +0800

plat: intel: Add BL2 support for Stratix 10 SoC

This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>