context_mgmt: Fix MISRA defects
The macro EL_IMPLEMENTED() has been deprecated in favour of the new
function el_implemented().
Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index f037e18..39c27d0 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -68,7 +68,7 @@
gp_regs_t *gp_regs;
unsigned long sctlr_elx, actlr_elx;
- assert(ctx);
+ assert(ctx != NULL);
security_state = GET_SECURITY_STATE(ep->h.attr);
@@ -84,7 +84,7 @@
* the required value depending on the state of the SPSR_EL3 and the
* Security state and entrypoint attributes of the next EL.
*/
- scr_el3 = read_scr();
+ scr_el3 = (uint32_t)read_scr();
scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
SCR_ST_BIT | SCR_HCE_BIT);
/*
@@ -103,7 +103,7 @@
* Secure timer registers to EL3, from AArch64 state only, if specified
* by the entrypoint attributes.
*/
- if (EP_GET_ST(ep->h.attr))
+ if (EP_GET_ST(ep->h.attr) != 0U)
scr_el3 |= SCR_ST_BIT;
#if !HANDLE_EA_EL3_FIRST
@@ -133,10 +133,9 @@
* AArch64 and next EL is EL2, or if next execution state is AArch32 and
* next mode is Hyp.
*/
- if ((GET_RW(ep->spsr) == MODE_RW_64
- && GET_EL(ep->spsr) == MODE_EL2)
- || (GET_RW(ep->spsr) != MODE_RW_64
- && GET_M32(ep->spsr) == MODE32_hyp)) {
+ if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
+ || ((GET_RW(ep->spsr) != MODE_RW_64)
+ && (GET_M32(ep->spsr) == MODE32_hyp))) {
scr_el3 |= SCR_HCE_BIT;
}
@@ -151,7 +150,7 @@
* SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
* required by PSCI specification)
*/
- sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0;
+ sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
if (GET_RW(ep->spsr) == MODE_RW_64)
sctlr_elx |= SCTLR_EL1_RES1;
else {
@@ -291,20 +290,21 @@
uint32_t sctlr_elx, scr_el3, mdcr_el2;
cpu_context_t *ctx = cm_get_context(security_state);
bool el2_unused = false;
- uint64_t hcr_el2 = 0;
+ uint64_t hcr_el2 = 0U;
- assert(ctx);
+ assert(ctx != NULL);
if (security_state == NON_SECURE) {
- scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
- if (scr_el3 & SCR_HCE_BIT) {
+ scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx),
+ CTX_SCR_EL3);
+ if ((scr_el3 & SCR_HCE_BIT) != 0U) {
/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
- sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx),
- CTX_SCTLR_EL1);
+ sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx),
+ CTX_SCTLR_EL1);
sctlr_elx &= SCTLR_EE_BIT;
sctlr_elx |= SCTLR_EL2_RES1;
write_sctlr_el2(sctlr_elx);
- } else if (EL_IMPLEMENTED(2)) {
+ } else if (el_implemented(2) != EL_IMPL_NONE) {
el2_unused = true;
/*
@@ -314,7 +314,7 @@
* Set EL2 register width appropriately: Set HCR_EL2
* field to match SCR_EL3.RW.
*/
- if (scr_el3 & SCR_RW_BIT)
+ if ((scr_el3 & SCR_RW_BIT) != 0U)
hcr_el2 |= HCR_RW_BIT;
/*
@@ -470,7 +470,7 @@
cpu_context_t *ctx;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
el1_sysregs_context_save(get_sysregs_ctx(ctx));
@@ -487,7 +487,7 @@
cpu_context_t *ctx;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
el1_sysregs_context_restore(get_sysregs_ctx(ctx));
@@ -509,7 +509,7 @@
el3_state_t *state;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
/* Populate EL3 state so that ERET jumps to the correct entry */
state = get_el3state_ctx(ctx);
@@ -527,7 +527,7 @@
el3_state_t *state;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
/* Populate EL3 state so that ERET jumps to the correct entry */
state = get_el3state_ctx(ctx);
@@ -549,21 +549,21 @@
uint32_t scr_el3;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
/* Ensure that the bit position is a valid one */
- assert((1 << bit_pos) & SCR_VALID_BIT_MASK);
+ assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
/* Ensure that the 'value' is only a bit wide */
- assert(value <= 1);
+ assert(value <= 1U);
/*
* Get the SCR_EL3 value from the cpu context, clear the desired bit
* and set it to its new value.
*/
state = get_el3state_ctx(ctx);
- scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
- scr_el3 &= ~(1 << bit_pos);
+ scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
+ scr_el3 &= ~(1U << bit_pos);
scr_el3 |= value << bit_pos;
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
}
@@ -578,11 +578,11 @@
el3_state_t *state;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
/* Populate EL3 state so that ERET jumps to the correct entry */
state = get_el3state_ctx(ctx);
- return read_ctx_reg(state, CTX_SCR_EL3);
+ return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
}
/*******************************************************************************
@@ -595,7 +595,7 @@
cpu_context_t *ctx;
ctx = cm_get_context(security_state);
- assert(ctx);
+ assert(ctx != NULL);
cm_set_next_context(ctx);
}