Merge "feat(handoff): fix register convention r1/x1 value on transfer list" into integration
diff --git a/Makefile b/Makefile
index bbde1a7..819d774 100644
--- a/Makefile
+++ b/Makefile
@@ -1227,9 +1227,11 @@
ENABLE_FEAT_AMUv1p1 \
ENABLE_FEAT_CSV2_2 \
ENABLE_FEAT_CSV2_3 \
+ ENABLE_FEAT_DEBUGV8P9 \
ENABLE_FEAT_DIT \
ENABLE_FEAT_ECV \
ENABLE_FEAT_FGT \
+ ENABLE_FEAT_FGT2 \
ENABLE_FEAT_HCX \
ENABLE_FEAT_MTE2 \
ENABLE_FEAT_PAN \
@@ -1297,6 +1299,7 @@
AMU_RESTRICT_COUNTERS \
ENABLE_ASSERTIONS \
ENABLE_BTI \
+ ENABLE_FEAT_DEBUGV8P9 \
ENABLE_FEAT_MPAM \
ENABLE_PAUTH \
ENABLE_PIE \
@@ -1381,6 +1384,7 @@
ENABLE_MPMM \
ENABLE_MPMM_FCONF \
ENABLE_FEAT_FGT \
+ ENABLE_FEAT_FGT2 \
ENABLE_FEAT_ECV \
ENABLE_FEAT_AMUv1p1 \
ENABLE_FEAT_SEL2 \
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 40add91..7e9fde3 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -105,6 +105,10 @@
BL31_SOURCES += ${AMU_SOURCES}
endif
+ifneq (${ENABLE_FEAT_FGT2},0)
+BL31_SOURCES += lib/extensions/fgt/fgt2.c
+endif
+
ifeq (${ENABLE_MPMM},1)
BL31_SOURCES += ${MPMM_SOURCES}
endif
@@ -120,6 +124,10 @@
BL31_SOURCES += lib/extensions/mpam/mpam.c
endif
+ifneq (${ENABLE_FEAT_DEBUGV8P9},0)
+BL31_SOURCES += lib/extensions/debug/debugv8p9.c
+endif
+
ifneq (${ENABLE_TRBE_FOR_NS},0)
BL31_SOURCES += lib/extensions/trbe/trbe.c
endif
diff --git a/changelog.yaml b/changelog.yaml
index 6a235cd..c085ede 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -104,9 +104,15 @@
- title: Extended Translation Control Register (FEAT_TCR2).
scope: tcr2
+ - title: Fine-grained Traps 2 (FEAT_FGT2).
+ scope: fgt2
+
- title: CPU feature / ID register handling in general
scope: cpufeat
+ - title: Debug Extension (FEAT_Debugv8p9)
+ scope: debugv8p9
+
- title: Guarded Control Stack (FEAT_GCS)
scope: gcs
@@ -241,8 +247,8 @@
- title: RD-N2
scope: rdn2
- - title: RD-Fremont
- scope: rdfremont
+ - title: RD-V3
+ scope: rdv3
deprecated:
- board/rdn2
@@ -1428,6 +1434,16 @@
- title: Marvell Tools
scope: marvell-tools
+ - title: Renesas Tools
+ scope: renesas-tools
+
+ subsections:
+ - title: R-Car Layout Tool
+ scope: rcar-layout
+
+ - title: R/ZG Layout Tool
+ scope: rzg-layout
+
- title: Dependencies
scope: deps
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 8e3e3dd..9b9f7b4 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -94,6 +94,12 @@
ID_AA64PFR0_CSV2_MASK);
}
+static unsigned int read_feat_debugv8p9_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_DEBUGVER_SHIFT,
+ ID_AA64DFR0_DEBUGVER_MASK);
+}
+
static unsigned int read_feat_pmuv3_id_field(void)
{
return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT,
@@ -328,7 +334,8 @@
/* v8.6 features */
check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
"AMUv1p1", 2, 2);
- check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 1);
+ check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 2);
+ check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(), "FGT2", 2, 2);
check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", 1, 2);
check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(),
"TWED", 1, 1);
@@ -356,6 +363,8 @@
"S1POE", 1, 1);
check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(),
"CSV2_3", 3, 3);
+ check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(),
+ "DEBUGV8P9", 11, 11);
/* v9.0 features */
check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 52a9317..f59303e 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -320,6 +320,12 @@
The flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
+- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9``
+ extension which allows the ability to implement more than 16 breakpoints
+ and/or watchpoints. This feature is mandatory from v8.9 and is optional
+ from v8.8. This flag can take the values of 0 to 2, to align with the
+ ``ENABLE_FEAT`` mechanism. Default value is ``0``.
+
- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent
Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3.
``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4
@@ -340,6 +346,13 @@
This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
+- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2
+ (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers
+ during EL2 to EL3 context save/restore operations.
+ Its an optional architectural feature and is available from v8.8 and upwards.
+ This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
+ mechanism. Default value is ``0``.
+
- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to
allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a
diff --git a/docs/plat/mt8195.rst b/docs/plat/mt8195.rst
index b2aeea2..9810f9e 100644
--- a/docs/plat/mt8195.rst
+++ b/docs/plat/mt8195.rst
@@ -2,8 +2,8 @@
=============
MediaTek 8195 (MT8195) is a 64-bit ARM SoC introduced by MediaTek in 2021.
-The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
-Cortex-A76 can operate at up to 2.2 GHz.
+The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A78.
+Cortex-A78 can operate at up to 2.6 GHz.
Cortex-A55 can operate at up to 2.0 GHz.
Boot Sequence
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
new file mode 100644
index 0000000..7ae9624
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2020-2021, 2023-2024 NXP
+ */
+#ifndef S32CC_CLK_REGS_H
+#define S32CC_CLK_REGS_H
+
+#include <lib/utils_def.h>
+
+#define FXOSC_BASE_ADDR (0x40050000UL)
+
+/* FXOSC */
+#define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL)
+#define FXOSC_CTRL_OSC_BYP BIT_32(31U)
+#define FXOSC_CTRL_COMP_EN BIT_32(24U)
+#define FXOSC_CTRL_EOCV_OFFSET 16U
+#define FXOSC_CTRL_EOCV_MASK GENMASK_32(23U, FXOSC_CTRL_EOCV_OFFSET)
+#define FXOSC_CTRL_EOCV(VAL) (FXOSC_CTRL_EOCV_MASK & \
+ ((uint32_t)(VAL) << FXOSC_CTRL_EOCV_OFFSET))
+#define FXOSC_CTRL_GM_SEL_OFFSET 4U
+#define FXOSC_CTRL_GM_SEL_MASK GENMASK_32(7U, FXOSC_CTRL_GM_SEL_OFFSET)
+#define FXOSC_CTRL_GM_SEL(VAL) (FXOSC_CTRL_GM_SEL_MASK & \
+ ((uint32_t)(VAL) << FXOSC_CTRL_GM_SEL_OFFSET))
+#define FXOSC_CTRL_OSCON BIT_32(0U)
+
+#define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL)
+#define FXOSC_STAT_OSC_STAT BIT_32(31U)
+
+#endif /* S32CC_CLK_REGS_H */
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk.mk b/drivers/nxp/clk/s32cc/s32cc_clk.mk
index f5279d3..7a65ea6 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk.mk
+++ b/drivers/nxp/clk/s32cc/s32cc_clk.mk
@@ -6,6 +6,7 @@
PLAT_INCLUDES += \
-I${PLAT_DRIVERS_INCLUDE_PATH}/clk/s32cc \
+ -I${PLAT_DRIVERS_PATH}/clk/s32cc/include \
CLK_SOURCES := \
${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_drv.c \
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index e6653bd..f35a469 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -5,13 +5,20 @@
*/
#include <errno.h>
+#include <s32cc-clk-regs.h>
+
#include <common/debug.h>
#include <drivers/clk.h>
+#include <lib/mmio.h>
#include <s32cc-clk-modules.h>
#include <s32cc-clk-utils.h>
#define MAX_STACK_DEPTH (15U)
+struct s32cc_clk_drv {
+ uintptr_t fxosc_base;
+};
+
static int update_stack_depth(unsigned int *depth)
{
if (*depth == 0U) {
@@ -22,9 +29,151 @@
return 0;
}
+static struct s32cc_clk_drv *get_drv(void)
+{
+ static struct s32cc_clk_drv driver = {
+ .fxosc_base = FXOSC_BASE_ADDR,
+ };
+
+ return &driver;
+}
+
+static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth);
+
+static int enable_clk_module(const struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int *depth)
+{
+ const struct s32cc_clk *clk = s32cc_obj2clk(module);
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (clk == NULL) {
+ return -EINVAL;
+ }
+
+ if (clk->module != NULL) {
+ return enable_module(clk->module, depth);
+ }
+
+ if (clk->pclock != NULL) {
+ return enable_clk_module(&clk->pclock->desc, drv, depth);
+ }
+
+ return -EINVAL;
+}
+
+static void enable_fxosc(const struct s32cc_clk_drv *drv)
+{
+ uintptr_t fxosc_base = drv->fxosc_base;
+ uint32_t ctrl;
+
+ ctrl = mmio_read_32(FXOSC_CTRL(fxosc_base));
+ if ((ctrl & FXOSC_CTRL_OSCON) != U(0)) {
+ return;
+ }
+
+ ctrl = FXOSC_CTRL_COMP_EN;
+ ctrl &= ~FXOSC_CTRL_OSC_BYP;
+ ctrl |= FXOSC_CTRL_EOCV(0x1);
+ ctrl |= FXOSC_CTRL_GM_SEL(0x7);
+ mmio_write_32(FXOSC_CTRL(fxosc_base), ctrl);
+
+ /* Switch ON the crystal oscillator. */
+ mmio_setbits_32(FXOSC_CTRL(fxosc_base), FXOSC_CTRL_OSCON);
+
+ /* Wait until the clock is stable. */
+ while ((mmio_read_32(FXOSC_STAT(fxosc_base)) & FXOSC_STAT_OSC_STAT) == U(0)) {
+ }
+}
+
+static int enable_osc(const struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int *depth)
+{
+ const struct s32cc_osc *osc = s32cc_obj2osc(module);
+ int ret = 0;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ switch (osc->source) {
+ case S32CC_FXOSC:
+ enable_fxosc(drv);
+ break;
+ /* FIRC and SIRC oscillators are enabled by default */
+ case S32CC_FIRC:
+ break;
+ case S32CC_SIRC:
+ break;
+ default:
+ ERROR("Invalid oscillator %d\n", osc->source);
+ ret = -EINVAL;
+ break;
+ };
+
+ return ret;
+}
+
+static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth)
+{
+ const struct s32cc_clk_drv *drv = get_drv();
+ int ret = 0;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (drv == NULL) {
+ return -EINVAL;
+ }
+
+ switch (module->type) {
+ case s32cc_osc_t:
+ ret = enable_osc(module, drv, depth);
+ break;
+ case s32cc_clk_t:
+ ret = enable_clk_module(module, drv, depth);
+ break;
+ case s32cc_clkmux_t:
+ ret = -ENOTSUP;
+ break;
+ case s32cc_shared_clkmux_t:
+ ret = -ENOTSUP;
+ break;
+ case s32cc_pll_t:
+ ret = -ENOTSUP;
+ break;
+ case s32cc_pll_out_div_t:
+ case s32cc_fixed_div_t:
+ ret = -ENOTSUP;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
static int s32cc_clk_enable(unsigned long id)
{
- return -ENOTSUP;
+ unsigned int depth = MAX_STACK_DEPTH;
+ const struct s32cc_clk *clk;
+
+ clk = s32cc_get_arch_clk(id);
+ if (clk == NULL) {
+ return -EINVAL;
+ }
+
+ return enable_module(&clk->desc, &depth);
}
static void s32cc_clk_disable(unsigned long id)
@@ -97,6 +246,100 @@
return -EINVAL;
}
+static int set_pll_freq(const struct s32cc_clk_obj *module, unsigned long rate,
+ unsigned long *orate, unsigned int *depth)
+{
+ struct s32cc_pll *pll = s32cc_obj2pll(module);
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if ((pll->vco_freq != 0UL) && (pll->vco_freq != rate)) {
+ ERROR("PLL frequency was already set\n");
+ return -EINVAL;
+ }
+
+ pll->vco_freq = rate;
+ *orate = pll->vco_freq;
+
+ return 0;
+}
+
+static int set_pll_div_freq(const struct s32cc_clk_obj *module, unsigned long rate,
+ unsigned long *orate, unsigned int *depth)
+{
+ struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
+ const struct s32cc_pll *pll;
+ unsigned long prate, dc;
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (pdiv->parent == NULL) {
+ ERROR("Failed to identify PLL divider's parent\n");
+ return -EINVAL;
+ }
+
+ pll = s32cc_obj2pll(pdiv->parent);
+ if (pll == NULL) {
+ ERROR("The parent of the PLL DIV is invalid\n");
+ return -EINVAL;
+ }
+
+ prate = pll->vco_freq;
+
+ /**
+ * The PLL is not initialized yet, so let's take a risk
+ * and accept the proposed rate.
+ */
+ if (prate == 0UL) {
+ pdiv->freq = rate;
+ *orate = rate;
+ return 0;
+ }
+
+ /* Decline in case the rate cannot fit PLL's requirements. */
+ dc = prate / rate;
+ if ((prate / dc) != rate) {
+ return -EINVAL;
+ }
+
+ pdiv->freq = rate;
+ *orate = pdiv->freq;
+
+ return 0;
+}
+
+static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long rate,
+ unsigned long *orate, unsigned int *depth)
+{
+ const struct s32cc_fixed_div *fdiv = s32cc_obj2fixeddiv(module);
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (fdiv->parent == NULL) {
+ ERROR("The divider doesn't have a valid parent\b");
+ return -EINVAL;
+ }
+
+ ret = set_module_rate(fdiv->parent, rate * fdiv->rate_div, orate, depth);
+
+ /* Update the output rate based on the parent's rate */
+ *orate /= fdiv->rate_div;
+
+ return ret;
+}
+
static int set_module_rate(const struct s32cc_clk_obj *module,
unsigned long rate, unsigned long *orate,
unsigned int *depth)
@@ -115,6 +358,19 @@
case s32cc_osc_t:
ret = set_osc_freq(module, rate, orate, depth);
break;
+ case s32cc_pll_t:
+ ret = set_pll_freq(module, rate, orate, depth);
+ break;
+ case s32cc_pll_out_div_t:
+ ret = set_pll_div_freq(module, rate, orate, depth);
+ break;
+ case s32cc_fixed_div_t:
+ ret = set_fixed_div_freq(module, rate, orate, depth);
+ break;
+ case s32cc_clkmux_t:
+ case s32cc_shared_clkmux_t:
+ ret = -ENOTSUP;
+ break;
default:
ret = -EINVAL;
break;
@@ -151,7 +407,49 @@
static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id)
{
- return -ENOTSUP;
+ const struct s32cc_clk *parent;
+ const struct s32cc_clk *clk;
+ bool valid_source = false;
+ struct s32cc_clkmux *mux;
+ uint8_t i;
+
+ clk = s32cc_get_arch_clk(id);
+ if (clk == NULL) {
+ return -EINVAL;
+ }
+
+ parent = s32cc_get_arch_clk(parent_id);
+ if (parent == NULL) {
+ return -EINVAL;
+ }
+
+ if (!is_s32cc_clk_mux(clk)) {
+ ERROR("Clock %lu is not a mux\n", id);
+ return -EINVAL;
+ }
+
+ mux = s32cc_clk2mux(clk);
+ if (mux == NULL) {
+ ERROR("Failed to cast clock %lu to clock mux\n", id);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < mux->nclks; i++) {
+ if (mux->clkids[i] == parent_id) {
+ valid_source = true;
+ break;
+ }
+ }
+
+ if (!valid_source) {
+ ERROR("Clock %lu is not a valid clock for mux %lu\n",
+ parent_id, id);
+ return -EINVAL;
+ }
+
+ mux->source_id = parent_id;
+
+ return 0;
}
void s32cc_clk_register_drv(void)
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
index f8fc52f..039db2a 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
@@ -7,6 +7,9 @@
#include <s32cc-clk-modules.h>
#include <s32cc-clk-utils.h>
+#define S32CC_A53_MIN_FREQ (48UL * MHZ)
+#define S32CC_A53_MAX_FREQ (1000UL * MHZ)
+
/* Oscillators */
static struct s32cc_osc fxosc =
S32CC_OSC_INIT(S32CC_FXOSC);
@@ -23,11 +26,55 @@
static struct s32cc_clk sirc_clk =
S32CC_MODULE_CLK(sirc);
-static struct s32cc_clk *s32cc_hw_clk_list[3] = {
+/* ARM PLL */
+static struct s32cc_clkmux arm_pll_mux =
+ S32CC_CLKMUX_INIT(S32CC_ARM_PLL, 0, 2,
+ S32CC_CLK_FIRC,
+ S32CC_CLK_FXOSC, 0, 0, 0);
+static struct s32cc_clk arm_pll_mux_clk =
+ S32CC_MODULE_CLK(arm_pll_mux);
+static struct s32cc_pll armpll =
+ S32CC_PLL_INIT(arm_pll_mux_clk, S32CC_ARM_PLL, 2);
+static struct s32cc_clk arm_pll_vco_clk =
+ S32CC_FREQ_MODULE_CLK(armpll, 1400 * MHZ, 2000 * MHZ);
+
+static struct s32cc_pll_out_div arm_pll_phi0_div =
+ S32CC_PLL_OUT_DIV_INIT(armpll, 0);
+static struct s32cc_clk arm_pll_phi0_clk =
+ S32CC_FREQ_MODULE_CLK(arm_pll_phi0_div, 0, GHZ);
+
+/* MC_CGM1 */
+static struct s32cc_clkmux cgm1_mux0 =
+ S32CC_SHARED_CLKMUX_INIT(S32CC_CGM1, 0, 3,
+ S32CC_CLK_FIRC,
+ S32CC_CLK_ARM_PLL_PHI0,
+ S32CC_CLK_ARM_PLL_DFS2, 0, 0);
+static struct s32cc_clk cgm1_mux0_clk = S32CC_MODULE_CLK(cgm1_mux0);
+
+/* A53_CORE */
+static struct s32cc_clk a53_core_clk =
+ S32CC_FREQ_MODULE_CLK(cgm1_mux0_clk, S32CC_A53_MIN_FREQ,
+ S32CC_A53_MAX_FREQ);
+/* A53_CORE_DIV2 */
+static struct s32cc_fixed_div a53_core_div2 =
+ S32CC_FIXED_DIV_INIT(cgm1_mux0_clk, 2);
+static struct s32cc_clk a53_core_div2_clk =
+ S32CC_FREQ_MODULE_CLK(a53_core_div2, S32CC_A53_MIN_FREQ / 2,
+ S32CC_A53_MAX_FREQ / 2);
+/* A53_CORE_DIV10 */
+static struct s32cc_fixed_div a53_core_div10 =
+ S32CC_FIXED_DIV_INIT(cgm1_mux0_clk, 10);
+static struct s32cc_clk a53_core_div10_clk =
+ S32CC_FREQ_MODULE_CLK(a53_core_div10, S32CC_A53_MIN_FREQ / 10,
+ S32CC_A53_MAX_FREQ / 10);
+
+static struct s32cc_clk *s32cc_hw_clk_list[5] = {
/* Oscillators */
[S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
[S32CC_CLK_ID(S32CC_CLK_SIRC)] = &sirc_clk,
[S32CC_CLK_ID(S32CC_CLK_FXOSC)] = &fxosc_clk,
+ /* ARM PLL */
+ [S32CC_CLK_ID(S32CC_CLK_ARM_PLL_PHI0)] = &arm_pll_phi0_clk,
};
static struct s32cc_clk_array s32cc_hw_clocks = {
@@ -36,10 +83,29 @@
.n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
};
+static struct s32cc_clk *s32cc_arch_clk_list[6] = {
+ /* ARM PLL */
+ [S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
+ [S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
+ /* MC_CGM1 */
+ [S32CC_CLK_ID(S32CC_CLK_MC_CGM1_MUX0)] = &cgm1_mux0_clk,
+ /* A53 */
+ [S32CC_CLK_ID(S32CC_CLK_A53_CORE)] = &a53_core_clk,
+ [S32CC_CLK_ID(S32CC_CLK_A53_CORE_DIV2)] = &a53_core_div2_clk,
+ [S32CC_CLK_ID(S32CC_CLK_A53_CORE_DIV10)] = &a53_core_div10_clk,
+};
+
+static struct s32cc_clk_array s32cc_arch_clocks = {
+ .type_mask = S32CC_CLK_TYPE(S32CC_CLK_ARM_PLL_MUX),
+ .clks = &s32cc_arch_clk_list[0],
+ .n_clks = ARRAY_SIZE(s32cc_arch_clk_list),
+};
+
struct s32cc_clk *s32cc_get_arch_clk(unsigned long id)
{
- static const struct s32cc_clk_array *clk_table[1] = {
+ static const struct s32cc_clk_array *clk_table[2] = {
&s32cc_hw_clocks,
+ &s32cc_arch_clocks,
};
return s32cc_get_clk_from_table(clk_table, ARRAY_SIZE(clk_table), id);
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index fc1dc02..ac1f7d0 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -9,6 +9,8 @@
#include <s32cc-clk-utils.h>
#define S32CC_FXOSC_FREQ (40U * MHZ)
+#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
+#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
int s32cc_init_early_clks(void)
{
@@ -16,10 +18,35 @@
s32cc_clk_register_drv();
+ ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0);
+ if (ret != 0) {
+ return ret;
+ }
+
ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
if (ret != 0) {
return ret;
}
+ ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_FXOSC);
+ if (ret != 0) {
+ return ret;
+ }
+
return ret;
}
diff --git a/drivers/st/clk/clk-stm32mp2.c b/drivers/st/clk/clk-stm32mp2.c
new file mode 100644
index 0000000..12839f1
--- /dev/null
+++ b/drivers/st/clk/clk-stm32mp2.c
@@ -0,0 +1,2357 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <limits.h>
+#include <stdint.h>
+
+#include "clk-stm32-core.h"
+#include <common/fdt_wrappers.h>
+#include <drivers/clk.h>
+#include <drivers/delay_timer.h>
+#include <drivers/generic_delay_timer.h>
+#include <drivers/st/stm32mp2_clk.h>
+#include <drivers/st/stm32mp_clkfunc.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+#include <lib/utils_def.h>
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+struct stm32_osci_dt_cfg {
+ unsigned long freq;
+ uint32_t drive;
+ bool bypass;
+ bool digbyp;
+ bool css;
+};
+
+struct stm32_pll_dt_cfg {
+ uint32_t src;
+ uint32_t frac;
+ uint32_t cfg[PLLCFG_NB];
+ uint32_t csg[PLLCSG_NB];
+ bool csg_enabled;
+ bool enabled;
+};
+
+struct stm32_clk_platdata {
+ uintptr_t rcc_base;
+ uint32_t nosci;
+ struct stm32_osci_dt_cfg *osci;
+ uint32_t npll;
+ struct stm32_pll_dt_cfg *pll;
+ uint32_t nflexgen;
+ uint32_t *flexgen;
+ uint32_t nbusclk;
+ uint32_t *busclk;
+ uint32_t nkernelclk;
+ uint32_t *kernelclk;
+};
+
+/* A35 Sub-System which manages its own PLL (PLL1) */
+#define A35_SS_CHGCLKREQ 0x0000
+#define A35_SS_PLL_FREQ1 0x0080
+#define A35_SS_PLL_FREQ2 0x0090
+#define A35_SS_PLL_ENABLE 0x00a0
+
+#define A35_SS_CHGCLKREQ_ARM_CHGCLKREQ BIT(0)
+#define A35_SS_CHGCLKREQ_ARM_CHGCLKACK BIT(1)
+
+#define A35_SS_PLL_FREQ1_FBDIV_MASK GENMASK(11, 0)
+#define A35_SS_PLL_FREQ1_FBDIV_SHIFT 0
+#define A35_SS_PLL_FREQ1_REFDIV_MASK GENMASK(21, 16)
+#define A35_SS_PLL_FREQ1_REFDIV_SHIFT 16
+
+#define A35_SS_PLL_FREQ2_POSTDIV1_MASK GENMASK(2, 0)
+#define A35_SS_PLL_FREQ2_POSTDIV1_SHIFT 0
+#define A35_SS_PLL_FREQ2_POSTDIV2_MASK GENMASK(5, 3)
+#define A35_SS_PLL_FREQ2_POSTDIV2_SHIFT 3
+
+#define A35_SS_PLL_ENABLE_PD BIT(0)
+#define A35_SS_PLL_ENABLE_LOCKP BIT(1)
+#define A35_SS_PLL_ENABLE_NRESET_SWPLL_FF BIT(2)
+
+#define TIMEOUT_US_200MS U(200000)
+#define TIMEOUT_US_1S U(1000000)
+
+#define PLLRDY_TIMEOUT TIMEOUT_US_200MS
+#define CLKSRC_TIMEOUT TIMEOUT_US_200MS
+#define CLKDIV_TIMEOUT TIMEOUT_US_200MS
+#define OSCRDY_TIMEOUT TIMEOUT_US_1S
+
+/* PLL minimal frequencies for clock sources */
+#define PLL_REFCLK_MIN UL(5000000)
+#define PLL_FRAC_REFCLK_MIN UL(10000000)
+
+#define XBAR_CHANNEL_NB 64
+
+/* Warning, should be start to 1 */
+enum clock {
+ _CK_0_MHZ,
+
+ /* ROOT CLOCKS */
+ _CK_HSI,
+ _CK_HSE,
+ _CK_MSI,
+ _CK_LSI,
+ _CK_LSE,
+ _I2SCKIN,
+ _SPDIFSYMB,
+ _CK_PLL1,
+ _CK_PLL2,
+ _CK_PLL3,
+ _CK_PLL4,
+ _CK_PLL5,
+ _CK_PLL6,
+ _CK_PLL7,
+ _CK_PLL8,
+ _CK_HSE_RTC,
+ _CK_RTCCK,
+ _CK_ICN_HS_MCU,
+ _CK_ICN_SDMMC,
+ _CK_ICN_DDR,
+ _CK_ICN_HSL,
+ _CK_ICN_NIC,
+ _CK_ICN_LS_MCU,
+ _CK_FLEXGEN_07,
+ _CK_FLEXGEN_08,
+ _CK_FLEXGEN_09,
+ _CK_FLEXGEN_10,
+ _CK_FLEXGEN_11,
+ _CK_FLEXGEN_12,
+ _CK_FLEXGEN_13,
+ _CK_FLEXGEN_14,
+ _CK_FLEXGEN_15,
+ _CK_FLEXGEN_16,
+ _CK_FLEXGEN_17,
+ _CK_FLEXGEN_18,
+ _CK_FLEXGEN_19,
+ _CK_FLEXGEN_20,
+ _CK_FLEXGEN_21,
+ _CK_FLEXGEN_22,
+ _CK_FLEXGEN_23,
+ _CK_FLEXGEN_24,
+ _CK_FLEXGEN_25,
+ _CK_FLEXGEN_26,
+ _CK_FLEXGEN_27,
+ _CK_FLEXGEN_28,
+ _CK_FLEXGEN_29,
+ _CK_FLEXGEN_30,
+ _CK_FLEXGEN_31,
+ _CK_FLEXGEN_32,
+ _CK_FLEXGEN_33,
+ _CK_FLEXGEN_34,
+ _CK_FLEXGEN_35,
+ _CK_FLEXGEN_36,
+ _CK_FLEXGEN_37,
+ _CK_FLEXGEN_38,
+ _CK_FLEXGEN_39,
+ _CK_FLEXGEN_40,
+ _CK_FLEXGEN_41,
+ _CK_FLEXGEN_42,
+ _CK_FLEXGEN_43,
+ _CK_FLEXGEN_44,
+ _CK_FLEXGEN_45,
+ _CK_FLEXGEN_46,
+ _CK_FLEXGEN_47,
+ _CK_FLEXGEN_48,
+ _CK_FLEXGEN_49,
+ _CK_FLEXGEN_50,
+ _CK_FLEXGEN_51,
+ _CK_FLEXGEN_52,
+ _CK_FLEXGEN_53,
+ _CK_FLEXGEN_54,
+ _CK_FLEXGEN_55,
+ _CK_FLEXGEN_56,
+ _CK_FLEXGEN_57,
+ _CK_FLEXGEN_58,
+ _CK_FLEXGEN_59,
+ _CK_FLEXGEN_60,
+ _CK_FLEXGEN_61,
+ _CK_FLEXGEN_62,
+ _CK_FLEXGEN_63,
+ _CK_ICN_APB1,
+ _CK_ICN_APB2,
+ _CK_ICN_APB3,
+ _CK_ICN_APB4,
+ _CK_ICN_APBDBG,
+ _CK_BKPSRAM,
+ _CK_BSEC,
+ _CK_CRC,
+ _CK_CRYP1,
+ _CK_CRYP2,
+ _CK_DDR,
+ _CK_DDRCAPB,
+ _CK_DDRCP,
+ _CK_DDRPHYC,
+ _CK_FMC,
+ _CK_GPIOA,
+ _CK_GPIOB,
+ _CK_GPIOC,
+ _CK_GPIOD,
+ _CK_GPIOE,
+ _CK_GPIOF,
+ _CK_GPIOG,
+ _CK_GPIOH,
+ _CK_GPIOI,
+ _CK_GPIOJ,
+ _CK_GPIOK,
+ _CK_GPIOZ,
+ _CK_HASH,
+ _CK_I2C1,
+ _CK_I2C2,
+ _CK_I2C3,
+ _CK_I2C4,
+ _CK_I2C5,
+ _CK_I2C6,
+ _CK_I2C7,
+ _CK_I2C8,
+ _CK_IWDG1,
+ _CK_IWDG2,
+ _CK_OSPI1,
+ _CK_OSPI2,
+ _CK_OSPIIOM,
+ _CK_PKA,
+ _CK_RETRAM,
+ _CK_RNG,
+ _CK_RTC,
+ _CK_SAES,
+ _CK_SDMMC1,
+ _CK_SDMMC2,
+ _CK_SRAM1,
+ _CK_SRAM2,
+ _CK_STGEN,
+ _CK_SYSCPU1,
+ _CK_SYSRAM,
+ _CK_UART4,
+ _CK_UART5,
+ _CK_UART7,
+ _CK_UART8,
+ _CK_UART9,
+ _CK_USART1,
+ _CK_USART2,
+ _CK_USART3,
+ _CK_USART6,
+ _CK_USB2EHCI,
+ _CK_USB2OHCI,
+ _CK_USB2PHY1,
+ _CK_USB2PHY2,
+ _CK_USB3DR,
+ _CK_USB3PCIEPHY,
+ _CK_USBTC,
+
+ CK_LAST
+};
+
+static const uint16_t muxsel_src[] = {
+ _CK_HSI, _CK_HSE, _CK_MSI, _CK_0_MHZ
+};
+
+static const uint16_t xbarsel_src[] = {
+ _CK_PLL4, _CK_PLL5, _CK_PLL6, _CK_PLL7, _CK_PLL8,
+ _CK_HSI, _CK_HSE, _CK_MSI, _CK_HSI, _CK_HSE, _CK_MSI,
+ _SPDIFSYMB, _I2SCKIN, _CK_LSI, _CK_LSE
+};
+
+static const uint16_t rtc_src[] = {
+ _CK_0_MHZ, _CK_LSE, _CK_LSI, _CK_HSE_RTC
+};
+
+static const uint16_t usb2phy1_src[] = {
+ _CK_FLEXGEN_57, _CK_HSE
+};
+
+static const uint16_t usb2phy2_src[] = {
+ _CK_FLEXGEN_58, _CK_HSE
+};
+
+static const uint16_t usb3pciphy_src[] = {
+ _CK_FLEXGEN_34, _CK_HSE
+};
+
+static const uint16_t d3per_src[] = {
+ _CK_MSI, _CK_LSI, _CK_LSE
+};
+
+#define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\
+ .id_parents = src,\
+ .num_parents = ARRAY_SIZE(src),\
+ .mux = &(struct mux_cfg) {\
+ .offset = (_offset),\
+ .shift = (_shift),\
+ .width = (_witdh),\
+ .bitrdy = UINT8_MAX,\
+ },\
+}
+
+static const struct parent_cfg parent_mp25[] = {
+ MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2),
+ MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2),
+ MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2),
+ MUX_CONF(MUX_MUXSEL3, muxsel_src, RCC_MUXSELCFGR, 12, 2),
+ MUX_CONF(MUX_MUXSEL4, muxsel_src, RCC_MUXSELCFGR, 16, 2),
+ MUX_CONF(MUX_MUXSEL5, muxsel_src, RCC_MUXSELCFGR, 20, 2),
+ MUX_CONF(MUX_MUXSEL6, muxsel_src, RCC_MUXSELCFGR, 24, 2),
+ MUX_CONF(MUX_MUXSEL7, muxsel_src, RCC_MUXSELCFGR, 28, 2),
+ MUX_CONF(MUX_XBARSEL, xbarsel_src, RCC_XBAR0CFGR, 0, 4),
+ MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2),
+ MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1),
+ MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1),
+ MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1),
+ MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2),
+};
+
+/* GATES */
+enum enum_gate_cfg {
+ GATE_ZERO, /* reserved for no gate */
+ GATE_LSE,
+ GATE_RTCCK,
+ GATE_LSI,
+ GATE_HSI,
+ GATE_MSI,
+ GATE_HSE,
+ GATE_LSI_RDY,
+ GATE_MSI_RDY,
+ GATE_LSE_RDY,
+ GATE_HSE_RDY,
+ GATE_HSI_RDY,
+ GATE_SYSRAM,
+ GATE_RETRAM,
+ GATE_SRAM1,
+ GATE_SRAM2,
+
+ GATE_DDRPHYC,
+ GATE_SYSCPU1,
+ GATE_CRC,
+ GATE_OSPIIOM,
+ GATE_BKPSRAM,
+ GATE_HASH,
+ GATE_RNG,
+ GATE_CRYP1,
+ GATE_CRYP2,
+ GATE_SAES,
+ GATE_PKA,
+
+ GATE_GPIOA,
+ GATE_GPIOB,
+ GATE_GPIOC,
+ GATE_GPIOD,
+ GATE_GPIOE,
+ GATE_GPIOF,
+ GATE_GPIOG,
+ GATE_GPIOH,
+ GATE_GPIOI,
+ GATE_GPIOJ,
+ GATE_GPIOK,
+ GATE_GPIOZ,
+ GATE_RTC,
+
+ GATE_DDRCP,
+
+ /* WARNING 2 CLOCKS FOR ONE GATE */
+ GATE_USB2OHCI,
+ GATE_USB2EHCI,
+
+ GATE_USB3DR,
+
+ GATE_BSEC,
+ GATE_IWDG1,
+ GATE_IWDG2,
+
+ GATE_DDRCAPB,
+ GATE_DDR,
+
+ GATE_USART2,
+ GATE_UART4,
+ GATE_USART3,
+ GATE_UART5,
+ GATE_I2C1,
+ GATE_I2C2,
+ GATE_I2C3,
+ GATE_I2C5,
+ GATE_I2C4,
+ GATE_I2C6,
+ GATE_I2C7,
+ GATE_USART1,
+ GATE_USART6,
+ GATE_UART7,
+ GATE_UART8,
+ GATE_UART9,
+ GATE_STGEN,
+ GATE_USB3PCIEPHY,
+ GATE_USBTC,
+ GATE_I2C8,
+ GATE_OSPI1,
+ GATE_OSPI2,
+ GATE_FMC,
+ GATE_SDMMC1,
+ GATE_SDMMC2,
+ GATE_USB2PHY1,
+ GATE_USB2PHY2,
+ LAST_GATE
+};
+
+#define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\
+ .offset = (_offset),\
+ .bit_idx = (_bit_idx),\
+ .set_clr = (_offset_clr),\
+}
+
+static const struct gate_cfg gates_mp25[LAST_GATE] = {
+ GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
+ GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0),
+ GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
+ GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1),
+ GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1),
+ GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0),
+
+ GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0),
+ GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
+ GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0),
+ GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0),
+ GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0),
+ GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0),
+ GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0),
+ GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0),
+ GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0),
+ GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCAPBCFGR, 1, 0),
+ GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0),
+ GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
+ GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),
+ GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0),
+ GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),
+ GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),
+ GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
+ GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
+ GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
+ GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),
+ GATE_CFG(GATE_GPIOA, RCC_GPIOACFGR, 1, 0),
+ GATE_CFG(GATE_GPIOB, RCC_GPIOBCFGR, 1, 0),
+ GATE_CFG(GATE_GPIOC, RCC_GPIOCCFGR, 1, 0),
+ GATE_CFG(GATE_GPIOD, RCC_GPIODCFGR, 1, 0),
+ GATE_CFG(GATE_GPIOE, RCC_GPIOECFGR, 1, 0),
+ GATE_CFG(GATE_GPIOF, RCC_GPIOFCFGR, 1, 0),
+ GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0),
+ GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0),
+ GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0),
+ GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0),
+ GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0),
+ GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0),
+ GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0),
+ GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0),
+
+ /* WARNING 2 CLOCKS FOR ONE GATE */
+ GATE_CFG(GATE_USB2OHCI, RCC_USB2CFGR, 1, 0),
+ GATE_CFG(GATE_USB2EHCI, RCC_USB2CFGR, 1, 0),
+ GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),
+ GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0),
+ GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
+ GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
+ GATE_CFG(GATE_DDRCAPB, RCC_DDRCAPBCFGR, 1, 0),
+ GATE_CFG(GATE_DDR, RCC_DDRCFGR, 1, 0),
+ GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),
+ GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),
+ GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),
+ GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
+ GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
+ GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
+ GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
+ GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),
+ GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),
+ GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),
+ GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),
+ GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
+ GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
+ GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
+ GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),
+ GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),
+ GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0),
+ GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),
+ GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0),
+ GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),
+ GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0),
+ GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0),
+ GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0),
+ GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
+ GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
+ GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),
+ GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),
+};
+
+static const struct clk_div_table apb_div_table[] = {
+ { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, { 4, 16 },
+ { 5, 16 }, { 6, 16 }, { 7, 16 }, { 0 },
+};
+
+#undef DIV_CFG
+#define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\
+ .offset = _offset,\
+ .shift = _shift,\
+ .width = _width,\
+ .flags = _flags,\
+ .table = _table,\
+ .bitrdy = _bitrdy,\
+}
+
+static const struct div_cfg dividers_mp25[] = {
+ DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
+ DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
+ DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
+ DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
+ DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31),
+ DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31),
+ DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0),
+};
+
+enum stm32_osc {
+ OSC_HSI,
+ OSC_HSE,
+ OSC_MSI,
+ OSC_LSI,
+ OSC_LSE,
+ OSC_I2SCKIN,
+ OSC_SPDIFSYMB,
+ NB_OSCILLATOR
+};
+
+static struct clk_oscillator_data stm32mp25_osc_data[] = {
+ OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY,
+ NULL, NULL, NULL),
+
+ OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY,
+ NULL, NULL, NULL),
+
+ OSCILLATOR(OSC_MSI, _CK_MSI, "clk-msi", GATE_MSI, GATE_MSI_RDY,
+ NULL, NULL, NULL),
+
+ OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY,
+ BYPASS(RCC_OCENSETR, 10, 7),
+ CSS(RCC_OCENSETR, 11),
+ NULL),
+
+ OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY,
+ BYPASS(RCC_BDCR, 1, 3),
+ CSS(RCC_BDCR, 8),
+ DRIVE(RCC_BDCR, 4, 2, 2)),
+
+ OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE,
+ NULL, NULL, NULL),
+
+ OSCILLATOR(OSC_SPDIFSYMB, _SPDIFSYMB, "spdif_symb", NO_GATE, NO_GATE,
+ NULL, NULL, NULL),
+};
+
+#ifdef IMAGE_BL2
+static const char *clk_stm32_get_oscillator_name(enum stm32_osc id)
+{
+ if (id < NB_OSCILLATOR) {
+ return stm32mp25_osc_data[id].name;
+ }
+
+ return NULL;
+}
+#endif
+
+enum pll_id {
+ _PLL1,
+ _PLL2,
+ _PLL3,
+ _PLL4,
+ _PLL5,
+ _PLL6,
+ _PLL7,
+ _PLL8,
+ _PLL_NB
+};
+
+/* PLL configuration registers offsets from RCC_PLLxCFGR1 */
+#define RCC_OFFSET_PLLXCFGR1 0x00
+#define RCC_OFFSET_PLLXCFGR2 0x04
+#define RCC_OFFSET_PLLXCFGR3 0x08
+#define RCC_OFFSET_PLLXCFGR4 0x0C
+#define RCC_OFFSET_PLLXCFGR5 0x10
+#define RCC_OFFSET_PLLXCFGR6 0x18
+#define RCC_OFFSET_PLLXCFGR7 0x1C
+
+struct stm32_clk_pll {
+ uint16_t clk_id;
+ uint16_t reg_pllxcfgr1;
+};
+
+#define CLK_PLL_CFG(_idx, _clk_id, _reg)\
+ [(_idx)] = {\
+ .clk_id = (_clk_id),\
+ .reg_pllxcfgr1 = (_reg),\
+ }
+
+static const struct stm32_clk_pll stm32mp25_clk_pll[_PLL_NB] = {
+ CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ),
+ CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1),
+ CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1),
+ CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1),
+ CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1),
+ CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1),
+ CLK_PLL_CFG(_PLL7, _CK_PLL7, RCC_PLL7CFGR1),
+ CLK_PLL_CFG(_PLL8, _CK_PLL8, RCC_PLL8CFGR1),
+};
+
+static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx)
+{
+ return &stm32mp25_clk_pll[idx];
+}
+
+static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv,
+ const struct stm32_clk_pll *pll,
+ unsigned long prate)
+{
+ unsigned long refclk, fvco;
+ uint32_t fracin, fbdiv, refdiv;
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+ uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;
+ uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
+
+ refclk = prate;
+
+ fracin = mmio_read_32(pllxcfgr3) & RCC_PLLxCFGR3_FRACIN_MASK;
+ fbdiv = (mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >>
+ RCC_PLLxCFGR2_FBDIV_SHIFT;
+ refdiv = mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK;
+
+ if (fracin != 0U) {
+ uint64_t numerator, denominator;
+
+ numerator = ((uint64_t)fbdiv << 24) + fracin;
+ numerator = refclk * numerator;
+ denominator = (uint64_t)refdiv << 24;
+ fvco = (unsigned long)(numerator / denominator);
+ } else {
+ fvco = (unsigned long)(refclk * fbdiv / refdiv);
+ }
+
+ return fvco;
+}
+
+struct stm32_pll_cfg {
+ uint16_t pll_id;
+};
+
+static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
+{
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+
+ return ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLEN) != 0U);
+}
+
+static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
+{
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+
+ mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);
+}
+
+static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
+{
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+
+ /* Stop PLL */
+ mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);
+}
+
+static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv,
+ const struct stm32_clk_pll *pll)
+{
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+ uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
+
+ /* Wait PLL lock */
+ while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) == 0U) {
+ if (timeout_elapsed(timeout)) {
+ ERROR("PLL%d start failed @ 0x%x: 0x%x\n",
+ pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcfgr1,
+ mmio_read_32(pllxcfgr1));
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv,
+ const struct stm32_clk_pll *pll)
+{
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+ uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
+
+ /* Wait PLL stopped */
+ while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_PLLRDY) != 0U) {
+ if (timeout_elapsed(timeout)) {
+ ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n",
+ pll->clk_id - _CK_PLL1 + 1, pllxcfgr1, mmio_read_32(pllxcfgr1));
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
+{
+ if (_clk_stm32_pll_is_enabled(priv, pll)) {
+ return 0;
+ }
+
+ _clk_stm32_pll_set_on(priv, pll);
+
+ return _clk_stm32_pll_wait_ready_on(priv, pll);
+}
+
+static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)
+{
+ if (!_clk_stm32_pll_is_enabled(priv, pll)) {
+ return;
+ }
+
+ _clk_stm32_pll_set_off(priv, pll);
+
+ _clk_stm32_pll_wait_ready_off(priv, pll);
+}
+
+static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, id);
+ struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
+ const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);
+
+ return _clk_stm32_pll_is_enabled(priv, pll);
+}
+
+static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, id);
+ struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
+ const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);
+
+ return _clk_stm32_pll_enable(priv, pll);
+}
+
+static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, id);
+ struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
+ const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);
+
+ _clk_stm32_pll_disable(priv, pll);
+}
+
+static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id,
+ unsigned long prate)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, id);
+ struct stm32_pll_cfg *pll_cfg = clk->clock_cfg;
+ const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_cfg->pll_id);
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+ uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
+ uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;
+ uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;
+ unsigned long dfout;
+ uint32_t postdiv1, postdiv2;
+
+ postdiv1 = mmio_read_32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK;
+ postdiv2 = mmio_read_32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK;
+
+ if ((mmio_read_32(pllxcfgr4) & RCC_PLLxCFGR4_BYPASS) != 0U) {
+ dfout = prate;
+ } else {
+ if ((postdiv1 == 0U) || (postdiv2 == 0U)) {
+ dfout = prate;
+ } else {
+ dfout = clk_get_pll_fvco(priv, pll, prate) / (postdiv1 * postdiv2);
+ }
+ }
+
+ return dfout;
+}
+
+static const struct stm32_clk_ops clk_stm32_pll_ops = {
+ .recalc_rate = clk_stm32_pll_recalc_rate,
+ .enable = clk_stm32_pll_enable,
+ .disable = clk_stm32_pll_disable,
+ .is_enabled = clk_stm32_pll_is_enabled,
+};
+
+#define CLK_PLL(idx, _idx, _parent, _pll_id, _flags)[idx] = {\
+ .binding = _idx,\
+ .parent = _parent,\
+ .flags = (_flags),\
+ .clock_cfg = &(struct stm32_pll_cfg) {\
+ .pll_id = _pll_id,\
+ },\
+ .ops = STM32_PLL_OPS,\
+}
+
+static unsigned long clk_get_pll1_fvco(unsigned long refclk)
+{
+ uintptr_t pll_freq1_reg = A35SSC_BASE + A35_SS_PLL_FREQ1;
+ uint32_t reg, fbdiv, refdiv;
+
+ reg = mmio_read_32(pll_freq1_reg);
+
+ fbdiv = (reg & A35_SS_PLL_FREQ1_FBDIV_MASK) >> A35_SS_PLL_FREQ1_FBDIV_SHIFT;
+ refdiv = (reg & A35_SS_PLL_FREQ1_REFDIV_MASK) >> A35_SS_PLL_FREQ1_REFDIV_SHIFT;
+
+ return (unsigned long)(refclk * fbdiv / refdiv);
+}
+
+static unsigned long clk_stm32_pll1_recalc_rate(struct stm32_clk_priv *priv,
+ int id, unsigned long prate)
+{
+ uintptr_t pll_freq2_reg = A35SSC_BASE + A35_SS_PLL_FREQ2;
+ uint32_t postdiv1, postdiv2;
+ unsigned long dfout;
+
+ postdiv1 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV1_MASK) >>
+ A35_SS_PLL_FREQ2_POSTDIV1_SHIFT;
+ postdiv2 = (mmio_read_32(pll_freq2_reg) & A35_SS_PLL_FREQ2_POSTDIV2_MASK) >>
+ A35_SS_PLL_FREQ2_POSTDIV2_SHIFT;
+
+ if ((postdiv1 == 0U) || (postdiv2 == 0U)) {
+ dfout = prate;
+ } else {
+ dfout = clk_get_pll1_fvco(prate) / (postdiv1 * postdiv2);
+ }
+
+ return dfout;
+}
+
+static const struct stm32_clk_ops clk_stm32_pll1_ops = {
+ .recalc_rate = clk_stm32_pll1_recalc_rate,
+};
+
+#define CLK_PLL1(idx, _idx, _parent, _pll_id, _flags)[idx] = {\
+ .binding = _idx,\
+ .parent = _parent,\
+ .flags = (_flags),\
+ .clock_cfg = &(struct stm32_pll_cfg) {\
+ .pll_id = _pll_id,\
+ },\
+ .ops = STM32_PLL1_OPS,\
+}
+
+struct stm32_clk_flexgen_cfg {
+ uint8_t id;
+};
+
+static unsigned long clk_flexgen_recalc(struct stm32_clk_priv *priv, int idx,
+ unsigned long prate)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, idx);
+ struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
+ uintptr_t rcc_base = priv->base;
+ uint32_t prediv, findiv;
+ uint8_t channel = cfg->id;
+ unsigned long freq = prate;
+
+ prediv = mmio_read_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel)) &
+ RCC_PREDIVxCFGR_PREDIVx_MASK;
+ findiv = mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) &
+ RCC_FINDIVxCFGR_FINDIVx_MASK;
+
+ if (freq == 0UL) {
+ return 0U;
+ }
+
+ switch (prediv) {
+ case 0x0:
+ case 0x1:
+ case 0x3:
+ case 0x3FF:
+ break;
+
+ default:
+ ERROR("Unsupported PREDIV value (%x)\n", prediv);
+ panic();
+ break;
+ }
+
+ freq /= (prediv + 1U);
+ freq /= (findiv + 1U);
+
+ return freq;
+}
+
+static int clk_flexgen_get_parent(struct stm32_clk_priv *priv, int idx)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, idx);
+ struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
+ uint32_t sel;
+ uint32_t address;
+ uintptr_t rcc_base = priv->base;
+
+ address = RCC_XBAR0CFGR + (cfg->id * 4);
+
+ sel = mmio_read_32(rcc_base + address) & RCC_XBARxCFGR_XBARxSEL_MASK;
+
+ return sel;
+}
+
+static int clk_flexgen_gate_enable(struct stm32_clk_priv *priv, int idx)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, idx);
+ struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
+ uintptr_t rcc_base = priv->base;
+ uint8_t channel = cfg->id;
+
+ mmio_setbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel),
+ RCC_FINDIVxCFGR_FINDIVxEN);
+
+ return 0;
+}
+
+static void clk_flexgen_gate_disable(struct stm32_clk_priv *priv, int id)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, id);
+ struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
+ uintptr_t rcc_base = priv->base;
+ uint8_t channel = cfg->id;
+
+ mmio_clrbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel),
+ RCC_FINDIVxCFGR_FINDIVxEN);
+}
+
+static bool clk_flexgen_gate_is_enabled(struct stm32_clk_priv *priv, int id)
+{
+ const struct clk_stm32 *clk = _clk_get(priv, id);
+ struct stm32_clk_flexgen_cfg *cfg = clk->clock_cfg;
+ uintptr_t rcc_base = priv->base;
+ uint8_t channel = cfg->id;
+
+ return !!(mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) &
+ RCC_FINDIVxCFGR_FINDIVxEN);
+}
+
+static const struct stm32_clk_ops clk_stm32_flexgen_ops = {
+ .recalc_rate = clk_flexgen_recalc,
+ .get_parent = clk_flexgen_get_parent,
+ .enable = clk_flexgen_gate_enable,
+ .disable = clk_flexgen_gate_disable,
+ .is_enabled = clk_flexgen_gate_is_enabled,
+};
+
+#define FLEXGEN(idx, _idx, _flags, _id)[idx] = {\
+ .binding = _idx,\
+ .parent = MUX(MUX_XBARSEL),\
+ .flags = (_flags),\
+ .clock_cfg = &(struct stm32_clk_flexgen_cfg) {\
+ .id = _id,\
+ },\
+ .ops = STM32_FLEXGEN_OPS,\
+}
+
+#define RCC_0_MHZ UL(0)
+#define RCC_4_MHZ UL(4000000)
+#define RCC_16_MHZ UL(16000000)
+
+#ifdef IMAGE_BL2
+static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
+ unsigned long prate)
+{
+ uintptr_t address = priv->base + RCC_BDCR;
+ uint32_t mask = RCC_BDCR_MSIFREQSEL;
+ int ret = -1;
+
+ switch (rate) {
+ case RCC_4_MHZ:
+ mmio_clrbits_32(address, mask);
+ ret = 0;
+ break;
+
+ case RCC_16_MHZ:
+ mmio_setbits_32(address, mask);
+ ret = 0;
+ break;
+
+ default:
+ break;
+ }
+
+ return ret;
+}
+#endif /* IMAGE_BL2 */
+
+static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv,
+ int id __unused,
+ unsigned long prate __unused)
+{
+ uintptr_t address = priv->base + RCC_BDCR;
+
+ if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) {
+ return RCC_4_MHZ;
+ } else {
+ return RCC_16_MHZ;
+ }
+}
+
+static const struct stm32_clk_ops clk_stm32_osc_msi_ops = {
+ .recalc_rate = clk_stm32_osc_msi_recalc_rate,
+ .is_enabled = clk_stm32_osc_gate_is_enabled,
+ .enable = clk_stm32_osc_gate_enable,
+ .disable = clk_stm32_osc_gate_disable,
+ .init = clk_stm32_osc_init,
+};
+
+#define CLK_OSC_MSI(idx, _idx, _parent, _osc_id) \
+ [(idx)] = (struct clk_stm32){ \
+ .binding = (_idx),\
+ .parent = (_parent),\
+ .flags = CLK_IS_CRITICAL,\
+ .clock_cfg = &(struct stm32_osc_cfg){\
+ .osc_id = (_osc_id),\
+ },\
+ .ops = STM32_OSC_MSI_OPS,\
+ }
+
+static const struct stm32_clk_ops clk_stm32_rtc_ops = {
+ .enable = clk_stm32_gate_enable,
+ .disable = clk_stm32_gate_disable,
+ .is_enabled = clk_stm32_gate_is_enabled,
+};
+
+#define CLK_RTC(idx, _binding, _parent, _flags, _gate_id)[idx] = {\
+ .binding = (_binding),\
+ .parent = (_parent),\
+ .flags = (_flags),\
+ .clock_cfg = &(struct clk_stm32_gate_cfg) {\
+ .id = (_gate_id),\
+ },\
+ .ops = STM32_RTC_OPS,\
+}
+
+enum {
+ STM32_PLL_OPS = STM32_LAST_OPS,
+ STM32_PLL1_OPS,
+ STM32_FLEXGEN_OPS,
+ STM32_OSC_MSI_OPS,
+ STM32_RTC_OPS,
+
+ MP25_LAST_OPS
+};
+
+static const struct stm32_clk_ops *ops_array_mp25[MP25_LAST_OPS] = {
+ [NO_OPS] = NULL,
+ [FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
+ [GATE_OPS] = &clk_gate_ops,
+ [STM32_MUX_OPS] = &clk_mux_ops,
+ [STM32_DIVIDER_OPS] = &clk_stm32_divider_ops,
+ [STM32_GATE_OPS] = &clk_stm32_gate_ops,
+ [STM32_TIMER_OPS] = &clk_timer_ops,
+ [STM32_FIXED_RATE_OPS] = &clk_stm32_fixed_rate_ops,
+ [STM32_OSC_OPS] = &clk_stm32_osc_ops,
+ [STM32_OSC_NOGATE_OPS] = &clk_stm32_osc_nogate_ops,
+
+ [STM32_PLL_OPS] = &clk_stm32_pll_ops,
+ [STM32_PLL1_OPS] = &clk_stm32_pll1_ops,
+ [STM32_FLEXGEN_OPS] = &clk_stm32_flexgen_ops,
+ [STM32_OSC_MSI_OPS] = &clk_stm32_osc_msi_ops,
+ [STM32_RTC_OPS] = &clk_stm32_rtc_ops
+};
+
+static const struct clk_stm32 stm32mp25_clk[CK_LAST] = {
+ CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ),
+
+ /* ROOT CLOCKS */
+ CLK_OSC(_CK_HSE, HSE_CK, CLK_IS_ROOT, OSC_HSE),
+ CLK_OSC(_CK_LSE, LSE_CK, CLK_IS_ROOT, OSC_LSE),
+ CLK_OSC(_CK_HSI, HSI_CK, CLK_IS_ROOT, OSC_HSI),
+ CLK_OSC(_CK_LSI, LSI_CK, CLK_IS_ROOT, OSC_LSI),
+ CLK_OSC_MSI(_CK_MSI, MSI_CK, CLK_IS_ROOT, OSC_MSI),
+
+ CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN),
+ CLK_OSC_FIXED(_SPDIFSYMB, _NO_ID, CLK_IS_ROOT, OSC_SPDIFSYMB),
+
+ STM32_DIV(_CK_HSE_RTC, _NO_ID, _CK_HSE, 0, DIV_RTC),
+
+ CLK_RTC(_CK_RTCCK, RTC_CK, MUX(MUX_RTC), 0, GATE_RTCCK),
+
+ CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0),
+
+ CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0),
+ CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0),
+ CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0),
+ CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0),
+ CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0),
+ CLK_PLL(_CK_PLL7, PLL7_CK, MUX(MUX_MUXSEL3), _PLL7, 0),
+ CLK_PLL(_CK_PLL8, PLL8_CK, MUX(MUX_MUXSEL4), _PLL8, 0),
+
+ FLEXGEN(_CK_ICN_HS_MCU, CK_ICN_HS_MCU, CLK_IS_CRITICAL, 0),
+ FLEXGEN(_CK_ICN_SDMMC, CK_ICN_SDMMC, CLK_IS_CRITICAL, 1),
+ FLEXGEN(_CK_ICN_DDR, CK_ICN_DDR, CLK_IS_CRITICAL, 2),
+ FLEXGEN(_CK_ICN_HSL, CK_ICN_HSL, CLK_IS_CRITICAL, 4),
+ FLEXGEN(_CK_ICN_NIC, CK_ICN_NIC, CLK_IS_CRITICAL, 5),
+
+ STM32_DIV(_CK_ICN_LS_MCU, CK_ICN_LS_MCU, _CK_ICN_HS_MCU, 0, DIV_LSMCU),
+
+ FLEXGEN(_CK_FLEXGEN_07, CK_FLEXGEN_07, 0, 7),
+ FLEXGEN(_CK_FLEXGEN_08, CK_FLEXGEN_08, 0, 8),
+ FLEXGEN(_CK_FLEXGEN_09, CK_FLEXGEN_09, 0, 9),
+ FLEXGEN(_CK_FLEXGEN_10, CK_FLEXGEN_10, 0, 10),
+ FLEXGEN(_CK_FLEXGEN_11, CK_FLEXGEN_11, 0, 11),
+ FLEXGEN(_CK_FLEXGEN_12, CK_FLEXGEN_12, 0, 12),
+ FLEXGEN(_CK_FLEXGEN_13, CK_FLEXGEN_13, 0, 13),
+ FLEXGEN(_CK_FLEXGEN_14, CK_FLEXGEN_14, 0, 14),
+ FLEXGEN(_CK_FLEXGEN_15, CK_FLEXGEN_15, 0, 15),
+ FLEXGEN(_CK_FLEXGEN_16, CK_FLEXGEN_16, 0, 16),
+ FLEXGEN(_CK_FLEXGEN_17, CK_FLEXGEN_17, 0, 17),
+ FLEXGEN(_CK_FLEXGEN_18, CK_FLEXGEN_18, 0, 18),
+ FLEXGEN(_CK_FLEXGEN_19, CK_FLEXGEN_19, 0, 19),
+ FLEXGEN(_CK_FLEXGEN_20, CK_FLEXGEN_20, 0, 20),
+ FLEXGEN(_CK_FLEXGEN_21, CK_FLEXGEN_21, 0, 21),
+ FLEXGEN(_CK_FLEXGEN_22, CK_FLEXGEN_22, 0, 22),
+ FLEXGEN(_CK_FLEXGEN_23, CK_FLEXGEN_23, 0, 23),
+ FLEXGEN(_CK_FLEXGEN_24, CK_FLEXGEN_24, 0, 24),
+ FLEXGEN(_CK_FLEXGEN_25, CK_FLEXGEN_25, 0, 25),
+ FLEXGEN(_CK_FLEXGEN_26, CK_FLEXGEN_26, 0, 26),
+ FLEXGEN(_CK_FLEXGEN_27, CK_FLEXGEN_27, 0, 27),
+ FLEXGEN(_CK_FLEXGEN_28, CK_FLEXGEN_28, 0, 28),
+ FLEXGEN(_CK_FLEXGEN_29, CK_FLEXGEN_29, 0, 29),
+ FLEXGEN(_CK_FLEXGEN_30, CK_FLEXGEN_30, 0, 30),
+ FLEXGEN(_CK_FLEXGEN_31, CK_FLEXGEN_31, 0, 31),
+ FLEXGEN(_CK_FLEXGEN_32, CK_FLEXGEN_32, 0, 32),
+ FLEXGEN(_CK_FLEXGEN_33, CK_FLEXGEN_33, 0, 33),
+ FLEXGEN(_CK_FLEXGEN_34, CK_FLEXGEN_34, 0, 34),
+ FLEXGEN(_CK_FLEXGEN_35, CK_FLEXGEN_35, 0, 35),
+ FLEXGEN(_CK_FLEXGEN_36, CK_FLEXGEN_36, 0, 36),
+ FLEXGEN(_CK_FLEXGEN_37, CK_FLEXGEN_37, 0, 37),
+ FLEXGEN(_CK_FLEXGEN_38, CK_FLEXGEN_38, 0, 38),
+ FLEXGEN(_CK_FLEXGEN_39, CK_FLEXGEN_39, 0, 39),
+ FLEXGEN(_CK_FLEXGEN_40, CK_FLEXGEN_40, 0, 40),
+ FLEXGEN(_CK_FLEXGEN_41, CK_FLEXGEN_41, 0, 41),
+ FLEXGEN(_CK_FLEXGEN_42, CK_FLEXGEN_42, 0, 42),
+ FLEXGEN(_CK_FLEXGEN_43, CK_FLEXGEN_43, 0, 43),
+ FLEXGEN(_CK_FLEXGEN_44, CK_FLEXGEN_44, 0, 44),
+ FLEXGEN(_CK_FLEXGEN_45, CK_FLEXGEN_45, 0, 45),
+ FLEXGEN(_CK_FLEXGEN_46, CK_FLEXGEN_46, 0, 46),
+ FLEXGEN(_CK_FLEXGEN_47, CK_FLEXGEN_47, 0, 47),
+ FLEXGEN(_CK_FLEXGEN_48, CK_FLEXGEN_48, 0, 48),
+ FLEXGEN(_CK_FLEXGEN_49, CK_FLEXGEN_49, 0, 49),
+ FLEXGEN(_CK_FLEXGEN_50, CK_FLEXGEN_50, 0, 50),
+ FLEXGEN(_CK_FLEXGEN_51, CK_FLEXGEN_51, 0, 51),
+ FLEXGEN(_CK_FLEXGEN_52, CK_FLEXGEN_52, 0, 52),
+ FLEXGEN(_CK_FLEXGEN_53, CK_FLEXGEN_53, 0, 53),
+ FLEXGEN(_CK_FLEXGEN_54, CK_FLEXGEN_54, 0, 54),
+ FLEXGEN(_CK_FLEXGEN_55, CK_FLEXGEN_55, 0, 55),
+ FLEXGEN(_CK_FLEXGEN_56, CK_FLEXGEN_56, 0, 56),
+ FLEXGEN(_CK_FLEXGEN_57, CK_FLEXGEN_57, 0, 57),
+ FLEXGEN(_CK_FLEXGEN_58, CK_FLEXGEN_58, 0, 58),
+ FLEXGEN(_CK_FLEXGEN_59, CK_FLEXGEN_59, 0, 59),
+ FLEXGEN(_CK_FLEXGEN_60, CK_FLEXGEN_60, 0, 60),
+ FLEXGEN(_CK_FLEXGEN_61, CK_FLEXGEN_61, 0, 61),
+ FLEXGEN(_CK_FLEXGEN_62, CK_FLEXGEN_62, 0, 62),
+ FLEXGEN(_CK_FLEXGEN_63, CK_FLEXGEN_63, 0, 63),
+
+ STM32_DIV(_CK_ICN_APB1, CK_ICN_APB1, _CK_ICN_LS_MCU, 0, DIV_APB1),
+ STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2),
+ STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3),
+ STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4),
+ STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG),
+
+ /* KERNEL CLOCK */
+ STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM),
+ STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM),
+ STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1),
+ STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2),
+
+ STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC),
+ STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1),
+ STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC),
+ STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM),
+ STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM),
+ STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH),
+ STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG),
+ STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1),
+ STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2),
+ STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES),
+ STM32_GATE(_CK_PKA, CK_BUS_PKA, _CK_ICN_LS_MCU, 0, GATE_PKA),
+
+ STM32_GATE(_CK_GPIOA, CK_BUS_GPIOA, _CK_ICN_LS_MCU, 0, GATE_GPIOA),
+ STM32_GATE(_CK_GPIOB, CK_BUS_GPIOB, _CK_ICN_LS_MCU, 0, GATE_GPIOB),
+ STM32_GATE(_CK_GPIOC, CK_BUS_GPIOC, _CK_ICN_LS_MCU, 0, GATE_GPIOC),
+ STM32_GATE(_CK_GPIOD, CK_BUS_GPIOD, _CK_ICN_LS_MCU, 0, GATE_GPIOD),
+ STM32_GATE(_CK_GPIOE, CK_BUS_GPIOE, _CK_ICN_LS_MCU, 0, GATE_GPIOE),
+ STM32_GATE(_CK_GPIOF, CK_BUS_GPIOF, _CK_ICN_LS_MCU, 0, GATE_GPIOF),
+ STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG),
+ STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH),
+ STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI),
+ STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ),
+ STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK),
+ STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ),
+ STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, 0, GATE_RTC),
+
+ STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, 0, GATE_DDRCP),
+
+ /* WARNING 2 CLOCKS FOR ONE GATE */
+ STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI),
+ STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI),
+
+ STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR),
+
+ STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC),
+ STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1),
+ STM32_GATE(_CK_IWDG2, CK_BUS_IWDG2, _CK_ICN_APB3, 0, GATE_IWDG2),
+
+ STM32_GATE(_CK_DDRCAPB, CK_BUS_DDRC, _CK_ICN_APB4, 0, GATE_DDRCAPB),
+ STM32_GATE(_CK_DDR, CK_BUS_DDRCFG, _CK_ICN_APB4, 0, GATE_DDR),
+
+ STM32_GATE(_CK_USART2, CK_KER_USART2, _CK_FLEXGEN_08, 0, GATE_USART2),
+ STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4),
+ STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3),
+ STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5),
+ STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1),
+ STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2),
+ STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3),
+ STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5),
+ STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4),
+ STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6),
+ STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7),
+ STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1),
+ STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6),
+ STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7),
+ STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8),
+ STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9),
+ STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN),
+ STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY),
+ STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC),
+ STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8),
+ STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1),
+ STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2),
+ STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC),
+ STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1),
+ STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2),
+ STM32_GATE(_CK_USB2PHY1, CK_KER_USB2PHY1, _CK_FLEXGEN_57, 0, GATE_USB2PHY1),
+ STM32_GATE(_CK_USB2PHY2, CK_KER_USB2PHY2, _CK_FLEXGEN_58, 0, GATE_USB2PHY2),
+};
+
+enum clksrc_id {
+ CLKSRC_CA35SS,
+ CLKSRC_PLL1,
+ CLKSRC_PLL2,
+ CLKSRC_PLL3,
+ CLKSRC_PLL4,
+ CLKSRC_PLL5,
+ CLKSRC_PLL6,
+ CLKSRC_PLL7,
+ CLKSRC_PLL8,
+ CLKSRC_XBAR_CHANNEL0,
+ CLKSRC_XBAR_CHANNEL1,
+ CLKSRC_XBAR_CHANNEL2,
+ CLKSRC_XBAR_CHANNEL3,
+ CLKSRC_XBAR_CHANNEL4,
+ CLKSRC_XBAR_CHANNEL5,
+ CLKSRC_XBAR_CHANNEL6,
+ CLKSRC_XBAR_CHANNEL7,
+ CLKSRC_XBAR_CHANNEL8,
+ CLKSRC_XBAR_CHANNEL9,
+ CLKSRC_XBAR_CHANNEL10,
+ CLKSRC_XBAR_CHANNEL11,
+ CLKSRC_XBAR_CHANNEL12,
+ CLKSRC_XBAR_CHANNEL13,
+ CLKSRC_XBAR_CHANNEL14,
+ CLKSRC_XBAR_CHANNEL15,
+ CLKSRC_XBAR_CHANNEL16,
+ CLKSRC_XBAR_CHANNEL17,
+ CLKSRC_XBAR_CHANNEL18,
+ CLKSRC_XBAR_CHANNEL19,
+ CLKSRC_XBAR_CHANNEL20,
+ CLKSRC_XBAR_CHANNEL21,
+ CLKSRC_XBAR_CHANNEL22,
+ CLKSRC_XBAR_CHANNEL23,
+ CLKSRC_XBAR_CHANNEL24,
+ CLKSRC_XBAR_CHANNEL25,
+ CLKSRC_XBAR_CHANNEL26,
+ CLKSRC_XBAR_CHANNEL27,
+ CLKSRC_XBAR_CHANNEL28,
+ CLKSRC_XBAR_CHANNEL29,
+ CLKSRC_XBAR_CHANNEL30,
+ CLKSRC_XBAR_CHANNEL31,
+ CLKSRC_XBAR_CHANNEL32,
+ CLKSRC_XBAR_CHANNEL33,
+ CLKSRC_XBAR_CHANNEL34,
+ CLKSRC_XBAR_CHANNEL35,
+ CLKSRC_XBAR_CHANNEL36,
+ CLKSRC_XBAR_CHANNEL37,
+ CLKSRC_XBAR_CHANNEL38,
+ CLKSRC_XBAR_CHANNEL39,
+ CLKSRC_XBAR_CHANNEL40,
+ CLKSRC_XBAR_CHANNEL41,
+ CLKSRC_XBAR_CHANNEL42,
+ CLKSRC_XBAR_CHANNEL43,
+ CLKSRC_XBAR_CHANNEL44,
+ CLKSRC_XBAR_CHANNEL45,
+ CLKSRC_XBAR_CHANNEL46,
+ CLKSRC_XBAR_CHANNEL47,
+ CLKSRC_XBAR_CHANNEL48,
+ CLKSRC_XBAR_CHANNEL49,
+ CLKSRC_XBAR_CHANNEL50,
+ CLKSRC_XBAR_CHANNEL51,
+ CLKSRC_XBAR_CHANNEL52,
+ CLKSRC_XBAR_CHANNEL53,
+ CLKSRC_XBAR_CHANNEL54,
+ CLKSRC_XBAR_CHANNEL55,
+ CLKSRC_XBAR_CHANNEL56,
+ CLKSRC_XBAR_CHANNEL57,
+ CLKSRC_XBAR_CHANNEL58,
+ CLKSRC_XBAR_CHANNEL59,
+ CLKSRC_XBAR_CHANNEL60,
+ CLKSRC_XBAR_CHANNEL61,
+ CLKSRC_XBAR_CHANNEL62,
+ CLKSRC_XBAR_CHANNEL63,
+ CLKSRC_RTC,
+ CLKSRC_MCO1,
+ CLKSRC_MCO2,
+ CLKSRC_NB
+};
+
+static void stm32mp2_a35_ss_on_hsi(void)
+{
+ uintptr_t a35_ss_address = A35SSC_BASE;
+ uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ;
+ uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE;
+ uint64_t timeout;
+
+ if ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) ==
+ A35_SS_CHGCLKREQ_ARM_CHGCLKACK) {
+ /* Nothing to do, clock source is already set on bypass clock */
+ return;
+ }
+
+ mmio_setbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ);
+
+ timeout = timeout_init_us(CLKSRC_TIMEOUT);
+ while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) !=
+ A35_SS_CHGCLKREQ_ARM_CHGCLKACK) {
+ if (timeout_elapsed(timeout)) {
+ EARLY_ERROR("Cannot switch A35 to bypass clock\n");
+ panic();
+ }
+ }
+
+ mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF);
+}
+
+#ifdef IMAGE_BL2
+static void stm32mp2_clk_muxsel_on_hsi(struct stm32_clk_priv *priv)
+{
+ mmio_clrbits_32(priv->base + RCC_MUXSELCFGR,
+ RCC_MUXSELCFGR_MUXSEL0_MASK |
+ RCC_MUXSELCFGR_MUXSEL1_MASK |
+ RCC_MUXSELCFGR_MUXSEL2_MASK |
+ RCC_MUXSELCFGR_MUXSEL3_MASK |
+ RCC_MUXSELCFGR_MUXSEL4_MASK |
+ RCC_MUXSELCFGR_MUXSEL5_MASK |
+ RCC_MUXSELCFGR_MUXSEL6_MASK |
+ RCC_MUXSELCFGR_MUXSEL7_MASK);
+}
+
+static void stm32mp2_clk_xbar_on_hsi(struct stm32_clk_priv *priv)
+{
+ uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR;
+ uint32_t i;
+
+ for (i = 0; i < XBAR_CHANNEL_NB; i++) {
+ mmio_clrsetbits_32(xbar0cfgr + (0x4 * i),
+ RCC_XBAR0CFGR_XBAR0SEL_MASK,
+ XBAR_SRC_HSI);
+ }
+}
+
+static int stm32mp2_a35_pll1_start(void)
+{
+ uintptr_t a35_ss_address = A35SSC_BASE;
+ uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE;
+ uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ;
+ uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT);
+
+ mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD);
+
+ /* Wait PLL lock */
+ while ((mmio_read_32(pll_enable_reg) & A35_SS_PLL_ENABLE_LOCKP) == 0U) {
+ if (timeout_elapsed(timeout)) {
+ EARLY_ERROR("PLL1 start failed @ 0x%lx: 0x%x\n",
+ pll_enable_reg, mmio_read_32(pll_enable_reg));
+ return -ETIMEDOUT;
+ }
+ }
+
+ /* De-assert reset on PLL output clock path */
+ mmio_setbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_NRESET_SWPLL_FF);
+
+ /* Switch CPU clock to PLL clock */
+ mmio_clrbits_32(chgclkreq_reg, A35_SS_CHGCLKREQ_ARM_CHGCLKREQ);
+
+ /* Wait for clock change acknowledge */
+ timeout = timeout_init_us(CLKSRC_TIMEOUT);
+ while ((mmio_read_32(chgclkreq_reg) & A35_SS_CHGCLKREQ_ARM_CHGCLKACK) != 0U) {
+ if (timeout_elapsed(timeout)) {
+ EARLY_ERROR("CA35SS switch to PLL1 failed @ 0x%lx: 0x%x\n",
+ chgclkreq_reg, mmio_read_32(chgclkreq_reg));
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, uint32_t postdiv1,
+ uint32_t postdiv2)
+{
+ uintptr_t a35_ss_address = A35SSC_BASE;
+ uintptr_t pll_freq1_reg = a35_ss_address + A35_SS_PLL_FREQ1;
+ uintptr_t pll_freq2_reg = a35_ss_address + A35_SS_PLL_FREQ2;
+
+ mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_REFDIV_MASK,
+ (refdiv << A35_SS_PLL_FREQ1_REFDIV_SHIFT) &
+ A35_SS_PLL_FREQ1_REFDIV_MASK);
+
+ mmio_clrsetbits_32(pll_freq1_reg, A35_SS_PLL_FREQ1_FBDIV_MASK,
+ (fbdiv << A35_SS_PLL_FREQ1_FBDIV_SHIFT) &
+ A35_SS_PLL_FREQ1_FBDIV_MASK);
+
+ mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV1_MASK,
+ (postdiv1 << A35_SS_PLL_FREQ2_POSTDIV1_SHIFT) &
+ A35_SS_PLL_FREQ2_POSTDIV1_MASK);
+
+ mmio_clrsetbits_32(pll_freq2_reg, A35_SS_PLL_FREQ2_POSTDIV2_MASK,
+ (postdiv2 << A35_SS_PLL_FREQ2_POSTDIV2_SHIFT) &
+ A35_SS_PLL_FREQ2_POSTDIV2_MASK);
+}
+
+static int clk_stm32_pll_config_output(struct stm32_clk_priv *priv,
+ const struct stm32_clk_pll *pll,
+ uint32_t *pllcfg,
+ uint32_t fracv)
+{
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+ uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;
+ uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
+ uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
+ uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;
+ uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;
+ unsigned long refclk;
+
+ refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id);
+
+ if (fracv == 0U) {
+ /* PLL in integer mode */
+
+ /*
+ * No need to check max clock, as oscillator reference clocks
+ * will always be less than 1.2GHz
+ */
+ if (refclk < PLL_REFCLK_MIN) {
+ panic();
+ }
+
+ mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK);
+ mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
+ mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN);
+ mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
+ mmio_setbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);
+ } else {
+ /* PLL in frac mode */
+
+ /*
+ * No need to check max clock, as oscillator reference clocks
+ * will always be less than 1.2GHz
+ */
+ if (refclk < PLL_FRAC_REFCLK_MIN) {
+ panic();
+ }
+
+ mmio_clrsetbits_32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK,
+ fracv & RCC_PLLxCFGR3_FRACIN_MASK);
+ mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
+ mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
+ }
+
+ assert(pllcfg[REFDIV] != 0U);
+
+ mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK,
+ (pllcfg[FBDIV] << RCC_PLLxCFGR2_FBDIV_SHIFT) &
+ RCC_PLLxCFGR2_FBDIV_MASK);
+ mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK,
+ pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK);
+ mmio_clrsetbits_32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK,
+ pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK);
+ mmio_clrsetbits_32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK,
+ pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK);
+
+ if ((pllcfg[POSTDIV1] == 0U) || (pllcfg[POSTDIV2] == 0U)) {
+ /* Bypass mode */
+ mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS);
+ mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN);
+ } else {
+ mmio_clrbits_32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS);
+ mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN);
+ }
+
+ return 0;
+}
+
+static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv,
+ const struct stm32_clk_pll *pll,
+ uint32_t *csg)
+{
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+ uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
+ uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
+ uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5;
+
+
+ mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK,
+ csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK);
+ mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK,
+ (csg[SPREAD] << RCC_PLLxCFGR5_SPREAD_SHIFT) &
+ RCC_PLLxCFGR5_SPREAD_MASK);
+
+ if (csg[DOWNSPREAD] != 0) {
+ mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD);
+ } else {
+ mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD);
+ }
+
+ mmio_clrbits_32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
+
+ mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);
+ udelay(1);
+
+ mmio_setbits_32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
+ mmio_setbits_32(pllxcfgr3, RCC_PLLxCFGR3_DACEN);
+}
+
+static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data);
+
+static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx)
+{
+ struct stm32_clk_priv *priv = clk_stm32_get_priv();
+ struct stm32_clk_platdata *pdata = priv->pdata;
+
+ return &pdata->pll[pll_idx];
+}
+
+static int _clk_stm32_pll1_init(struct stm32_clk_priv *priv, int pll_idx,
+ struct stm32_pll_dt_cfg *pll_conf)
+{
+ const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);
+ unsigned long refclk;
+ int ret = 0;
+
+ stm32mp2_a35_ss_on_hsi();
+
+ ret = stm32_clk_configure_mux(priv, pll_conf->src);
+ if (ret != 0) {
+ panic();
+ }
+
+ refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id);
+
+ /*
+ * No need to check max clock, as oscillator reference clocks will
+ * always be less than 1.2 GHz
+ */
+ if (refclk < PLL_REFCLK_MIN) {
+ EARLY_ERROR("%s: %d\n", __func__, __LINE__);
+ panic();
+ }
+
+ stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV], pll_conf->cfg[REFDIV],
+ pll_conf->cfg[POSTDIV1], pll_conf->cfg[POSTDIV2]);
+
+ ret = stm32mp2_a35_pll1_start();
+ if (ret != 0) {
+ panic();
+ }
+
+ return 0;
+}
+
+static int clk_stm32_pll_wait_mux_ready(struct stm32_clk_priv *priv,
+ const struct stm32_clk_pll *pll)
+{
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+ uint64_t timeout = timeout_init_us(CLKSRC_TIMEOUT);
+
+ while ((mmio_read_32(pllxcfgr1) & RCC_PLLxCFGR1_CKREFST) !=
+ RCC_PLLxCFGR1_CKREFST) {
+ if (timeout_elapsed(timeout)) {
+ EARLY_ERROR("PLL%d ref clock not started\n", pll->clk_id - _CK_PLL1 + 1);
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx,
+ struct stm32_pll_dt_cfg *pll_conf)
+{
+ const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);
+ uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
+ bool spread_spectrum = false;
+ int ret = 0;
+
+ _clk_stm32_pll_disable(priv, pll);
+
+ ret = stm32_clk_configure_mux(priv, pll_conf->src);
+ if (ret != 0) {
+ panic();
+ }
+
+ ret = clk_stm32_pll_wait_mux_ready(priv, pll);
+ if (ret != 0) {
+ panic();
+ }
+
+ ret = clk_stm32_pll_config_output(priv, pll, pll_conf->cfg, pll_conf->frac);
+ if (ret != 0) {
+ panic();
+ }
+
+ if (pll_conf->csg_enabled) {
+ clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);
+ spread_spectrum = true;
+ }
+
+ _clk_stm32_pll_enable(priv, pll);
+
+ if (spread_spectrum) {
+ mmio_clrbits_32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);
+ }
+
+ return 0;
+}
+
+static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx)
+{
+ struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx);
+
+ if (pll_conf->enabled) {
+ if (pll_idx == _PLL1) {
+ return _clk_stm32_pll1_init(priv, pll_idx, pll_conf);
+ } else {
+ return _clk_stm32_pll_init(priv, pll_idx, pll_conf);
+ }
+ }
+
+ return 0;
+}
+
+static int stm32mp2_clk_pll_configure(struct stm32_clk_priv *priv)
+{
+ enum pll_id i;
+ int err;
+
+ for (i = _PLL1; i < _PLL_NB; i++) {
+ err = clk_stm32_pll_init(priv, i);
+ if (err) {
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+static int wait_predivsr(uint16_t channel)
+{
+ struct stm32_clk_priv *priv = clk_stm32_get_priv();
+ uintptr_t rcc_base = priv->base;
+ uintptr_t previvsr;
+ uint32_t channel_bit;
+ uint64_t timeout;
+
+ if (channel < __WORD_BIT) {
+ previvsr = rcc_base + RCC_PREDIVSR1;
+ channel_bit = BIT(channel);
+ } else {
+ previvsr = rcc_base + RCC_PREDIVSR2;
+ channel_bit = BIT(channel - __WORD_BIT);
+ }
+
+ timeout = timeout_init_us(CLKDIV_TIMEOUT);
+ while ((mmio_read_32(previvsr) & channel_bit) != 0U) {
+ if (timeout_elapsed(timeout)) {
+ EARLY_ERROR("Pre divider status: %x\n",
+ mmio_read_32(previvsr));
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static int wait_findivsr(uint16_t channel)
+{
+ struct stm32_clk_priv *priv = clk_stm32_get_priv();
+ uintptr_t rcc_base = priv->base;
+ uintptr_t finvivsr;
+ uint32_t channel_bit;
+ uint64_t timeout;
+
+ if (channel < __WORD_BIT) {
+ finvivsr = rcc_base + RCC_FINDIVSR1;
+ channel_bit = BIT(channel);
+ } else {
+ finvivsr = rcc_base + RCC_FINDIVSR2;
+ channel_bit = BIT(channel - __WORD_BIT);
+ }
+
+ timeout = timeout_init_us(CLKDIV_TIMEOUT);
+ while ((mmio_read_32(finvivsr) & channel_bit) != 0U) {
+ if (timeout_elapsed(timeout)) {
+ EARLY_ERROR("Final divider status: %x\n",
+ mmio_read_32(finvivsr));
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static int wait_xbar_sts(uint16_t channel)
+{
+ struct stm32_clk_priv *priv = clk_stm32_get_priv();
+ uintptr_t rcc_base = priv->base;
+ uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4U * channel);
+ uint64_t timeout;
+
+ timeout = timeout_init_us(CLKDIV_TIMEOUT);
+ while ((mmio_read_32(xbar_cfgr) & RCC_XBAR0CFGR_XBAR0STS) != 0U) {
+ if (timeout_elapsed(timeout)) {
+ EARLY_ERROR("XBAR%uCFGR: %x\n", channel,
+ mmio_read_32(xbar_cfgr));
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src,
+ unsigned int prediv, unsigned int findiv)
+{
+ struct stm32_clk_priv *priv = clk_stm32_get_priv();
+ uintptr_t rcc_base = priv->base;
+
+ if (wait_predivsr(channel) != 0) {
+ panic();
+ }
+
+ mmio_clrsetbits_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel),
+ RCC_PREDIV0CFGR_PREDIV0_MASK,
+ prediv);
+
+ if (wait_predivsr(channel) != 0) {
+ panic();
+ }
+
+ if (wait_findivsr(channel) != 0) {
+ panic();
+ }
+
+ mmio_clrsetbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel),
+ RCC_FINDIV0CFGR_FINDIV0_MASK,
+ findiv);
+
+ if (wait_findivsr(channel) != 0) {
+ panic();
+ }
+
+ if (wait_xbar_sts(channel) != 0) {
+ panic();
+ }
+
+ mmio_clrsetbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel),
+ RCC_XBARxCFGR_XBARxSEL_MASK,
+ clk_src);
+ mmio_setbits_32(rcc_base + RCC_XBAR0CFGR + (0x4U * channel),
+ RCC_XBARxCFGR_XBARxEN);
+
+ if (wait_xbar_sts(channel) != 0) {
+ panic();
+ }
+}
+
+static int stm32mp2_clk_flexgen_configure(struct stm32_clk_priv *priv)
+{
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ uint32_t i;
+
+ for (i = 0U; i < pdata->nflexgen; i++) {
+ uint32_t val = pdata->flexgen[i];
+ uint32_t cmd, cmd_data;
+ unsigned int channel, clk_src, pdiv, fdiv;
+
+ cmd = (val & CMD_MASK) >> CMD_SHIFT;
+ cmd_data = val & ~CMD_MASK;
+
+ if (cmd != CMD_FLEXGEN) {
+ continue;
+ }
+
+ channel = (cmd_data & FLEX_ID_MASK) >> FLEX_ID_SHIFT;
+ clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT;
+ pdiv = (cmd_data & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT;
+ fdiv = (cmd_data & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT;
+
+ switch (channel) {
+ case 33U: /* STGEN */
+ break;
+
+ default:
+ flexclkgen_config_channel(channel, clk_src, pdiv, fdiv);
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv)
+{
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE];
+ bool digbyp = osci->digbyp;
+ bool bypass = osci->bypass;
+ bool css = osci->css;
+
+ if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) {
+ return;
+ }
+
+ clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass);
+
+ _clk_stm32_enable(priv, _CK_HSE);
+
+ clk_oscillator_set_css(priv, _CK_HSE, css);
+}
+
+static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv)
+{
+ struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE);
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
+ bool digbyp = osci->digbyp;
+ bool bypass = osci->bypass;
+ uint8_t drive = osci->drive;
+
+ if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) {
+ return;
+ }
+
+ /* Do not reconfigure LSE if already enabled */
+ if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) {
+ return;
+ }
+
+ clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass);
+
+ clk_oscillator_set_drive(priv, _CK_LSE, drive);
+
+ _clk_stm32_gate_enable(priv, osc_data->gate_id);
+}
+
+static int stm32mp2_clk_switch_to_hsi(struct stm32_clk_priv *priv)
+{
+ stm32mp2_a35_ss_on_hsi();
+ stm32mp2_clk_muxsel_on_hsi(priv);
+ stm32mp2_clk_xbar_on_hsi(priv);
+
+ return 0;
+}
+
+static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv)
+{
+ int ret = 0;
+
+ if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) {
+ ret = clk_oscillator_wait_ready_on(priv, _CK_LSE);
+ }
+
+ return ret;
+}
+
+static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv)
+{
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI];
+ int err;
+
+ err = clk_stm32_osc_msi_set_rate(priv, _CK_MSI, osci->freq, 0);
+ if (err != 0) {
+ EARLY_ERROR("Invalid rate %lu MHz for MSI ! (4 or 16 only)\n",
+ osci->freq / 1000000U);
+ panic();
+ }
+
+ _clk_stm32_enable(priv, _CK_MSI);
+}
+
+static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv)
+{
+ stm32_enable_oscillator_hse(priv);
+ stm32_enable_oscillator_lse(priv);
+ stm32_enable_oscillator_msi(priv);
+ _clk_stm32_enable(priv, _CK_LSI);
+}
+
+static int stm32_clk_configure_div(struct stm32_clk_priv *priv, uint32_t data)
+{
+ int div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT;
+ int div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT;
+
+ return clk_stm32_set_div(priv, div_id, div_n);
+}
+
+static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data)
+{
+ int mux_id = (data & MUX_ID_MASK) >> MUX_ID_SHIFT;
+ int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
+
+ return clk_mux_set_parent(priv, mux_id, sel);
+}
+
+static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data)
+{
+ unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT;
+
+ return clk_get_index(priv, binding_id);
+}
+
+static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)
+{
+ int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT;
+ bool enable = ((data & CLK_ON_MASK) >> CLK_ON_SHIFT) != 0U;
+ int clk_id = 0;
+ int ret = 0;
+
+ clk_id = stm32_clk_configure_clk_get_binding_id(priv, data);
+ if (clk_id < 0) {
+ return clk_id;
+ }
+
+ if (sel != CLK_NOMUX) {
+ ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+
+ if (enable) {
+ clk_stm32_enable_call_ops(priv, clk_id);
+ } else {
+ clk_stm32_disable_call_ops(priv, clk_id);
+ }
+
+ return 0;
+}
+
+static int stm32_clk_configure(struct stm32_clk_priv *priv, uint32_t val)
+{
+ uint32_t cmd = (val & CMD_MASK) >> CMD_SHIFT;
+ uint32_t cmd_data = val & ~CMD_MASK;
+ int ret = -1;
+
+ switch (cmd) {
+ case CMD_DIV:
+ ret = stm32_clk_configure_div(priv, cmd_data);
+ break;
+
+ case CMD_MUX:
+ ret = stm32_clk_configure_mux(priv, cmd_data);
+ break;
+
+ case CMD_CLK:
+ ret = stm32_clk_configure_clk(priv, cmd_data);
+ break;
+
+ default:
+ EARLY_ERROR("%s: cmd unknown ! : 0x%x\n", __func__, val);
+ break;
+ }
+
+ return ret;
+}
+
+static int stm32_clk_bus_configure(struct stm32_clk_priv *priv)
+{
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ uint32_t i;
+
+ for (i = 0; i < pdata->nbusclk; i++) {
+ int ret;
+
+ ret = stm32_clk_configure(priv, pdata->busclk[i]);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int stm32_clk_kernel_configure(struct stm32_clk_priv *priv)
+{
+ struct stm32_clk_platdata *pdata = priv->pdata;
+ uint32_t i;
+
+ for (i = 0U; i < pdata->nkernelclk; i++) {
+ int ret;
+
+ ret = stm32_clk_configure(priv, pdata->kernelclk[i]);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int stm32mp2_init_clock_tree(void)
+{
+ struct stm32_clk_priv *priv = clk_stm32_get_priv();
+ int ret;
+
+ /* Set timer with STGEN without changing its clock source */
+ stm32mp_stgen_restore_rate();
+ generic_delay_timer_init();
+
+ stm32_clk_oscillators_enable(priv);
+
+ /* Come back to HSI */
+ ret = stm32mp2_clk_switch_to_hsi(priv);
+ if (ret != 0) {
+ panic();
+ }
+
+ ret = stm32mp2_clk_pll_configure(priv);
+ if (ret != 0) {
+ panic();
+ }
+
+ /* Wait LSE ready before to use it */
+ ret = stm32_clk_oscillators_wait_lse_ready(priv);
+ if (ret != 0) {
+ panic();
+ }
+
+ ret = stm32mp2_clk_flexgen_configure(priv);
+ if (ret != 0) {
+ panic();
+ }
+
+ ret = stm32_clk_bus_configure(priv);
+ if (ret != 0) {
+ panic();
+ }
+
+ ret = stm32_clk_kernel_configure(priv);
+ if (ret != 0) {
+ panic();
+ }
+
+ return 0;
+}
+
+static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name,
+ struct stm32_osci_dt_cfg *osci)
+{
+ int subnode = 0;
+
+ /* Default value oscillator not found, freq=0 */
+ osci->freq = 0;
+
+ fdt_for_each_subnode(subnode, fdt, node) {
+ const char *cchar = NULL;
+ const fdt32_t *cuint = NULL;
+ int ret = 0;
+
+ cchar = fdt_get_name(fdt, subnode, &ret);
+ if (cchar == NULL) {
+ return ret;
+ }
+
+ if (strncmp(cchar, name, (size_t)ret) ||
+ fdt_get_status(subnode) == DT_DISABLED) {
+ continue;
+ }
+
+ cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);
+ if (cuint == NULL) {
+ return ret;
+ }
+
+ osci->freq = fdt32_to_cpu(*cuint);
+
+ if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) {
+ osci->bypass = true;
+ }
+
+ if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) {
+ osci->digbyp = true;
+ }
+
+ if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) {
+ osci->css = true;
+ }
+
+ osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH);
+
+ return 0;
+ }
+
+ return 0;
+}
+
+static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata)
+{
+ int fdt_err = 0;
+ uint32_t i = 0;
+ int node = 0;
+
+ node = fdt_path_offset(fdt, "/clocks");
+ if (node < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ for (i = 0; i < pdata->nosci; i++) {
+ const char *name = NULL;
+
+ name = clk_stm32_get_oscillator_name((enum stm32_osc)i);
+ if (name == NULL) {
+ continue;
+ }
+
+ fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]);
+ if (fdt_err < 0) {
+ panic();
+ }
+ }
+
+ return 0;
+}
+
+static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)
+{
+ const fdt32_t *cuint = NULL;
+ int subnode_pll = 0;
+ uint32_t val = 0;
+ int err = 0;
+
+ cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
+ if (!cuint) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
+ if (subnode_pll < 0) {
+ return -FDT_ERR_NOTFOUND;
+ }
+
+ err = fdt_read_uint32_array(fdt, subnode_pll, "cfg", (int)PLLCFG_NB, pll->cfg);
+ if (err != 0) {
+ return err;
+ }
+
+ err = fdt_read_uint32_array(fdt, subnode_pll, "csg", (int)PLLCSG_NB, pll->csg);
+
+ pll->csg_enabled = (err == 0);
+
+ if (err == -FDT_ERR_NOTFOUND) {
+ err = 0;
+ }
+
+ if (err != 0) {
+ return err;
+ }
+
+ pll->enabled = true;
+
+ pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0);
+
+ pll->src = UINT32_MAX;
+
+ err = fdt_read_uint32(fdt, subnode_pll, "src", &val);
+ if (err == 0) {
+ pll->src = val;
+ }
+
+ return 0;
+}
+
+#define RCC_PLL_NAME_SIZE 12
+
+static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata)
+{
+ unsigned int i = 0;
+
+ for (i = _PLL1; i < pdata->npll; i++) {
+ struct stm32_pll_dt_cfg *pll = pdata->pll + i;
+ char name[RCC_PLL_NAME_SIZE];
+ int subnode = 0;
+ int err = 0;
+
+ snprintf(name, sizeof(name), "st,pll-%u", i + 1);
+
+ subnode = fdt_subnode_offset(fdt, node, name);
+ if (!fdt_check_node(subnode)) {
+ continue;
+ }
+
+ err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);
+ if (err != 0) {
+ panic();
+ }
+ }
+
+ return 0;
+}
+
+static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata)
+{
+ void *fdt = NULL;
+ int node;
+ int err;
+
+ if (fdt_get_address(&fdt) == 0) {
+ return -ENOENT;
+ }
+
+ node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
+ if (node < 0) {
+ panic();
+ }
+
+ err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata);
+ if (err != 0) {
+ return err;
+ }
+
+ err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata);
+ if (err != 0) {
+ return err;
+ }
+
+ err = stm32_clk_parse_fdt_by_name(fdt, node, "st,busclk", pdata->busclk, &pdata->nbusclk);
+ if (err != 0) {
+ return err;
+ }
+
+ err = stm32_clk_parse_fdt_by_name(fdt, node, "st,flexgen", pdata->flexgen,
+ &pdata->nflexgen);
+ if (err != 0) {
+ return err;
+ }
+
+ err = stm32_clk_parse_fdt_by_name(fdt, node, "st,kerclk", pdata->kernelclk,
+ &pdata->nkernelclk);
+ if (err != 0) {
+ return err;
+ }
+
+ return 0;
+}
+#endif /* IMAGE_BL2 */
+
+static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR];
+
+static struct stm32_pll_dt_cfg mp25_pll[_PLL_NB];
+
+#define DT_FLEXGEN_CLK_MAX 64
+static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX];
+
+#define DT_BUS_CLK_MAX 6
+static uint32_t mp25_busclk[DT_BUS_CLK_MAX];
+
+#define DT_KERNEL_CLK_MAX 20
+static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX];
+
+static struct stm32_clk_platdata stm32mp25_pdata = {
+ .osci = mp25_osci,
+ .nosci = NB_OSCILLATOR,
+ .pll = mp25_pll,
+ .npll = _PLL_NB,
+ .flexgen = mp25_flexgen,
+ .nflexgen = DT_FLEXGEN_CLK_MAX,
+ .busclk = mp25_busclk,
+ .nbusclk = DT_BUS_CLK_MAX,
+ .kernelclk = mp25_kernelclk,
+ .nkernelclk = DT_KERNEL_CLK_MAX,
+};
+
+static uint8_t refcounts_mp25[CK_LAST];
+
+static struct stm32_clk_priv stm32mp25_clock_data = {
+ .base = RCC_BASE,
+ .num = ARRAY_SIZE(stm32mp25_clk),
+ .clks = stm32mp25_clk,
+ .parents = parent_mp25,
+ .nb_parents = ARRAY_SIZE(parent_mp25),
+ .gates = gates_mp25,
+ .nb_gates = ARRAY_SIZE(gates_mp25),
+ .div = dividers_mp25,
+ .nb_div = ARRAY_SIZE(dividers_mp25),
+ .osci_data = stm32mp25_osc_data,
+ .nb_osci_data = ARRAY_SIZE(stm32mp25_osc_data),
+ .gate_refcounts = refcounts_mp25,
+ .pdata = &stm32mp25_pdata,
+ .ops_array = ops_array_mp25,
+};
+
+int stm32mp2_clk_init(void)
+{
+ uintptr_t base = RCC_BASE;
+ int ret;
+
+#ifdef IMAGE_BL2
+ ret = stm32_clk_parse_fdt(&stm32mp25_pdata);
+ if (ret != 0) {
+ return ret;
+ }
+#endif
+
+ ret = clk_stm32_init(&stm32mp25_clock_data, base);
+ if (ret != 0) {
+ return ret;
+ }
+
+#ifdef IMAGE_BL2
+ ret = stm32mp2_init_clock_tree();
+ if (ret != 0) {
+ return ret;
+ }
+
+ clk_stm32_enable_critical_clocks();
+#endif
+
+ return 0;
+}
+
+int stm32mp2_pll1_disable(void)
+{
+#ifdef IMAGE_BL2
+ return -EPERM;
+#else
+ uintptr_t a35_ss_address = A35SSC_BASE;
+ uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE;
+
+ stm32mp2_a35_ss_on_hsi();
+
+ mmio_clrbits_32(pll_enable_reg, A35_SS_PLL_ENABLE_PD);
+
+ return 0;
+#endif
+}
diff --git a/drivers/st/reset/stm32mp1_reset.c b/drivers/st/reset/stm32mp1_reset.c
index 98c8dcf..8b828a1 100644
--- a/drivers/st/reset/stm32mp1_reset.c
+++ b/drivers/st/reset/stm32mp1_reset.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2018-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,6 @@
#include <errno.h>
#include <limits.h>
-#include <platform_def.h>
-
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
@@ -16,6 +14,8 @@
#include <lib/mmio.h>
#include <lib/utils_def.h>
+#include <platform_def.h>
+
static uint32_t id2reg_offset(unsigned int reset_id)
{
return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t);
@@ -67,3 +67,16 @@
return 0;
}
+
+void __dead2 stm32mp_system_reset(void)
+{
+ uintptr_t rcc_base = stm32mp_rcc_base();
+
+ mmio_setbits_32(rcc_base + RCC_MP_GRSTCSETR,
+ RCC_MP_GRSTCSETR_MPSYSRST);
+
+ /* Loop in case system reset is not immediately caught */
+ while (true) {
+ wfi();
+ }
+}
diff --git a/drivers/st/reset/stm32mp2_reset.c b/drivers/st/reset/stm32mp2_reset.c
new file mode 100644
index 0000000..0918df5
--- /dev/null
+++ b/drivers/st/reset/stm32mp2_reset.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/st/stm32mp_reset.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include <platform_def.h>
+
+static uint32_t id2reg_offset(unsigned int reset_id)
+{
+ return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t);
+}
+
+static uint8_t id2reg_bit_pos(unsigned int reset_id)
+{
+ return (uint8_t)(reset_id & GENMASK(4, 0));
+}
+
+static int reset_toggle(uint32_t id, unsigned int to_us, bool reset_status)
+{
+ uint32_t offset = id2reg_offset(id);
+ uint32_t bitmsk = BIT(id2reg_bit_pos(id));
+ uint32_t bit_check;
+ uintptr_t rcc_base = stm32mp_rcc_base();
+
+ if (reset_status) {
+ mmio_setbits_32(rcc_base + offset, bitmsk);
+ bit_check = bitmsk;
+ } else {
+ mmio_clrbits_32(rcc_base + offset, bitmsk);
+ bit_check = 0U;
+ }
+
+ if (to_us != 0U) {
+ uint64_t timeout_ref = timeout_init_us(to_us);
+
+ while ((mmio_read_32(rcc_base + offset) & bitmsk) != bit_check) {
+ if (timeout_elapsed(timeout_ref)) {
+ return -ETIMEDOUT;
+ }
+ }
+ }
+
+ return 0;
+}
+
+int stm32mp_reset_assert(uint32_t id, unsigned int to_us)
+{
+ return reset_toggle(id, to_us, true);
+}
+
+int stm32mp_reset_deassert(uint32_t id, unsigned int to_us)
+{
+ return reset_toggle(id, to_us, false);
+}
+
+void __dead2 stm32mp_system_reset(void)
+{
+ uintptr_t rcc_base = stm32mp_rcc_base();
+
+ mmio_setbits_32(rcc_base + RCC_GRSTCSETR, RCC_GRSTCSETR_SYSRST);
+
+ /* Loop in case system reset is not immediately caught */
+ while (true) {
+ wfi();
+ }
+}
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index c741be0..71b3cb1 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -92,6 +92,11 @@
reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
};
+ dsu-pmu {
+ compatible = "arm,dsu-pmu";
+ cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
+ };
+
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index df0dcc3..52ed2b9 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -114,9 +114,14 @@
* Definitions for EL2 system registers for save/restore routine
******************************************************************************/
#define CNTPOFF_EL2 S3_4_C14_C0_6
-#define HAFGRTR_EL2 S3_4_C3_C1_6
+#define HDFGRTR2_EL2 S3_4_C3_C1_0
+#define HDFGWTR2_EL2 S3_4_C3_C1_1
+#define HFGRTR2_EL2 S3_4_C3_C1_2
+#define HFGWTR2_EL2 S3_4_C3_C1_3
#define HDFGRTR_EL2 S3_4_C3_C1_4
#define HDFGWTR_EL2 S3_4_C3_C1_5
+#define HAFGRTR_EL2 S3_4_C3_C1_6
+#define HFGITR2_EL2 S3_4_C3_C1_7
#define HFGITR_EL2 S3_4_C1_C1_6
#define HFGRTR_EL2 S3_4_C1_C1_4
#define HFGWTR_EL2 S3_4_C1_C1_5
@@ -224,6 +229,11 @@
#define EL_IMPL_A64ONLY ULL(1)
#define EL_IMPL_A64_A32 ULL(2)
+/* ID_AA64DFR0_EL1.DebugVer definitions */
+#define ID_AA64DFR0_DEBUGVER_SHIFT U(0)
+#define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf)
+#define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb)
+
/* ID_AA64DFR0_EL1.TraceVer definitions */
#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
@@ -326,6 +336,7 @@
#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
+#define FGT2_IMPLEMENTED ULL(0x2)
#define FGT_IMPLEMENTED ULL(0x1)
#define FGT_NOT_IMPLEMENTED ULL(0x0)
@@ -569,6 +580,7 @@
/* SCR definitions */
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
#define SCR_NSE_SHIFT U(62)
+#define SCR_FGTEN2_BIT (UL(1) << 59)
#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
#define SCR_GPF_BIT (UL(1) << 48)
#define SCR_TWEDEL_SHIFT U(30)
@@ -607,6 +619,7 @@
#define SCR_RESET_VAL SCR_RES1_BITS
/* MDCR_EL3 definitions */
+#define MDCR_EBWE_BIT (ULL(1) << 43)
#define MDCR_EnPMSN_BIT (ULL(1) << 36)
#define MDCR_MPMX_BIT (ULL(1) << 35)
#define MDCR_MCCD_BIT (ULL(1) << 34)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index ddc1c80..c63eec8 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -130,6 +130,8 @@
* +----------------------------+
* | FEAT_MTPMU |
* +----------------------------+
+ * | FEAT_FGT2 |
+ * +----------------------------+
*/
static inline bool is_armv7_gentimer_present(void)
@@ -216,6 +218,10 @@
CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT)
+/* FEAT_FGT2: Fine-grained traps extended */
+CREATE_FEATURE_FUNCS(feat_fgt2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
+ ID_AA64MMFR0_EL1_FGT_MASK, FGT2_IMPLEMENTED, ENABLE_FEAT_FGT2)
+
/* FEAT_ECV: Enhanced Counter Virtualization */
CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV)
@@ -288,6 +294,23 @@
CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM)
+/*
+ * FEAT_DebugV8P9: Debug extension. This function checks the field 3:0 of
+ * ID_AA64DFR0 Aarch64 Debug Feature Register 0 for the version of
+ * Feat_Debug supported. The value of the field determines feature presence
+ *
+ * 0b0110 - Arm v8.0 debug
+ * 0b0111 - Arm v8.0 debug architecture with Virtualization host extensions
+ * 0x1000 - FEAT_Debugv8p2 is supported
+ * 0x1001 - FEAT_Debugv8p4 is supported
+ * 0x1010 - FEAT_Debugv8p8 is supported
+ * 0x1011 - FEAT_Debugv8p9 is supported
+ *
+ */
+CREATE_FEATURE_FUNCS(feat_debugv8p9, id_aa64dfr0_el1, ID_AA64DFR0_DEBUGVER_SHIFT,
+ ID_AA64DFR0_DEBUGVER_MASK, DEBUGVER_V8P9_IMPLEMENTED,
+ ENABLE_FEAT_DEBUGV8P9)
+
/* FEAT_HCX: Extended Hypervisor Configuration Register */
CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX)
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 1e2f84b..a892654 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -639,6 +639,13 @@
/* Armv8.9 system registers */
DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1)
+/* Armv8.9 FEAT_FGT2 Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr2_el2, HDFGRTR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr2_el2, HDFGWTR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr2_el2, HFGITR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr2_el2, HFGRTR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr2_el2, HFGWTR2_EL2)
+
/* FEAT_TCR2 Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el1, TCR2_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2)
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
index 9524f72..41fc6f4 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
@@ -6,6 +6,7 @@
#define S32CC_CLK_MODULES_H
#include <inttypes.h>
+#include <stdbool.h>
#include <stddef.h>
#define MHZ UL(1000000)
@@ -14,12 +15,19 @@
enum s32cc_clkm_type {
s32cc_osc_t,
s32cc_clk_t,
+ s32cc_pll_t,
+ s32cc_pll_out_div_t,
+ s32cc_clkmux_t,
+ s32cc_shared_clkmux_t,
+ s32cc_fixed_div_t,
};
enum s32cc_clk_source {
S32CC_FIRC,
S32CC_FXOSC,
S32CC_SIRC,
+ S32CC_ARM_PLL,
+ S32CC_CGM1,
};
struct s32cc_clk_obj {
@@ -42,6 +50,93 @@
.source = (SOURCE), \
}
+struct s32cc_clkmux {
+ struct s32cc_clk_obj desc;
+ enum s32cc_clk_source module;
+ uint8_t index; /* Mux index in parent module */
+ unsigned long source_id; /* Selected source */
+ uint8_t nclks; /* Number of input clocks */
+ unsigned long clkids[5]; /* IDs of the input clocks */
+};
+
+#define S32CC_CLKMUX_TYPE_INIT(TYPE, MODULE, INDEX, NCLKS, ...) \
+{ \
+ .desc = { \
+ .type = (TYPE), \
+ }, \
+ .module = (MODULE), \
+ .index = (INDEX), \
+ .nclks = (NCLKS), \
+ .clkids = {__VA_ARGS__}, \
+}
+
+#define S32CC_CLKMUX_INIT(MODULE, INDEX, NCLKS, ...) \
+ S32CC_CLKMUX_TYPE_INIT(s32cc_clkmux_t, MODULE, \
+ INDEX, NCLKS, __VA_ARGS__)
+
+#define S32CC_SHARED_CLKMUX_INIT(MODULE, INDEX, NCLKS, ...) \
+ S32CC_CLKMUX_TYPE_INIT(s32cc_shared_clkmux_t, MODULE, \
+ INDEX, NCLKS, __VA_ARGS__)
+
+struct s32cc_pll {
+ struct s32cc_clk_obj desc;
+ struct s32cc_clk_obj *source;
+ enum s32cc_clk_source instance;
+ unsigned long vco_freq;
+ uint32_t ndividers;
+ uintptr_t base;
+};
+
+#define S32CC_PLL_INIT(PLL_MUX_CLK, INSTANCE, NDIVIDERS) \
+{ \
+ .desc = { \
+ .type = s32cc_pll_t, \
+ }, \
+ .source = &(PLL_MUX_CLK).desc, \
+ .instance = (INSTANCE), \
+ .ndividers = (NDIVIDERS), \
+}
+
+struct s32cc_pll_out_div {
+ struct s32cc_clk_obj desc;
+ struct s32cc_clk_obj *parent;
+ uint32_t index;
+ unsigned long freq;
+};
+
+#define S32CC_PLL_OUT_DIV_INIT(PARENT, INDEX) \
+{ \
+ .desc = { \
+ .type = s32cc_pll_out_div_t, \
+ }, \
+ .parent = &(PARENT).desc, \
+ .index = (INDEX), \
+}
+
+#define S32CC_PLL_OUT_DIV_INIT(PARENT, INDEX) \
+{ \
+ .desc = { \
+ .type = s32cc_pll_out_div_t, \
+ }, \
+ .parent = &(PARENT).desc, \
+ .index = (INDEX), \
+}
+
+struct s32cc_fixed_div {
+ struct s32cc_clk_obj desc;
+ struct s32cc_clk_obj *parent;
+ uint32_t rate_div;
+};
+
+#define S32CC_FIXED_DIV_INIT(PARENT, RATE_DIV) \
+{ \
+ .desc = { \
+ .type = s32cc_fixed_div_t, \
+ }, \
+ .parent = &(PARENT).desc, \
+ .rate_div = (RATE_DIV), \
+}
+
struct s32cc_clk {
struct s32cc_clk_obj desc;
struct s32cc_clk_obj *module;
@@ -88,4 +183,58 @@
return (struct s32cc_clk *)clk_addr;
}
+static inline bool is_s32cc_clk_mux(const struct s32cc_clk *clk)
+{
+ const struct s32cc_clk_obj *module;
+
+ module = clk->module;
+ if (module == NULL) {
+ return false;
+ }
+
+ return (module->type == s32cc_clkmux_t) ||
+ (module->type == s32cc_shared_clkmux_t);
+}
+
+static inline struct s32cc_clkmux *s32cc_obj2clkmux(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t cmux_addr;
+
+ cmux_addr = ((uintptr_t)mod) - offsetof(struct s32cc_clkmux, desc);
+ return (struct s32cc_clkmux *)cmux_addr;
+}
+
+static inline struct s32cc_clkmux *s32cc_clk2mux(const struct s32cc_clk *clk)
+{
+ if (!is_s32cc_clk_mux(clk)) {
+ return NULL;
+ }
+
+ return s32cc_obj2clkmux(clk->module);
+}
+
+static inline struct s32cc_pll *s32cc_obj2pll(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t pll_addr;
+
+ pll_addr = ((uintptr_t)mod) - offsetof(struct s32cc_pll, desc);
+ return (struct s32cc_pll *)pll_addr;
+}
+
+static inline struct s32cc_pll_out_div *s32cc_obj2plldiv(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t plldiv_addr;
+
+ plldiv_addr = ((uintptr_t)mod) - offsetof(struct s32cc_pll_out_div, desc);
+ return (struct s32cc_pll_out_div *)plldiv_addr;
+}
+
+static inline struct s32cc_fixed_div *s32cc_obj2fixeddiv(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t fdiv_addr;
+
+ fdiv_addr = ((uintptr_t)mod) - offsetof(struct s32cc_fixed_div, desc);
+ return (struct s32cc_fixed_div *)fdiv_addr;
+}
+
#endif /* S32CC_CLK_MODULES_H */
diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h
index 9dd25f3..d5d228c 100644
--- a/include/drivers/st/stm32mp25_rcc.h
+++ b/include/drivers/st/stm32mp25_rcc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -426,7 +426,7 @@
#define RCC_USB2CFGR U(0x7FC)
#define RCC_USB2PHY1CFGR U(0x800)
#define RCC_USB2PHY2CFGR U(0x804)
-#define RCC_USB3DRDCFGR U(0x808)
+#define RCC_USB3DRCFGR U(0x808)
#define RCC_USB3PCIEPHYCFGR U(0x80C)
#define RCC_PCIECFGR U(0x810)
#define RCC_USBTCCFGR U(0x814)
@@ -459,7 +459,6 @@
#define RCC_IWDG5CFGR U(0x898)
#define RCC_WWDG1CFGR U(0x89C)
#define RCC_WWDG2CFGR U(0x8A0)
-#define RCC_BUSPERFMCFGR U(0x8A4)
#define RCC_VREFCFGR U(0x8A8)
#define RCC_TMPSENSCFGR U(0x8AC)
#define RCC_CRCCFGR U(0x8B4)
@@ -2352,11 +2351,13 @@
/* RCC_C1SREQSETR register fields */
#define RCC_C1SREQSETR_STPREQ_P0 BIT(0)
#define RCC_C1SREQSETR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQSETR_STPREQ_MASK GENMASK_32(1, 0)
#define RCC_C1SREQSETR_ESLPREQ BIT(16)
/* RCC_C1SREQCLRR register fields */
#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0)
#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQCLRR_STPREQ_MASK GENMASK_32(1, 0)
#define RCC_C1SREQCLRR_ESLPREQ BIT(16)
/* RCC_CPUBOOTCR register fields */
@@ -2401,12 +2402,12 @@
#define RCC_BDCR_LSEDRV_WIDTH 2
/* RCC_D3DCR register fields */
-#define RCC_D3DCR_CSION BIT(0)
-#define RCC_D3DCR_CSIKERON BIT(1)
-#define RCC_D3DCR_CSIRDY BIT(2)
+#define RCC_D3DCR_MSION BIT(0)
+#define RCC_D3DCR_MSIKERON BIT(1)
+#define RCC_D3DCR_MSIRDY BIT(2)
#define RCC_D3DCR_D3PERCKSEL_MASK GENMASK_32(17, 16)
#define RCC_D3DCR_D3PERCKSEL_SHIFT 16
-#define RCC_D3DCR_CSIRDY_BIT 2
+#define RCC_D3DCR_MSIRDY_BIT 2
/* RCC_D3DSR register fields */
#define RCC_D3DSR_D3STATE_MASK GENMASK_32(1, 0)
@@ -3458,11 +3459,11 @@
#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4)
#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15)
-/* RCC_USB3DRDCFGR register fields */
-#define RCC_USB3DRDCFGR_USB3DRDRST BIT(0)
-#define RCC_USB3DRDCFGR_USB3DRDEN BIT(1)
-#define RCC_USB3DRDCFGR_USB3DRDLPEN BIT(2)
-#define RCC_USB3DRDCFGR_USB3DRDSTPEN BIT(4)
+/* RCC_USB3DRCFGR register fields */
+#define RCC_USB3DRCFGR_USB3DRRST BIT(0)
+#define RCC_USB3DRCFGR_USB3DREN BIT(1)
+#define RCC_USB3DRCFGR_USB3DRLPEN BIT(2)
+#define RCC_USB3DRCFGR_USB3DRSTPEN BIT(4)
/* RCC_USB3PCIEPHYCFGR register fields */
#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYRST BIT(0)
@@ -3647,11 +3648,6 @@
#define RCC_WWDG2CFGR_WWDG2LPEN BIT(2)
#define RCC_WWDG2CFGR_WWDG2AMEN BIT(3)
-/* RCC_BUSPERFMCFGR register fields */
-#define RCC_BUSPERFMCFGR_BUSPERFMRST BIT(0)
-#define RCC_BUSPERFMCFGR_BUSPERFMEN BIT(1)
-#define RCC_BUSPERFMCFGR_BUSPERFMLPEN BIT(2)
-
/* RCC_VREFCFGR register fields */
#define RCC_VREFCFGR_VREFRST BIT(0)
#define RCC_VREFCFGR_VREFEN BIT(1)
diff --git a/include/drivers/st/stm32mp2_clk.h b/include/drivers/st/stm32mp2_clk.h
new file mode 100644
index 0000000..b9226cd
--- /dev/null
+++ b/include/drivers/st/stm32mp2_clk.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP2_CLK_H
+#define STM32MP2_CLK_H
+
+#include <platform_def.h>
+
+enum stm32mp_osc_id {
+ _HSI,
+ _HSE,
+ _CSI,
+ _LSI,
+ _LSE,
+ _I2S_CKIN,
+ _SPDIF_SYMB,
+ NB_OSC,
+ _UNKNOWN_OSC_ID = 0xFF
+};
+
+extern const char *stm32mp_osc_node_label[NB_OSC];
+
+enum pll_cfg {
+ FBDIV,
+ REFDIV,
+ POSTDIV1,
+ POSTDIV2,
+ PLLCFG_NB
+};
+
+enum pll_csg {
+ DIVVAL,
+ SPREAD,
+ DOWNSPREAD,
+ PLLCSG_NB
+};
+
+int stm32mp2_clk_init(void);
+int stm32mp2_pll1_disable(void);
+
+#endif /* STM32MP2_CLK_H */
diff --git a/include/drivers/st/stm32mp_reset.h b/include/drivers/st/stm32mp_reset.h
index 8444805..a8648b4 100644
--- a/include/drivers/st/stm32mp_reset.h
+++ b/include/drivers/st/stm32mp_reset.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2018-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,4 +47,9 @@
(void)stm32mp_reset_deassert(reset_id, 0U);
}
+/*
+ * Manage system reset control
+ */
+void __dead2 stm32mp_system_reset(void);
+
#endif /* STM32MP_RESET_H */
diff --git a/include/dt-bindings/clock/stm32mp25-clks.h b/include/dt-bindings/clock/stm32mp25-clks.h
index c4ff9cf..e7ab5b0 100644
--- a/include/dt-bindings/clock/stm32mp25-clks.h
+++ b/include/dt-bindings/clock/stm32mp25-clks.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
- * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
- * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
+ * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
*/
#ifndef _DT_BINDINGS_STM32MP25_CLKS_H_
@@ -109,7 +109,7 @@
/* LOW SPEED MCU CLOCK */
#define CK_ICN_LS_MCU 88
-#define CK_BUS_STM500 89
+#define CK_BUS_STM 89
#define CK_BUS_FMC 90
#define CK_BUS_GPU 91
#define CK_BUS_ETH1 92
@@ -233,7 +233,6 @@
#define CK_BUS_DDRCFG 210
#define CK_BUS_GICV2M 211
#define CK_BUS_USBTC 212
-#define CK_BUS_BUSPERFM 213
#define CK_BUS_USB3PCIEPHY 214
#define CK_BUS_STGEN 215
#define CK_BUS_VDEC 216
@@ -272,7 +271,7 @@
#define CK_BUS_RISAF4 249
#define CK_BUS_USB2OHCI 250
#define CK_BUS_USB2EHCI 251
-#define CK_BUS_USB3DRD 252
+#define CK_BUS_USB3DR 252
#define CK_KER_LPTIM1 253
#define CK_KER_LPTIM2 254
#define CK_KER_USART2 255
@@ -364,8 +363,10 @@
#define CK_BUS_ETHSWACMCFG 341
#define CK_BUS_ETHSWACMMSG 342
#define HSE_DIV2_CK 343
+#define CK_KER_ETR 344
+#define CK_KER_STM 345
-#define STM32MP25_LAST_CLK 344
+#define STM32MP25_LAST_CLK 346
#define CK_SCMI_ICN_HS_MCU 0
#define CK_SCMI_ICN_SDMMC 1
@@ -453,8 +454,7 @@
#define CK_SCMI_TIMG2 83
#define CK_SCMI_BKPSRAM 84
#define CK_SCMI_BSEC 85
-#define CK_SCMI_BUSPERFM 86
-#define CK_SCMI_ETR 87
+#define CK_SCMI_BUS_ETR 87
#define CK_SCMI_FMC 88
#define CK_SCMI_GPIOA 89
#define CK_SCMI_GPIOB 90
@@ -489,6 +489,8 @@
#define CK_SCMI_SYSDBG 119
#define CK_SCMI_SYSATB 120
#define CK_SCMI_TSDBG 121
-#define CK_SCMI_STM500 122
+#define CK_SCMI_BUS_STM 122
+#define CK_SCMI_KER_STM 123
+#define CK_SCMI_KER_ETR 124
#endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stm32mp25-clksrc.h b/include/dt-bindings/clock/stm32mp25-clksrc.h
index e6f7154..319fd82 100644
--- a/include/dt-bindings/clock/stm32mp25-clksrc.h
+++ b/include/dt-bindings/clock/stm32mp25-clksrc.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
- * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
*/
#ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_
@@ -108,9 +108,8 @@
#define MUX_DSIPHY 18
#define MUX_LVDSPHY 19
#define MUX_DTS 20
-#define MUX_CPU1 21
-#define MUX_D3PER 22
-#define MUX_NB 23
+#define MUX_D3PER 21
+#define MUX_NB 22
#define MUXSEL_HSI 0
#define MUXSEL_HSE 1
@@ -144,7 +143,7 @@
#define MUX_USB3PCIEPHY_FLEX34 0x0
#define MUX_USB3PCIEPHY_HSE 0x1
-#define MUX_DSIBLANE_FLEX28 0x0
+#define MUX_DSIBLANE_DSIPHY 0x0
#define MUX_DSIBLANE_FLEX27 0x1
#define MUX_DSIPHY_FLEX28 0x0
@@ -219,8 +218,8 @@
/* define for st,drive */
#define LSEDRV_LOWEST 0
-#define LSEDRV_MEDIUM_LOW 1
-#define LSEDRV_MEDIUM_HIGH 2
+#define LSEDRV_MEDIUM_LOW 2
+#define LSEDRV_MEDIUM_HIGH 1
#define LSEDRV_HIGHEST 3
#endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */
diff --git a/include/dt-bindings/reset/stm32mp25-resets.h b/include/dt-bindings/reset/stm32mp25-resets.h
index c34fe2a..99b8058 100644
--- a/include/dt-bindings/reset/stm32mp25-resets.h
+++ b/include/dt-bindings/reset/stm32mp25-resets.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
/*
- * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
* Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
@@ -14,16 +14,16 @@
#define C2_R 8288
#define C2_HOLDBOOT_R 8608
#define C1_HOLDBOOT_R 8609
-#define VSW_R 8703
-#define C1MS_R 8808
-#define IWDG2_KER_R 9074
-#define IWDG4_KER_R 9202
-#define C3_R 9312
-#define DDRCP_R 9856
-#define DDRCAPB_R 9888
-#define DDRPHYCAPB_R 9920
-#define DDRCFG_R 9984
-#define DDR_R 10016
+#define VSW_R 8735
+#define C1MS_R 8840
+#define IWDG2_KER_R 9106
+#define IWDG4_KER_R 9234
+#define C3_R 9344
+#define DDRCP_R 9888
+#define DDRCAPB_R 9920
+#define DDRPHYCAPB_R 9952
+#define DDRCFG_R 10016
+#define DDR_R 10048
#define OSPI1_R 10400
#define OSPI1DLL_R 10416
#define OSPI2_R 10432
@@ -115,7 +115,7 @@
#define USB2_R 16352
#define USB2PHY1_R 16384
#define USB2PHY2_R 16416
-#define USB3DRD_R 16448
+#define USB3DR_R 16448
#define USB3PCIEPHY_R 16480
#define PCIE_R 16512
#define USBTC_R 16544
@@ -143,7 +143,6 @@
#define CRYP2_R 17440
#define WWDG1_R 17632
#define WWDG2_R 17664
-#define BUSPERFM_R 17696
#define VREF_R 17728
#define DTS_R 17760
#define CRC_R 17824
@@ -159,6 +158,9 @@
#define RST_SCMI_C1_HOLDBOOT_R 2
#define RST_SCMI_C2_HOLDBOOT_R 3
#define RST_SCMI_FMC 4
-#define RST_SCMI_PCIE 5
+#define RST_SCMI_OSPI1 5
+#define RST_SCMI_OSPI1DLL 6
+#define RST_SCMI_OSPI2 7
+#define RST_SCMI_OSPI2DLL 8
#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */
diff --git a/include/lib/cpus/aarch64/cortex_a520.h b/include/lib/cpus/aarch64/cortex_a520.h
index 619a15d..ed3401d 100644
--- a/include/lib/cpus/aarch64/cortex_a520.h
+++ b/include/lib/cpus/aarch64/cortex_a520.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,6 +15,7 @@
#define CORTEX_A520_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT U(0)
/*******************************************************************************
* CPU Auxiliary Control register 1 specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_a725.h b/include/lib/cpus/aarch64/cortex_a725.h
index 123c5ab..cb1c099 100644
--- a/include/lib/cpus/aarch64/cortex_a725.h
+++ b/include/lib/cpus/aarch64/cortex_a725.h
@@ -13,6 +13,7 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_A725_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A725_CPUECTLR_EL1_EXTLLC_BIT U(0)
/*******************************************************************************
* CPU Power Control register specific definitions
diff --git a/include/lib/cpus/aarch64/cortex_x925.h b/include/lib/cpus/aarch64/cortex_x925.h
index 38aafcf..b0d0ca4 100644
--- a/include/lib/cpus/aarch64/cortex_x925.h
+++ b/include/lib/cpus/aarch64/cortex_x925.h
@@ -13,6 +13,7 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_X925_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_X925_CPUECTLR_EL1_EXTLLC_BIT U(0)
/*******************************************************************************
* CPU Power Control register specific definitions
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 6faef5d..d49d82e 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -456,6 +456,14 @@
msr \_reg, x0
.endm
+.macro sysreg_bitfield_insert_from_gpr _reg:req, _gpr:req, _lsb:req, _width:req
+ /* Source value in register for BFI */
+ mov x1, \_gpr
+ mrs x0, \_reg
+ bfi x0, x1, #\_lsb, #\_width
+ msr \_reg, x0
+.endm
+
/*
* Apply erratum
*
diff --git a/include/lib/el3_runtime/context_el2.h b/include/lib/el3_runtime/context_el2.h
index d25ab81..ca1ea4e 100644
--- a/include/lib/el3_runtime/context_el2.h
+++ b/include/lib/el3_runtime/context_el2.h
@@ -62,6 +62,14 @@
uint64_t hfgwtr_el2;
} el2_fgt_regs_t;
+typedef struct el2_fgt2_regs {
+ uint64_t hdfgrtr2_el2;
+ uint64_t hdfgwtr2_el2;
+ uint64_t hfgitr2_el2;
+ uint64_t hfgrtr2_el2;
+ uint64_t hfgwtr2_el2;
+} el2_fgt2_regs_t;
+
typedef struct el2_ecv_regs {
uint64_t cntpoff_el2;
} el2_ecv_regs_t;
@@ -140,6 +148,10 @@
el2_fgt_regs_t fgt;
#endif
+#if ENABLE_FEAT_FGT2
+ el2_fgt2_regs_t fgt2;
+#endif
+
#if ENABLE_FEAT_ECV
el2_ecv_regs_t ecv;
#endif
@@ -221,6 +233,15 @@
#define write_el2_ctx_fgt(ctx, reg, val)
#endif /* ENABLE_FEAT_FGT */
+#if ENABLE_FEAT_FGT2
+#define read_el2_ctx_fgt2(ctx, reg) (((ctx)->fgt2).reg)
+#define write_el2_ctx_fgt2(ctx, reg, val) ((((ctx)->fgt2).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el2_ctx_fgt2(ctx, reg) ULL(0)
+#define write_el2_ctx_fgt2(ctx, reg, val)
+#endif /* ENABLE_FEAT_FGT */
+
#if ENABLE_FEAT_ECV
#define read_el2_ctx_ecv(ctx, reg) (((ctx)->ecv).reg)
#define write_el2_ctx_ecv(ctx, reg, val) ((((ctx)->ecv).reg) \
diff --git a/include/lib/extensions/debug_v8p9.h b/include/lib/extensions/debug_v8p9.h
new file mode 100644
index 0000000..d72c9ea
--- /dev/null
+++ b/include/lib/extensions/debug_v8p9.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DEBUG_V8P9_H
+#define DEBUG_V8P9_H
+
+#include <context.h>
+
+#if ENABLE_FEAT_DEBUGV8P9
+void debugv8p9_extended_bp_wp_enable(cpu_context_t *ctx);
+#else
+static inline void debugv8p9_extended_bp_wp_enable(cpu_context_t *ctx)
+{
+}
+#endif /* ENABLE_FEAT_DEBUGV8P9 */
+
+#endif /* DEBUG_V8P9_H */
diff --git a/include/lib/extensions/fgt2.h b/include/lib/extensions/fgt2.h
new file mode 100644
index 0000000..0388d18
--- /dev/null
+++ b/include/lib/extensions/fgt2.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FGT2_H
+#define FGT2_H
+
+#include <context.h>
+
+#if ENABLE_FEAT_FGT2
+void fgt2_enable(cpu_context_t *ctx);
+#else
+static inline void fgt2_enable(cpu_context_t *ctx)
+{
+}
+#endif /* ENABLE_FEAT_FGT2 */
+
+#endif /* FGT2_H */
diff --git a/include/lib/psa/rse_crypto_defs.h b/include/lib/psa/rse_crypto_defs.h
index 44936b8..b94664f 100644
--- a/include/lib/psa/rse_crypto_defs.h
+++ b/include/lib/psa/rse_crypto_defs.h
@@ -16,7 +16,7 @@
* to the corresponding API implementation in the Crypto service backend.
*
*/
-#define RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID (uint16_t)(0x701)
+#define RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID (uint16_t)(0x206)
/*
* The persistent key identifiers for RSE builtin keys.
diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index 2d0949b..5434a9a 100644
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -171,8 +171,10 @@
#define SHAREABILITY_SHIFT 8
/* The Access Flag, AF. */
#define ACCESS_FLAG_SHIFT 10
-/* The not global bit, nG. */
+/* The not global bit, nG */
#define NOT_GLOBAL_SHIFT 11
+/* The Non-secure Extension bit, NSE */
+#define NSE_SHIFT 11
/* Contiguous hint bit. */
#define CONT_HINT_SHIFT 52
/* Execute-never bits, XN. */
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index 4e9bdfc..27cfc91 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -51,9 +51,9 @@
}
} else {
if (cve) {
- VERBOSE(CVE_FORMAT, BL_STRING, cpu_str, cve, id, "not applied");
+ VERBOSE(CVE_FORMAT, BL_STRING, cpu_str, cve, id, "not applicable");
} else {
- VERBOSE(ERRATUM_FORMAT, BL_STRING, cpu_str, id, "not applied");
+ VERBOSE(ERRATUM_FORMAT, BL_STRING, cpu_str, id, "not applicable");
}
}
}
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 981fddc..c525247 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -24,6 +24,8 @@
#include <lib/el3_runtime/pubsub_events.h>
#include <lib/extensions/amu.h>
#include <lib/extensions/brbe.h>
+#include <lib/extensions/debug_v8p9.h>
+#include <lib/extensions/fgt2.h>
#include <lib/extensions/mpam.h>
#include <lib/extensions/pmuv3.h>
#include <lib/extensions/sme.h>
@@ -334,6 +336,12 @@
u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val);
+
+ /*
+ * The actlr_el2 register can be initialized in platform's reset handler
+ * and it may contain access control bits (e.g. CLUSTERPMUEN bit).
+ */
+ write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2());
#endif /* CTX_INCLUDE_EL2_REGS */
/* Start with a clean SCR_EL3 copy as all relevant values are set */
@@ -736,7 +744,7 @@
if (is_feat_trbe_supported()) {
/*
- * Enable FEAT_SPE for Non-Secure and prohibit for Secure and
+ * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and
* Realm state.
*/
trbe_enable(ctx);
@@ -744,14 +752,14 @@
if (is_feat_trf_supported()) {
/*
- * Enable FEAT_SPE for Non-Secure and prohibit for Secure state.
+ * Enable FEAT_TRF for Non-Secure and prohibit for Secure state.
*/
trf_enable(ctx);
}
if (is_feat_brbe_supported()) {
/*
- * Enable FEAT_SPE for Non-Secure and prohibit for Secure state.
+ * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state.
*/
brbe_enable(ctx);
}
@@ -772,6 +780,14 @@
sme_enable(ctx);
}
+ if (is_feat_fgt2_supported()) {
+ fgt2_enable(ctx);
+ }
+
+ if (is_feat_debugv8p9_supported()) {
+ debugv8p9_extended_bp_wp_enable(ctx);
+ }
+
pmuv3_enable(ctx);
#endif /* IMAGE_BL31 */
}
@@ -1098,6 +1114,24 @@
write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2));
}
+static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx)
+{
+ write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2());
+ write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2());
+ write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2());
+ write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2());
+ write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2());
+}
+
+static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx)
+{
+ write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2));
+ write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2));
+ write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2));
+ write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2));
+ write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2));
+}
+
static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx)
{
u_register_t mpam_idr = read_mpamidr_el1();
@@ -1337,6 +1371,10 @@
el2_sysregs_context_save_fgt(el2_sysregs_ctx);
}
+ if (is_feat_fgt2_supported()) {
+ el2_sysregs_context_save_fgt2(el2_sysregs_ctx);
+ }
+
if (is_feat_ecv_v2_supported()) {
write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2());
}
@@ -1420,6 +1458,10 @@
el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
}
+ if (is_feat_fgt2_supported()) {
+ el2_sysregs_context_restore_fgt2(el2_sysregs_ctx);
+ }
+
if (is_feat_ecv_v2_supported()) {
write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2));
}
diff --git a/lib/extensions/debug/debugv8p9.c b/lib/extensions/debug/debugv8p9.c
new file mode 100644
index 0000000..f3cffa7
--- /dev/null
+++ b/lib/extensions/debug/debugv8p9.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_features.h>
+#include <arch_helpers.h>
+#include <lib/extensions/debug_v8p9.h>
+
+void debugv8p9_extended_bp_wp_enable(cpu_context_t *ctx)
+{
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
+
+ /* When FEAT_Debugv8p9 is implemented:
+ *
+ * MDCR_EL3.EBWE: Set to 0b1
+ * Enables use of additional breakpoints or watchpoints,
+ * and disables trap to EL3 on accesses to debug register.
+ */
+
+ mdcr_el3_val |= MDCR_EBWE_BIT;
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
+}
diff --git a/lib/extensions/fgt/fgt2.c b/lib/extensions/fgt/fgt2.c
new file mode 100644
index 0000000..78f1a82
--- /dev/null
+++ b/lib/extensions/fgt/fgt2.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_features.h>
+#include <arch_helpers.h>
+#include <lib/extensions/fgt2.h>
+
+void fgt2_enable(cpu_context_t *context)
+{
+ u_register_t reg;
+ el3_state_t *state;
+
+ state = get_el3state_ctx(context);
+
+ /* Set the FGTEN2 bit in SCR_EL3 to enable access to HFGITR2_EL2,
+ * HFGRTR2_EL2, HFGWTR_EL2, HDFGRTR2_EL2, and HDFGWTR2_EL2.
+ */
+
+ reg = read_ctx_reg(state, CTX_SCR_EL3);
+ reg |= SCR_FGTEN2_BIT;
+ write_ctx_reg(state, CTX_SCR_EL3, reg);
+}
+
diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c
index f3a53cc..a3b913c 100644
--- a/lib/xlat_tables_v2/xlat_tables_utils.c
+++ b/lib/xlat_tables_v2/xlat_tables_utils.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,7 @@
#include <platform_def.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/utils_def.h>
@@ -419,10 +420,59 @@
*attributes |= MT_USER;
}
- uint64_t ns_bit = (desc >> NS_SHIFT) & 1U;
+ uint64_t ns_bit = (desc >> NS_SHIFT) & 1ULL;
- if (ns_bit == 1U)
+#if ENABLE_RME
+ uint64_t nse_bit = (desc >> NSE_SHIFT) & 1ULL;
+ uint32_t sec_state = (uint32_t)(ns_bit | (nse_bit << 1ULL));
+
+/*
+ * =========================================================
+ * NSE NS | Output PA space
+ * =========================================================
+ * 0 0 | Secure (if S-EL2 is present, else invalid)
+ * 0 1 | Non-secure
+ * 1 0 | Root
+ * 1 1 | Realm
+ *==========================================================
+ */
+ switch (sec_state) {
+ case 0U:
+ /*
+ * We expect to get Secure mapping on an RME system only if
+ * S-EL2 is enabled.
+ * Hence panic() if we hit the case without EEL2 being enabled.
+ */
+ if ((read_scr_el3() & SCR_EEL2_BIT) == 0ULL) {
+ ERROR("A secure descriptor is not supported when"
+ "FEAT_RME is implemented and FEAT_SEL2 is"
+ "not enabled\n");
+ panic();
+ } else {
+ *attributes |= MT_SECURE;
+ }
+ break;
+ case 1U:
*attributes |= MT_NS;
+ break;
+ case 2U:
+ *attributes |= MT_ROOT;
+ break;
+ case 3U:
+ *attributes |= MT_REALM;
+ break;
+ default:
+ /* unreachable code */
+ assert(false);
+ break;
+ }
+#else /* !ENABLE_RME */
+ if (ns_bit == 1ULL) {
+ *attributes |= MT_NS;
+ } else {
+ *attributes |= MT_SECURE;
+ }
+#endif /* ENABLE_RME */
uint64_t xn_mask = xlat_arch_regime_get_xn_desc(ctx->xlat_regime);
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index ac47960..3097181 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -90,7 +90,7 @@
# Enable the features which are mandatory from ARCH version 8.9 and upwards.
ifeq "8.9" "$(word 1, $(sort 8.9 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-armv8-9-a-feats := ENABLE_FEAT_TCR2
+armv8-9-a-feats := ENABLE_FEAT_TCR2 ENABLE_FEAT_DEBUGV8P9
# 8.8 Compliant
armv8-9-a-feats += ${armv8-8-a-feats}
FEAT_LIST := ${armv8-9-a-feats}
@@ -337,6 +337,9 @@
# Disable MTPMU if FEAT_MTPMU is supported.
DISABLE_MTPMU ?= 0
+# Flag to enable FEAT_FGT2 (Fine Granular Traps 2)
+ENABLE_FEAT_FGT2 ?= 0
+
#----
# 8.9
#----
@@ -353,6 +356,9 @@
# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE).
ENABLE_FEAT_S1POE ?= 0
+# Flag to enable access to Arm v8.9 Debug extension
+ENABLE_FEAT_DEBUGV8P9 ?= 0
+
#----
# 9.0
#----
diff --git a/package-lock.json b/package-lock.json
index a6bb905..26caae4 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -1172,12 +1172,12 @@
}
},
"node_modules/braces": {
- "version": "3.0.2",
- "resolved": "https://registry.npmjs.org/braces/-/braces-3.0.2.tgz",
- "integrity": "sha512-b8um+L1RzM3WDSzvhm6gIz1yfTbBt6YTlcEKAvsmqCZZFw46z626lVj9j1yEPW33H5H+lBQpZMP1k8l+78Ha0A==",
+ "version": "3.0.3",
+ "resolved": "https://registry.npmjs.org/braces/-/braces-3.0.3.tgz",
+ "integrity": "sha512-yQbXgO/OSZVD2IsiLlro+7Hf6Q18EJrKSEsdoMzKePKXct3gvD8oLcOQdIzGupr5Fj+EDe8gO/lxc1BzfMpxvA==",
"dev": true,
"dependencies": {
- "fill-range": "^7.0.1"
+ "fill-range": "^7.1.1"
},
"engines": {
"node": ">=8"
@@ -2395,9 +2395,9 @@
}
},
"node_modules/fill-range": {
- "version": "7.0.1",
- "resolved": "https://registry.npmjs.org/fill-range/-/fill-range-7.0.1.tgz",
- "integrity": "sha512-qOo9F+dMUmC2Lcb4BbVvnKJxTPjCm+RRpe4gDuGrzkL7mEVl/djYSu2OdQ2Pa302N4oqkSg9ir6jaLWJ2USVpQ==",
+ "version": "7.1.1",
+ "resolved": "https://registry.npmjs.org/fill-range/-/fill-range-7.1.1.tgz",
+ "integrity": "sha512-YsGpe3WHLK8ZYi4tWDg2Jy3ebRz2rXowDxnld4bkQB00cc/1Zw9AWnC0i9ztDJitivtQvaI9KaLyKrc+hBW0yg==",
"dev": true,
"dependencies": {
"to-regex-range": "^5.0.1"
@@ -4903,7 +4903,7 @@
}
},
"tools/conventional-changelog-tf-a": {
- "version": "2.10.0",
+ "version": "2.11.0",
"dev": true,
"license": "BSD-3-Clause",
"dependencies": {
diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
index ee07605..51d696c 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
@@ -7,6 +7,7 @@
#include <lib/psci/psci.h>
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
+#include <plat/common/platform.h>
/*******************************************************************************
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
* platform layer will take care of registering the handlers with PSCI.
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_el1_optee_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_el1_optee_manifest.dts
new file mode 100644
index 0000000..36a22a1
--- /dev/null
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_el1_optee_manifest.dts
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "arm,ffa-core-manifest-1.0";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ attribute {
+ spmc_id = <0x8000>;
+ maj_ver = <0x1>;
+ min_ver = <0x1>;
+ exec_state = <0x0>;
+ load_address = <0x0 0x6000000>;
+ entrypoint = <0x0 0x6000000>;
+ binary_size = <0x80000>;
+ };
+};
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
index d90544b..234ab587 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
@@ -35,7 +35,7 @@
debug_name = "op-tee";
load_address = <0x6280000>;
vcpu_count = <8>;
- mem_size = <1048576>;
+ mem_size = <0xd80000>;
};
};
@@ -63,10 +63,11 @@
reg = <0x0 0x6000000 0x0 0x2000000>; /* Trusted DRAM */
};
- memory@1 {
+ memory@80000000 {
device_type = "ns-memory";
- reg = <0x00008800 0x80000000 0x0 0x7f000000>,
- <0x0 0x88000000 0x0 0x10000000>;
+ reg = <0x0 0x80000000 0x0 0x7c000000>,
+ <0x8 0x80000000 0x1 0x80000000>,
+ <0x00008800 0x80000000 0x0 0x7f000000>;
};
memory@0 {
diff --git a/plat/arm/board/fvp/fdts/optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
index 27f4724..a6b4886 100644
--- a/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -15,23 +15,30 @@
/* Properties */
description = "op-tee";
- ffa-version = <0x00010000>; /* 31:16 - Major, 15:0 - Minor */
+ ffa-version = <0x00010001>; /* 31:16 - Major, 15:0 - Minor */
uuid = <0xe0786148 0xe311f8e7 0x02005ebc 0x1bc5d5a5>;
id = <1>;
execution-ctx-count = <8>;
exception-level = <2>; /* S-EL1 */
execution-state = <0>; /* AARCH64 */
load-address = <0x6280000>;
+ mem-size = <0xd80000>; /* OP-TEE specific extension */
entrypoint-offset = <0x4000>;
xlat-granule = <0>; /* 4KiB */
boot-order = <0>;
messaging-method = <0x3>; /* Direct request/response supported. */
- managed-exit;
+ ns-interrupts-action = <1>; /* NS_ACTION_ME */
run-time-model = <1>; /* SP pre-emptible. */
/* Boot protocol */
gp-register-num = <0x0>;
+ /* Boot Info */
+ boot-info {
+ compatible = "arm,ffa-manifest-boot-info";
+ ffa_manifest;
+ };
+
device-regions {
compatible = "arm,ffa-manifest-device-regions";
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index af2b78d..6d63646 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -57,6 +57,7 @@
ENABLE_SYS_REG_TRACE_FOR_NS := 2
ENABLE_FEAT_CSV2_2 := 2
ENABLE_FEAT_CSV2_3 := 2
+ENABLE_FEAT_DEBUGV8P9 := 2
ENABLE_FEAT_DIT := 2
ENABLE_FEAT_PAN := 2
ENABLE_FEAT_VHE := 2
@@ -65,6 +66,7 @@
ENABLE_TRF_FOR_NS := 2
ENABLE_FEAT_ECV := 2
ENABLE_FEAT_FGT := 2
+ENABLE_FEAT_FGT2 := 2
ENABLE_FEAT_TCR2 := 2
ENABLE_FEAT_S2PIE := 2
ENABLE_FEAT_S1PIE := 2
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
index 391c68c..86d82e2 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
@@ -28,13 +28,13 @@
#define RD_V2_SID_VER_PART_NUM 0x07F2
#define RD_V2_CONFIG_ID 0x1
-/* SID Version values for RD-Fremont */
-#define RD_FREMONT_SID_VER_PART_NUM 0x07EE
-#define RD_FREMONT_CONFIG_ID 0x0
+/* SID Version values for RD-V3 */
+#define RD_V3_SID_VER_PART_NUM 0x07EE
+#define RD_V3_CONFIG_ID 0x0
-/* SID Version values for RD-Fremont variants */
-#define RD_FREMONT_CFG1_SID_VER_PART_NUM 0x07F9
-#define RD_FREMONT_CFG2_SID_VER_PART_NUM 0x07EE
+/* SID Version values for RD-V3 variants */
+#define RD_V3_CFG1_SID_VER_PART_NUM 0x07F9
+#define RD_V3_CFG2_SID_VER_PART_NUM 0x07EE
/* Structure containing Neoverse RD platform variant information */
typedef struct nrd_platform_info {
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index 5a7dfb1..18aa2fb 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -131,9 +131,9 @@
panic();
}
return &plat_rd_scmi_info[channel_id];
- } else if (nrd_plat_info.platform_id == RD_FREMONT_SID_VER_PART_NUM ||
- nrd_plat_info.platform_id == RD_FREMONT_CFG1_SID_VER_PART_NUM ||
- nrd_plat_info.platform_id == RD_FREMONT_CFG2_SID_VER_PART_NUM) {
+ } else if (nrd_plat_info.platform_id == RD_V3_SID_VER_PART_NUM ||
+ nrd_plat_info.platform_id == RD_V3_CFG1_SID_VER_PART_NUM ||
+ nrd_plat_info.platform_id == RD_V3_CFG2_SID_VER_PART_NUM) {
if (channel_id >= ARRAY_SIZE(plat3_rd_scmi_info)) {
panic();
}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts
similarity index 100%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_fw_config.dts
rename to plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_fw_config.dts
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_nt_fw_config.dts
similarity index 92%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_nt_fw_config.dts
rename to plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_nt_fw_config.dts
index 62cad39..941d4a0 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_nt_fw_config.dts
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_nt_fw_config.dts
@@ -7,7 +7,7 @@
/dts-v1/;
/ {
/* compatible string */
- compatible = "arm,rd-fremont";
+ compatible = "arm,rd-v3";
/*
* Place holder for system-id node with default values. The
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts
similarity index 100%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_tb_fw_config.dts
rename to plat/arm/board/neoverse_rd/platform/rdv3/fdts/rdv3_tb_fw_config.dts
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv3/include/platform_def.h
similarity index 100%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h
rename to plat/arm/board/neoverse_rd/platform/rdv3/include/platform_def.h
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_mhuv3.h b/plat/arm/board/neoverse_rd/platform/rdv3/include/rdv3_mhuv3.h
similarity index 69%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_mhuv3.h
rename to plat/arm/board/neoverse_rd/platform/rdv3/include/rdv3_mhuv3.h
index 400dcc5..fa64963 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_mhuv3.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/include/rdv3_mhuv3.h
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef RDFREMONT_MHUV3_H
-#define RDFREMONT_MHUV3_H
+#ifndef RDV3_MHUV3_H
+#define RDV3_MHUV3_H
void mhu_v3_get_secure_device_base(uintptr_t *base, bool sender);
-#endif /* RDFREMONT_MHUV3_H */
+#endif /* RDV3_MHUV3_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_rse_comms.h b/plat/arm/board/neoverse_rd/platform/rdv3/include/rdv3_rse_comms.h
similarity index 62%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_rse_comms.h
rename to plat/arm/board/neoverse_rd/platform/rdv3/include/rdv3_rse_comms.h
index ad1bc23..cb8e786 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_rse_comms.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/include/rdv3_rse_comms.h
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef RDFREMONT_RSE_COMMS_H
-#define RDFREMONT_RSE_COMMS_H
+#ifndef RDV3_RSE_COMMS_H
+#define RDV3_RSE_COMMS_H
int plat_rse_comms_init(void);
-#endif /* RDFREMONT_RSE_COMMS_H */
+#endif /* RDV3_RSE_COMMS_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
similarity index 67%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
rename to plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
index bca6172..7d770f5 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
@@ -3,16 +3,16 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-RD_FREMONT_VARIANTS := 0 1 2
+RD_V3_VARIANTS := 0 1 2
ifneq ($(NRD_PLATFORM_VARIANT), \
- $(filter $(NRD_PLATFORM_VARIANT),$(RD_FREMONT_VARIANTS)))
- $(error "NRD_PLATFORM_VARIANT for RD-FREMONT should be 0, 1, or 2,"
+ $(filter $(NRD_PLATFORM_VARIANT),$(RD_V3_VARIANTS)))
+ $(error "NRD_PLATFORM_VARIANT for RD-V3 should be 0, 1, or 2,"
"currently set to ${NRD_PLATFORM_VARIANT}.")
endif
$(eval $(call CREATE_SEQ,SEQ,4))
ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
- $(error "Chip count for RD-Fremont-MC should be either $(SEQ) \
+ $(error "Chip count for RD-V3-MC should be either $(SEQ) \
currently it is set to ${NRD_CHIP_COUNT}.")
endif
@@ -30,7 +30,7 @@
# Misc options
override CTX_INCLUDE_AARCH32_REGS := 0
-# RD-Fremont platform uses GIC-700 which is based on GICv4.1
+# RD-V3 platform uses GIC-700 which is based on GICv4.1
GIC_ENABLE_V4_EXTN := 1
# Enable GIC multichip extension only for multichip platforms
@@ -38,7 +38,7 @@
GICV3_IMPL_GIC600_MULTICHIP := 1
endif
-# RD-Fremont uses MHUv3
+# RD-V3 uses MHUv3
PLAT_MHU_VERSION := 3
include plat/arm/board/neoverse_rd/common/nrd-common.mk
@@ -48,58 +48,58 @@
include drivers/measured_boot/rse/rse_measured_boot.mk
endif
-RDFREMONT_BASE = plat/arm/board/neoverse_rd/platform/rdfremont
+RDV3_BASE = plat/arm/board/neoverse_rd/platform/rdv3
PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd3/ \
- -I${RDFREMONT_BASE}/include/ \
+ -I${RDV3_BASE}/include/ \
-Iinclude/lib/psa
NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v3.S
-# Source files for RD-Fremont variants
+# Source files for RD-V3 variants
PLAT_BL_COMMON_SOURCES \
+= ${NRD_COMMON_BASE}/nrd_plat3.c \
- ${RDFREMONT_BASE}/rdfremont_common.c
+ ${RDV3_BASE}/rdv3_common.c
PLAT_MEASURED_BOOT_SOURCES \
:= ${MEASURED_BOOT_SOURCES} \
${RSE_COMMS_SOURCES} \
- ${RDFREMONT_BASE}/rdfremont_common_measured_boot.c \
+ ${RDV3_BASE}/rdv3_common_measured_boot.c \
lib/psa/measured_boot.c
BL1_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDFREMONT_BASE}/rdfremont_err.c \
- ${RDFREMONT_BASE}/rdfremont_mhuv3.c
+ ${RDV3_BASE}/rdv3_err.c \
+ ${RDV3_BASE}/rdv3_mhuv3.c
ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += ${RDFREMONT_BASE}/rdfremont_trusted_boot.c
+BL1_SOURCES += ${RDV3_BASE}/rdv3_trusted_boot.c
endif
ifeq (${MEASURED_BOOT},1)
BL1_SOURCES += ${PLAT_MEASURED_BOOT_SOURCES} \
- ${RDFREMONT_BASE}/rdfremont_bl1_measured_boot.c
+ ${RDV3_BASE}/rdv3_bl1_measured_boot.c
endif
-BL2_SOURCES += ${RDFREMONT_BASE}/rdfremont_bl2_setup.c \
- ${RDFREMONT_BASE}/rdfremont_err.c \
- ${RDFREMONT_BASE}/rdfremont_mhuv3.c \
- ${RDFREMONT_BASE}/rdfremont_security.c \
+BL2_SOURCES += ${RDV3_BASE}/rdv3_bl2_setup.c \
+ ${RDV3_BASE}/rdv3_err.c \
+ ${RDV3_BASE}/rdv3_mhuv3.c \
+ ${RDV3_BASE}/rdv3_security.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL2_SOURCES += ${RDFREMONT_BASE}/rdfremont_trusted_boot.c
+BL2_SOURCES += ${RDV3_BASE}/rdv3_trusted_boot.c
endif
ifeq (${MEASURED_BOOT},1)
BL2_SOURCES += ${PLAT_MEASURED_BOOT_SOURCES} \
- ${RDFREMONT_BASE}/rdfremont_bl2_measured_boot.c
+ ${RDV3_BASE}/rdv3_bl2_measured_boot.c
endif
BL31_SOURCES += ${NRD_CPU_SOURCES} \
${MBEDTLS_SOURCES} \
${RSE_COMMS_SOURCES} \
- ${RDFREMONT_BASE}/rdfremont_bl31_setup.c \
- ${RDFREMONT_BASE}/rdfremont_mhuv3.c \
- ${RDFREMONT_BASE}/rdfremont_topology.c \
- ${RDFREMONT_BASE}/rdfremont_plat_attest_token.c \
- ${RDFREMONT_BASE}/rdfremont_realm_attest_key.c \
+ ${RDV3_BASE}/rdv3_bl31_setup.c \
+ ${RDV3_BASE}/rdv3_mhuv3.c \
+ ${RDV3_BASE}/rdv3_topology.c \
+ ${RDV3_BASE}/rdv3_plat_attest_token.c \
+ ${RDV3_BASE}/rdv3_realm_attest_key.c \
drivers/arm/smmu/smmu_v3.c \
drivers/cfi/v2m/v2m_flash.c \
lib/psa/cca_attestation.c \
@@ -111,14 +111,14 @@
BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
endif
-# XLAT options for RD-Fremont variants
+# XLAT options for RD-V3 variants
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
BL2_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${RDFREMONT_BASE}/fdts/${PLAT}_fw_config.dts \
- ${RDFREMONT_BASE}/fdts/${PLAT}_tb_fw_config.dts \
- ${RDFREMONT_BASE}/fdts/${PLAT}_nt_fw_config.dts
+FDT_SOURCES += ${RDV3_BASE}/fdts/${PLAT}_fw_config.dts \
+ ${RDV3_BASE}/fdts/${PLAT}_tb_fw_config.dts \
+ ${RDV3_BASE}/fdts/${PLAT}_nt_fw_config.dts
FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
@@ -131,7 +131,7 @@
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
-# Features for RD-Fremont variants
+# Features for RD-V3 variants
override ENABLE_FEAT_MPAM := 2
override ENABLE_FEAT_AMU := 2
override ENABLE_SVE_FOR_SWD := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl1_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl1_measured_boot.c
similarity index 88%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl1_measured_boot.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl1_measured_boot.c
index 92e96c2..4db9a11 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl1_measured_boot.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl1_measured_boot.c
@@ -13,13 +13,13 @@
#include <platform_def.h>
#include <nrd_plat.h>
-#include <rdfremont_rse_comms.h>
+#include <rdv3_rse_comms.h>
/*
* Platform specific table with image IDs and metadata. Intentionally not a
* const struct, some members might set by bootloaders during trusted boot.
*/
-struct rse_mboot_metadata rdfremont_rse_mboot_metadata[] = {
+struct rse_mboot_metadata rdv3_rse_mboot_metadata[] = {
{
.id = FW_CONFIG_ID,
.slot = U(8),
@@ -51,7 +51,7 @@
/* Initialize the communication channel between AP and RSE */
(void)plat_rse_comms_init();
- rse_measured_boot_init(rdfremont_rse_mboot_metadata);
+ rse_measured_boot_init(rdv3_rse_mboot_metadata);
}
void bl1_plat_mboot_finish(void)
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_measured_boot.c
similarity index 90%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_measured_boot.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_measured_boot.c
index 570c33a..1b94427 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_measured_boot.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_measured_boot.c
@@ -13,13 +13,13 @@
#include <platform_def.h>
#include <nrd_plat.h>
-#include <rdfremont_rse_comms.h>
+#include <rdv3_rse_comms.h>
/*
* Platform specific table with image IDs and metadata. Intentionally not a
* const struct, some members might set by bootloaders during trusted boot.
*/
-struct rse_mboot_metadata rdfremont_rse_mboot_metadata[] = {
+struct rse_mboot_metadata rdv3_rse_mboot_metadata[] = {
{
.id = BL31_IMAGE_ID,
.slot = U(11),
@@ -60,7 +60,7 @@
/* Initialize the communication channel between AP and RSE */
(void)plat_rse_comms_init();
- rse_measured_boot_init(rdfremont_rse_mboot_metadata);
+ rse_measured_boot_init(rdv3_rse_mboot_metadata);
}
void bl2_plat_mboot_finish(void)
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_setup.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_setup.c
similarity index 100%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_setup.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl2_setup.c
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
similarity index 80%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
index 8544930..21675f6 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_bl31_setup.c
@@ -13,10 +13,10 @@
#include <plat/common/platform.h>
#include <nrd_plat.h>
#include <nrd_variant.h>
-#include <rdfremont_rse_comms.h>
+#include <rdv3_rse_comms.h>
#if (NRD_PLATFORM_VARIANT == 2)
-static const mmap_region_t rdfremontmc_dynamic_mmap[] = {
+static const mmap_region_t rdv3mc_dynamic_mmap[] = {
#if NRD_CHIP_COUNT > 1
NRD_CSS_SHARED_RAM_MMAP(1),
NRD_CSS_PERIPH_MMAP(1),
@@ -31,7 +31,7 @@
#endif
};
-static struct gic600_multichip_data rdfremontmc_multichip_data __init = {
+static struct gic600_multichip_data rdv3mc_multichip_data __init = {
.rt_owner_base = PLAT_ARM_GICD_BASE,
.rt_owner = 0,
.chip_count = NRD_CHIP_COUNT,
@@ -61,7 +61,7 @@
}
};
-static uintptr_t rdfremontmc_multichip_gicr_frames[] = {
+static uintptr_t rdv3mc_multichip_gicr_frames[] = {
/* Chip 0's GICR Base */
PLAT_ARM_GICR_BASE,
#if NRD_CHIP_COUNT > 1
@@ -84,7 +84,7 @@
{
/*
* Perform SMMUv3 GPT configuration for the GPC SMMU present in system
- * control block on RD-Fremont platforms. This SMMUv3 initialization is
+ * control block on RD-V3 platforms. This SMMUv3 initialization is
* not fatal.
*
* Don't perform smmuv3_security_init() for this instance of SMMUv3 as
@@ -104,14 +104,14 @@
NRD_CHIP_COUNT);
panic();
} else {
- INFO("Enabling multi-chip support for RD-Fremont variant\n");
+ INFO("Enabling multi-chip support for RD-V3 variant\n");
- for (i = 0; i < ARRAY_SIZE(rdfremontmc_dynamic_mmap); i++) {
+ for (i = 0; i < ARRAY_SIZE(rdv3mc_dynamic_mmap); i++) {
ret = mmap_add_dynamic_region(
- rdfremontmc_dynamic_mmap[i].base_pa,
- rdfremontmc_dynamic_mmap[i].base_va,
- rdfremontmc_dynamic_mmap[i].size,
- rdfremontmc_dynamic_mmap[i].attr);
+ rdv3mc_dynamic_mmap[i].base_pa,
+ rdv3mc_dynamic_mmap[i].base_va,
+ rdv3mc_dynamic_mmap[i].size,
+ rdv3mc_dynamic_mmap[i].attr);
if (ret != 0) {
ERROR("Failed to add entry i: %d (ret=%d)\n",
i, ret);
@@ -120,8 +120,8 @@
}
plat_arm_override_gicr_frames(
- rdfremontmc_multichip_gicr_frames);
- gic600_multichip_init(&rdfremontmc_multichip_data);
+ rdv3mc_multichip_gicr_frames);
+ gic600_multichip_init(&rdv3mc_multichip_data);
}
#endif /* NRD_PLATFORM_VARIANT == 2 */
nrd_bl31_common_platform_setup();
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c
similarity index 98%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c
index 31cc2a0..10fe666 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common.c
@@ -11,8 +11,8 @@
#include <plat/common/platform.h>
#include <platform_def.h>
#include <nrd_plat.h>
-#include <rdfremont_mhuv3.h>
-#include <rdfremont_rse_comms.h>
+#include <rdv3_mhuv3.h>
+#include <rdv3_rse_comms.h>
unsigned int plat_arm_nrd_get_platform_id(void)
{
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
similarity index 76%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common_measured_boot.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
index e95c544..f5160ce 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common_measured_boot.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
@@ -10,11 +10,11 @@
#include <common/desc_image_load.h>
#include <drivers/measured_boot/rse/rse_measured_boot.h>
-extern struct rse_mboot_metadata rdfremont_rse_mboot_metadata[];
+extern struct rse_mboot_metadata rdv3_rse_mboot_metadata[];
struct rse_mboot_metadata *plat_rse_mboot_get_metadata(void)
{
- return rdfremont_rse_mboot_metadata;
+ return rdv3_rse_mboot_metadata;
}
int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
@@ -22,7 +22,7 @@
int err;
/* Calculate image hash and record data in RSE */
- err = rse_mboot_measure_and_record(rdfremont_rse_mboot_metadata,
+ err = rse_mboot_measure_and_record(rdv3_rse_mboot_metadata,
image_data->image_base,
image_data->image_size,
image_id);
@@ -36,6 +36,6 @@
int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
{
- return rse_mboot_set_signer_id(rdfremont_rse_mboot_metadata, pk_oid,
+ return rse_mboot_set_signer_id(rdv3_rse_mboot_metadata, pk_oid,
pk_ptr, pk_len);
}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_err.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_err.c
similarity index 89%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_err.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_err.c
index de6cc68..270febf 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_err.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_err.c
@@ -7,7 +7,7 @@
#include <plat/arm/common/plat_arm.h>
/*
- * rdfremont error handler
+ * rdv3 error handler
*/
void __dead2 plat_arm_error_handler(int err)
{
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_mhuv3.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_mhuv3.c
similarity index 92%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_mhuv3.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_mhuv3.c
index 41332cc..738f753 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_mhuv3.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_mhuv3.c
@@ -11,7 +11,7 @@
#include <nrd_css_def3.h>
#include <nrd_plat.h>
-#include <rdfremont_mhuv3.h>
+#include <rdv3_mhuv3.h>
void mhu_v3_get_secure_device_base(uintptr_t *base, bool sender)
{
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_plat_attest_token.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c
similarity index 100%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_plat_attest_token.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_plat_attest_token.c
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_realm_attest_key.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_realm_attest_key.c
similarity index 100%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_realm_attest_key.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_realm_attest_key.c
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_security.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_security.c
similarity index 100%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_security.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_security.c
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_topology.c
similarity index 97%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_topology.c
index e7931d4..6eb5002 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_topology.c
@@ -10,7 +10,7 @@
/******************************************************************************
* The power domain tree descriptor.
******************************************************************************/
-const unsigned char rd_fremont_pd_tree_desc[] = {
+const unsigned char rd_v3_pd_tree_desc[] = {
(PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
@@ -44,7 +44,7 @@
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
- return rd_fremont_pd_tree_desc;
+ return rd_v3_pd_tree_desc;
}
/*******************************************************************************
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_trusted_boot.c
similarity index 100%
rename from plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_trusted_boot.c
rename to plat/arm/board/neoverse_rd/platform/rdv3/rdv3_trusted_boot.c
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 38413ef..45d17ba 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -7,6 +7,7 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
+#include <cortex_a520.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/board_css_def.h>
@@ -333,6 +334,7 @@
*/
#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000
+#if TARGET_PLATFORM <= 2
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x25000000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
@@ -360,6 +362,7 @@
PLAT_ARM_TZC_NS_DEV_ACCESS}, \
{PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
+#endif
/* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
@@ -444,6 +447,21 @@
#define SLC_DONT_ALLOC 0
#define SLC_ALWAYS_ALLOC 1
#define SLC_ALLOC_BUS_SIGNAL_ATTR 2
+
+#define MCN_CONFIG_OFFSET 0x204
+#define MCN_CONFIG_ADDR (MCN_BASE_ADDR + MCN_CONFIG_OFFSET)
+#define MCN_CONFIG_SLC_PRESENT_BIT 3
+
+/*
+ * TC3 CPUs have the same definitions for:
+ * CORTEX_{A520|A725|X925}_CPUECTLR_EL1
+ * CORTEX_{A520|A725|X925}_CPUECTLR_EL1_EXTLLC_BIT
+ * Define the common macros for easier using.
+ */
+#define CPUECTLR_EL1 CORTEX_A520_CPUECTLR_EL1
+#define CPUECTLR_EL1_EXTLLC_BIT CORTEX_A520_CPUECTLR_EL1_EXTLLC_BIT
#endif /* TARGET_PLATFORM == 3 */
+#define CPUACTLR_CLUSTERPMUEN (ULL(1) << 12)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S
index 5f54856..29130ea 100644
--- a/plat/arm/board/tc/include/tc_helpers.S
+++ b/plat/arm/board/tc/include/tc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,9 @@
#include <platform_def.h>
#include <cpu_macros.S>
+#define TC_HANDLER(rev) plat_reset_handler_tc##rev
+#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev)
+
.globl plat_arm_calc_core_pos
.globl plat_reset_handler
@@ -49,13 +52,42 @@
ret
endfunc plat_arm_calc_core_pos
+func mark_extllc_presence
+#ifdef MCN_CONFIG_ADDR
+ mov_imm x0, (MCN_CONFIG_ADDR)
+ ldr w1, [x0]
+ ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1
+ sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, \
+ CPUECTLR_EL1_EXTLLC_BIT, 1
+#endif
+ ret
+endfunc mark_extllc_presence
+
+func enable_dsu_pmu_el1_access
+ sysreg_bit_set actlr_el2, CPUACTLR_CLUSTERPMUEN
+ sysreg_bit_set actlr_el3, CPUACTLR_CLUSTERPMUEN
+ ret
+endfunc enable_dsu_pmu_el1_access
+
+func TC_HANDLER(2)
+ ret
+endfunc TC_HANDLER(2)
+
+func TC_HANDLER(3)
+ mov x9, lr
+ bl mark_extllc_presence
+ bl enable_dsu_pmu_el1_access
+ mov lr, x9
+ ret
+endfunc TC_HANDLER(3)
+
/* -----------------------------------------------------
* void plat_reset_handler(void);
- *
- * Determine the CPU MIDR and disable power down bit for
- * that CPU.
* -----------------------------------------------------
*/
func plat_reset_handler
+ mov x8, lr
+ bl PLAT_RESET_HANDLER(TARGET_PLATFORM)
+ mov lr, x8
ret
endfunc plat_reset_handler
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 28b98c2..78b6945 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -33,12 +33,12 @@
ENABLE_AMU_AUXILIARY_COUNTERS := 1
ENABLE_MPMM := 1
ENABLE_MPMM_FCONF := 1
+ENABLE_FEAT_MTE2 := 2
CTX_INCLUDE_AARCH32_REGS := 0
ifeq (${SPD},spmd)
SPMD_SPM_AT_SEL2 := 1
- ENABLE_FEAT_MTE2 := 1
CTX_INCLUDE_PAUTH_REGS := 1
endif
@@ -129,6 +129,7 @@
BL1_SOURCES += ${INTERCONNECT_SOURCES} \
${TC_CPU_SOURCES} \
${TC_BASE}/tc_trusted_boot.c \
+ ${TC_BASE}/tc_bl1_setup.c \
${TC_BASE}/tc_err.c \
drivers/arm/sbsa/sbsa.c
@@ -138,9 +139,12 @@
${TC_BASE}/tc_bl2_setup.c \
lib/utils/mem_region.c \
drivers/arm/tzc/tzc400.c \
- plat/arm/common/arm_tzc400.c \
plat/arm/common/arm_nor_psci_mem_protect.c
+ifeq ($(shell test $(TARGET_PLATFORM) -le 2; echo $$?),0)
+BL2_SOURCES += plat/arm/common/arm_tzc400.c
+endif
+
BL31_SOURCES += ${INTERCONNECT_SOURCES} \
${TC_CPU_SOURCES} \
${ENT_GIC_SOURCES} \
@@ -258,5 +262,4 @@
include plat/arm/common/arm_common.mk
include plat/arm/css/common/css_common.mk
-include plat/arm/soc/common/soc_css.mk
include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/tc/tc_bl1_setup.c b/plat/arm/board/tc/tc_bl1_setup.c
new file mode 100644
index 0000000..aedc94f
--- /dev/null
+++ b/plat/arm/board/tc/tc_bl1_setup.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*******************************************************************************
+ * Perform any BL1 specific platform actions.
+ ******************************************************************************/
+
+void soc_css_init_nic400(void)
+{
+}
+
+void soc_css_init_pcie(void)
+{
+}
diff --git a/plat/arm/board/tc/tc_security.c b/plat/arm/board/tc/tc_security.c
index 6a34501..7c7a1a1 100644
--- a/plat/arm/board/tc/tc_security.c
+++ b/plat/arm/board/tc/tc_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,17 +7,21 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
+#if (TARGET_PLATFORM <= 2)
static const arm_tzc_regions_info_t tzc_regions[] = {
TC_TZC_REGIONS_DEF,
{}
};
+#endif
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
+#if (TARGET_PLATFORM <= 2)
unsigned int i;
for (i = 0U; i < TZC400_COUNT; i++) {
arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
}
+#endif
}
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 58a14ab..99243dc 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -335,8 +335,10 @@
void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node)
{
- assert(transfer_list_set_handoff_args(
- secure_tl, &next_param_node->ep_info) != NULL);
+ entry_point_info_t *ep __unused;
+ ep = transfer_list_set_handoff_args(secure_tl,
+ &next_param_node->ep_info);
+ assert(ep != NULL);
arm_transfer_list_populate_ep_info(next_param_node, secure_tl, ns_tl);
}
diff --git a/plat/arm/common/arm_io_storage.c b/plat/arm/common/arm_io_storage.c
index 19ee1b0..5a3d27a 100644
--- a/plat/arm/common/arm_io_storage.c
+++ b/plat/arm/common/arm_io_storage.c
@@ -124,6 +124,7 @@
const struct plat_io_policy *policy;
policy = FCONF_GET_PROPERTY(arm, io_policies, image_id);
+ assert(policy->check != NULL);
result = policy->check(policy->image_spec);
if (result == 0) {
*image_spec = policy->image_spec;
diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
index 6d8825f..18aa48e 100644
--- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
+++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
@@ -14,6 +14,7 @@
#include "cadence_qspi.h"
#include "socfpga_plat_def.h"
+#include "wdt/watchdog.h"
#define LESS(a, b) (((a) < (b)) ? (a) : (b))
#define MORE(a, b) (((a) > (b)) ? (a) : (b))
@@ -654,6 +655,9 @@
read_count += level * sizeof(uint8_t);
count++;
+#if ARM_LINUX_KERNEL_AS_BL33
+ watchdog_sw_rst();
+#endif
} while (level > 0);
}
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index 3e44833..fcee101 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -75,6 +76,7 @@
#define MBOX_RSU_STATUS 0x5B
#define MBOX_RSU_UPDATE 0x5C
#define MBOX_HPS_STAGE_NOTIFY 0x5D
+#define MBOX_RSU_GET_DEVICE_INFO 0x74
/* FCS Command */
#define MBOX_FCS_GET_PROVISION 0x7B
@@ -249,6 +251,7 @@
int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
+int mailbox_rsu_get_device_info(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_rsu_update(uint32_t *flash_offset);
int mailbox_hps_stage_notify(uint32_t execution_stage);
int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index d45ab11..d2eceb9 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -64,6 +65,7 @@
#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013
#define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014
#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015
+#define INTEL_SIP_SMC_RSU_GET_DEVICE_INFO 0xC2000016
/* Hardware monitor */
#define INTEL_SIP_SMC_HWMON_READTEMP 0xC2000020
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index e2a25ea..b8e5cde 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -578,6 +579,13 @@
return ret;
}
+int mailbox_rsu_get_device_info(uint32_t *resp_buf, unsigned int resp_buf_len)
+{
+ return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_GET_DEVICE_INFO, NULL, 0U,
+ CMD_CASUAL, resp_buf,
+ &resp_buf_len);
+}
+
int mailbox_rsu_update(uint32_t *flash_offset)
{
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE,
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 5204146..5c80798 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -777,14 +777,6 @@
VERBOSE("Deassert F2SDRAM ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_F2SSDRAM0);
-
- /*
- * Clear fpga2sdram_manager_main_SidebandManager_FlagOutClr0
- * f2s_ready_latency_enable
- */
- VERBOSE("Clear F2SDRAM f2s_ready_latency_enable ...\n");
- mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
- FLAGOUTCLR0_F2SDRAM0_ENABLE);
}
#else
if (brg_mask != 0U) {
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f68dc29..2f88c86 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -507,6 +509,16 @@
return INTEL_SIP_SMC_STATUS_OK;
}
+static uint32_t intel_rsu_get_device_info(uint32_t *respbuf,
+ unsigned int respbuf_sz)
+{
+ if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) {
+ return INTEL_SIP_SMC_RSU_ERROR;
+ }
+
+ return INTEL_SIP_SMC_STATUS_OK;
+}
+
uint32_t intel_rsu_update(uint64_t update_address)
{
if (update_address > SIZE_MAX) {
@@ -878,6 +890,16 @@
status = intel_rsu_copy_dcmf_version(x1, x2);
SMC_RET1(handle, status);
+ case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO:
+ status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf,
+ ARRAY_SIZE(rsu_respbuf));
+ if (status) {
+ SMC_RET1(handle, status);
+ } else {
+ SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1],
+ rsu_respbuf[2], rsu_respbuf[3]);
+ }
+
case INTEL_SIP_SMC_RSU_DCMF_STATUS:
SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK,
((uint64_t)rsu_dcmf_stat[3] << 48) |
diff --git a/plat/mediatek/build_helpers/mtk_build_helpers.mk b/plat/mediatek/build_helpers/mtk_build_helpers.mk
index 87a7db4..a497049 100644
--- a/plat/mediatek/build_helpers/mtk_build_helpers.mk
+++ b/plat/mediatek/build_helpers/mtk_build_helpers.mk
@@ -29,7 +29,7 @@
ifdef $(1)
ifeq ($(strip $(value $(1))),y)
DEFINES += -D$(1)$(if $(value $(1)),=1,)
-else
+else ifneq ($(strip $(value $(1))),n)
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endif
endif
diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
index f7ed5e6..efb70b7 100644
--- a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
+++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
@@ -25,6 +25,7 @@
FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
emi_mpu_set_protection(®ion_info);
+#ifndef SPD_NONE
/* BL32 address */
region_info.start = BL32_REGION_BASE;
region_info.end = BL32_REGION_BASE + BL32_REGION_SIZE - 1;
@@ -35,6 +36,7 @@
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, SEC_RW, SEC_RW);
emi_mpu_set_protection(®ion_info);
+#endif
/* SCP core0 DRAM */
region_info.start = SCP_CORE0_REGION_BASE;
diff --git a/plat/qemu/common/qemu_pm.c b/plat/qemu/common/qemu_pm.c
index c2b5091..5f64d70 100644
--- a/plat/qemu/common/qemu_pm.c
+++ b/plat/qemu/common/qemu_pm.c
@@ -102,22 +102,6 @@
}
/*******************************************************************************
- * Platform handler called to check the validity of the non secure
- * entrypoint.
- ******************************************************************************/
-static int qemu_validate_ns_entrypoint(uintptr_t entrypoint)
-{
- /*
- * Check if the non secure entrypoint lies within the non
- * secure DRAM.
- */
- if ((entrypoint >= NS_DRAM0_BASE) &&
- (entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE)))
- return PSCI_E_SUCCESS;
- return PSCI_E_INVALID_ADDRESS;
-}
-
-/*******************************************************************************
* Platform handler called when a CPU is about to enter standby.
******************************************************************************/
static void qemu_cpu_standby(plat_local_state_t cpu_state)
@@ -241,7 +225,6 @@
.system_off = qemu_system_off,
.system_reset = qemu_system_reset,
.validate_power_state = qemu_validate_power_state,
- .validate_ns_entrypoint = qemu_validate_ns_entrypoint
};
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
diff --git a/plat/rpi/rpi4/rpi4_pci_svc.c b/plat/rpi/common/rpi_pci_svc.c
similarity index 76%
rename from plat/rpi/rpi4/rpi4_pci_svc.c
rename to plat/rpi/common/rpi_pci_svc.c
index e4ef5c1..c22f6d8 100644
--- a/plat/rpi/rpi4/rpi4_pci_svc.c
+++ b/plat/rpi/common/rpi_pci_svc.c
@@ -1,9 +1,10 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
*
* SPDX-License-Identifier: BSD-3-Clause
*
- * The RPi4 has a single nonstandard PCI config region. It is broken into two
+ * The RPi has a single nonstandard PCI config region. It is broken into two
* pieces, the root port config registers and a window to a single device's
* config space which can move between devices. There isn't (yet) an
* authoritative public document on this since the available BCM2711 reference
@@ -29,62 +30,63 @@
#include <lib/mmio.h>
-static spinlock_t pci_lock;
-
-#define PCIE_REG_BASE U(RPI_IO_BASE + 0x01500000)
#define PCIE_MISC_PCIE_STATUS 0x4068
#define PCIE_EXT_CFG_INDEX 0x9000
-/* A small window pointing at the ECAM of the device selected by CFG_INDEX */
#define PCIE_EXT_CFG_DATA 0x8000
+#define PCIE_EXT_CFG_BDF_SHIFT 12
+
#define INVALID_PCI_ADDR 0xFFFFFFFF
-#define PCIE_EXT_BUS_SHIFT 20
-#define PCIE_EXT_DEV_SHIFT 15
-#define PCIE_EXT_FUN_SHIFT 12
+static spinlock_t pci_lock;
+static uint64_t pcie_rc_bases[] = { RPI_PCIE_RC_BASES };
static uint64_t pci_segment_lib_get_base(uint32_t address, uint32_t offset)
{
- uint64_t base;
- uint32_t bus, dev, fun;
- uint32_t status;
+ uint64_t base;
+ uint32_t seg, bus, dev, fun;
- base = PCIE_REG_BASE;
+ seg = PCI_ADDR_SEG(address);
- offset &= PCI_OFFSET_MASK; /* Pick off the 4k register offset */
+ if (seg >= ARRAY_SIZE(pcie_rc_bases)) {
+ return INVALID_PCI_ADDR;
+ }
/* The root port is at the base of the PCIe register space */
- if (address != 0U) {
- /*
- * The current device must be at CFG_DATA, a 4K window mapped,
- * via CFG_INDEX, to the device we are accessing. At the same
- * time we must avoid accesses to certain areas of the cfg
- * space via CFG_DATA. Detect those accesses and report that
- * the address is invalid.
- */
- base += PCIE_EXT_CFG_DATA;
- bus = PCI_ADDR_BUS(address);
- dev = PCI_ADDR_DEV(address);
- fun = PCI_ADDR_FUN(address);
- address = (bus << PCIE_EXT_BUS_SHIFT) |
- (dev << PCIE_EXT_DEV_SHIFT) |
- (fun << PCIE_EXT_FUN_SHIFT);
+ base = pcie_rc_bases[seg];
- /* Allow only dev = 0 on root port and bus 1 */
- if ((bus < 2U) && (dev > 0U)) {
- return INVALID_PCI_ADDR;
- }
+ bus = PCI_ADDR_BUS(address);
+ dev = PCI_ADDR_DEV(address);
+ fun = PCI_ADDR_FUN(address);
- /* Assure link up before reading bus 1 */
- status = mmio_read_32(PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
- if ((status & 0x30) != 0x30) {
- return INVALID_PCI_ADDR;
- }
-
- /* Adjust which device the CFG_DATA window is pointing at */
- mmio_write_32(PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, address);
+ /* There can only be the root port on bus 0 */
+ if ((bus == 0U) && ((dev > 0U) || (fun > 0U))) {
+ return INVALID_PCI_ADDR;
}
- return base + offset;
+
+ /* There can only be one device on bus 1 */
+ if ((bus == 1U) && (dev > 0U)) {
+ return INVALID_PCI_ADDR;
+ }
+
+ if (bus > 0) {
+#if RPI_PCIE_ECAM_SERROR_QUIRK
+ uint32_t status = mmio_read_32(base + PCIE_MISC_PCIE_STATUS);
+
+ /* Assure link up before accessing downstream of root port */
+ if ((status & 0x30) == 0U) {
+ return INVALID_PCI_ADDR;
+ }
+#endif
+ /*
+ * Device function is mapped at CFG_DATA, a 4 KB window
+ * movable by writing its B/D/F location to CFG_INDEX.
+ */
+ mmio_write_32(base + PCIE_EXT_CFG_INDEX, address << PCIE_EXT_CFG_BDF_SHIFT);
+ base += PCIE_EXT_CFG_DATA;
+ }
+
+ return base + (offset & PCI_OFFSET_MASK);
}
/**
@@ -130,7 +132,7 @@
*val = mmio_read_32(base);
break;
default: /* should be unreachable */
- *val = 0;
+ *val = 0U;
ret = SMC_PCI_CALL_INVAL_PARAM;
}
}
@@ -204,9 +206,12 @@
uint32_t pci_get_bus_for_seg(uint32_t seg, uint32_t *bus_range, uint32_t *nseg)
{
uint32_t ret = SMC_PCI_CALL_SUCCESS;
- *nseg = 0U; /* only a single segment */
- if (seg == 0U) {
- *bus_range = 0xFF00; /* start 0, end 255 */
+ uint32_t rc_count = ARRAY_SIZE(pcie_rc_bases);
+
+ *nseg = (seg < rc_count - 1U) ? seg + 1U : 0U;
+
+ if (seg < rc_count) {
+ *bus_range = 0U + (0xFF << 8); /* start 0, end 255 */
} else {
*bus_range = 0U;
ret = SMC_PCI_CALL_NOT_IMPL;
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
index 8162492..53ce0f8 100644
--- a/plat/rpi/rpi4/include/rpi_hw.h
+++ b/plat/rpi/rpi4/include/rpi_hw.h
@@ -69,4 +69,11 @@
#define RPI4_LOCAL_CONTROL_BASE_ADDRESS ULL(0xff800000)
#define RPI4_LOCAL_CONTROL_PRESCALER ULL(0xff800008)
+/*
+ * PCI Express
+ */
+#define RPI_PCIE_RC_BASES (RPI_IO_BASE + ULL(0x01500000))
+
+#define RPI_PCIE_ECAM_SERROR_QUIRK 1
+
#endif /* RPI_HW_H */
diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk
index f17911f..cbfa6f2 100644
--- a/plat/rpi/rpi4/platform.mk
+++ b/plat/rpi/rpi4/platform.mk
@@ -113,5 +113,5 @@
endif
ifeq ($(SMC_PCI_SUPPORT), 1)
-BL31_SOURCES += plat/rpi/rpi4/rpi4_pci_svc.c
+BL31_SOURCES += plat/rpi/common/rpi_pci_svc.c
endif
diff --git a/plat/rpi/rpi5/include/rpi_hw.h b/plat/rpi/rpi5/include/rpi_hw.h
index 384542e..a737676 100644
--- a/plat/rpi/rpi5/include/rpi_hw.h
+++ b/plat/rpi/rpi5/include/rpi_hw.h
@@ -48,4 +48,11 @@
#define RPI4_LOCAL_CONTROL_BASE_ADDRESS (RPI_IO_BASE + ULL(0x7c280000))
#define RPI4_LOCAL_CONTROL_PRESCALER (RPI_IO_BASE + ULL(0x7c280008))
+/*
+ * PCI Express
+ */
+#define RPI_PCIE_RC_BASES RPI_IO_BASE + ULL(0x00100000), \
+ RPI_IO_BASE + ULL(0x00110000), \
+ RPI_IO_BASE + ULL(0x00120000)
+
#endif /* RPI_HW_H */
diff --git a/plat/rpi/rpi5/platform.mk b/plat/rpi/rpi5/platform.mk
index 81b7ded..70c5add 100644
--- a/plat/rpi/rpi5/platform.mk
+++ b/plat/rpi/rpi5/platform.mk
@@ -86,6 +86,9 @@
# Use normal memory mapping for ROM, FIP, SRAM and DRAM
RPI3_USE_UEFI_MAP := 0
+# SMCCC PCI support (should be enabled for ACPI builds)
+SMC_PCI_SUPPORT := 0
+
# Process platform flags
# ----------------------
@@ -96,6 +99,7 @@
endif
$(eval $(call add_define,RPI3_RUNTIME_UART))
$(eval $(call add_define,RPI3_USE_UEFI_MAP))
+$(eval $(call add_define,SMC_PCI_SUPPORT))
ifeq (${ARCH},aarch32)
$(error Error: AArch32 not supported on rpi5)
@@ -105,3 +109,7 @@
PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \
plat/rpi/common/rpi3_stack_protector.c
endif
+
+ifeq ($(SMC_PCI_SUPPORT), 1)
+BL31_SOURCES += plat/rpi/common/rpi_pci_svc.c
+endif
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 2ade242..9da311e 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -331,7 +331,7 @@
print_pmic_info_and_debug();
}
- stm32mp1_syscfg_init();
+ stm32mp_syscfg_init();
if (stm32_iwdg_init() < 0) {
panic();
@@ -365,7 +365,7 @@
}
#endif
- stm32mp1_syscfg_enable_io_compensation_finish();
+ stm32mp_syscfg_enable_io_compensation_finish();
fconf_populate("TB_FW", STM32MP_DTB_BASE);
@@ -461,7 +461,8 @@
break;
case BL32_IMAGE_ID:
- if (optee_header_is_valid(bl_mem_params->image_info.image_base)) {
+ if ((bl_mem_params->image_info.image_base != 0UL) &&
+ (optee_header_is_valid(bl_mem_params->image_info.image_base))) {
image_info_t *paged_image_info = NULL;
/* BL32 is OP-TEE header */
diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index f6e5a8f..55227fb 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -14,19 +14,19 @@
void stm32mp1_arch_security_setup(void);
void stm32mp1_security_setup(void);
-void stm32mp1_syscfg_init(void);
-void stm32mp1_syscfg_enable_io_compensation_start(void);
-void stm32mp1_syscfg_enable_io_compensation_finish(void);
-void stm32mp1_syscfg_disable_io_compensation(void);
-uint32_t stm32mp1_syscfg_get_chip_version(void);
-uint32_t stm32mp1_syscfg_get_chip_dev_id(void);
+void stm32mp_syscfg_init(void);
+void stm32mp_syscfg_enable_io_compensation_start(void);
+void stm32mp_syscfg_enable_io_compensation_finish(void);
+void stm32mp_syscfg_disable_io_compensation(void);
+uint32_t stm32mp_syscfg_get_chip_version(void);
+uint32_t stm32mp_syscfg_get_chip_dev_id(void);
#if STM32MP13
-void stm32mp1_syscfg_boot_mode_enable(void);
-void stm32mp1_syscfg_boot_mode_disable(void);
+void stm32mp_syscfg_boot_mode_enable(void);
+void stm32mp_syscfg_boot_mode_disable(void);
#endif
#if STM32MP15
-static inline void stm32mp1_syscfg_boot_mode_enable(void){}
-static inline void stm32mp1_syscfg_boot_mode_disable(void){}
+static inline void stm32mp_syscfg_boot_mode_enable(void){}
+static inline void stm32mp_syscfg_boot_mode_disable(void){}
#endif
void stm32mp1_deconfigure_uart_pins(void);
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index ff2218f..97e1ac6 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,7 @@
#include <drivers/arm/gic_common.h>
#include <drivers/arm/gicv2.h>
#include <drivers/clk.h>
+#include <drivers/st/stm32mp_reset.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
@@ -149,13 +150,7 @@
static void __dead2 stm32_system_reset(void)
{
- mmio_setbits_32(stm32mp_rcc_base() + RCC_MP_GRSTCSETR,
- RCC_MP_GRSTCSETR_MPSYSRST);
-
- /* Loop in case system reset is not immediately caught */
- for ( ; ; ) {
- ;
- }
+ stm32mp_system_reset();
}
static int stm32_validate_power_state(unsigned int power_state,
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 189f83d..32de391 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -280,7 +280,7 @@
uint32_t stm32mp_get_chip_version(void)
{
#if STM32MP13
- return stm32mp1_syscfg_get_chip_version();
+ return stm32mp_syscfg_get_chip_version();
#endif
#if STM32MP15
uint32_t version = 0U;
@@ -297,7 +297,7 @@
uint32_t stm32mp_get_chip_dev_id(void)
{
#if STM32MP13
- return stm32mp1_syscfg_get_chip_dev_id();
+ return stm32mp_syscfg_get_chip_dev_id();
#endif
#if STM32MP15
uint32_t dev_id;
diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c
index 75dd709..199bdc9 100644
--- a/plat/st/stm32mp1/stm32mp1_syscfg.c
+++ b/plat/st/stm32mp1/stm32mp1_syscfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -261,7 +261,7 @@
#endif
}
-static void stm32mp1_syscfg_set_hslv(void)
+static void stm32mp_syscfg_set_hslv(void)
{
uint32_t otp_value;
uint32_t vdd_voltage;
@@ -310,7 +310,7 @@
}
}
-void stm32mp1_syscfg_init(void)
+void stm32mp_syscfg_init(void)
{
#if STM32MP15
uint32_t bootr;
@@ -328,12 +328,12 @@
bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
#endif
- stm32mp1_syscfg_set_hslv();
+ stm32mp_syscfg_set_hslv();
- stm32mp1_syscfg_enable_io_compensation_start();
+ stm32mp_syscfg_enable_io_compensation_start();
}
-void stm32mp1_syscfg_enable_io_compensation_start(void)
+void stm32mp_syscfg_enable_io_compensation_start(void)
{
/*
* Activate automatic I/O compensation.
@@ -353,7 +353,7 @@
#endif
}
-void stm32mp1_syscfg_enable_io_compensation_finish(void)
+void stm32mp_syscfg_enable_io_compensation_finish(void)
{
enable_io_comp_cell_finish(SYSCFG_CMPCR);
#if STM32MP13
@@ -362,7 +362,7 @@
#endif
}
-void stm32mp1_syscfg_disable_io_compensation(void)
+void stm32mp_syscfg_disable_io_compensation(void)
{
clk_enable(SYSCFG);
@@ -385,7 +385,7 @@
* @brief Get silicon revision from SYSCFG registers.
* @retval chip version (REV_ID).
*/
-uint32_t stm32mp1_syscfg_get_chip_version(void)
+uint32_t stm32mp_syscfg_get_chip_version(void)
{
return (mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) &
SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT;
@@ -395,18 +395,18 @@
* @brief Get device ID from SYSCFG registers.
* @retval device ID (DEV_ID).
*/
-uint32_t stm32mp1_syscfg_get_chip_dev_id(void)
+uint32_t stm32mp_syscfg_get_chip_dev_id(void)
{
return mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) & SYSCFG_IDC_DEV_ID_MASK;
}
#if STM32MP13
-void stm32mp1_syscfg_boot_mode_enable(void)
+void stm32mp_syscfg_boot_mode_enable(void)
{
mmio_setbits_32(SYSCFG_BASE + SYSCFG_BOOTCR, SYSCFG_BOOTCR_BMEN);
}
-void stm32mp1_syscfg_boot_mode_disable(void)
+void stm32mp_syscfg_boot_mode_disable(void)
{
mmio_clrbits_32(SYSCFG_BASE + SYSCFG_BOOTCR, SYSCFG_BOOTCR_BMEN);
}
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 11b1138..d9a4d79 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -51,7 +51,11 @@
PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
-PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c
+PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \
+ drivers/st/reset/stm32mp2_reset.c
+
+PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \
+ drivers/st/clk/clk-stm32mp2.c
BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index e3662ad..d65fcea 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -293,6 +293,11 @@
#define SYSCFG_BASE U(0x44230000)
/*******************************************************************************
+ * STM32MP CA35SSC
+ ******************************************************************************/
+#define A35SSC_BASE U(0x48800000)
+
+/*******************************************************************************
* REGULATORS
******************************************************************************/
/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index dba1734..b0bd8a1 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,7 +12,7 @@
#include <drivers/generic_delay_timer.h>
#include <lib/mmio.h>
#include <lib/smccc.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <services/arm_arch_svc.h>
@@ -28,9 +28,9 @@
* configure_mmu_elx() will give the available subset of that,
*/
const mmap_region_t plat_zynqmp_mmap[] = {
- { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
- { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
- { CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
+ MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
{0}
};
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 0a34f72..50d4240 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <common/fdt_fixup.h>
#include <common/fdt_wrappers.h>
#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <libfdt.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
@@ -220,5 +221,5 @@
custom_mmap_add();
setup_page_tables(bl_regions, plat_get_mmap());
- enable_mmu_el3(0);
+ enable_mmu(0);
}
diff --git a/plat/xilinx/zynqmp/include/plat_private.h b/plat/xilinx/zynqmp/include/plat_private.h
index afa102d..1b41b7c 100644
--- a/plat/xilinx/zynqmp/include/plat_private.h
+++ b/plat/xilinx/zynqmp/include/plat_private.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,7 +13,7 @@
#include <bl31/interrupt_mgmt.h>
#include <common/bl_common.h>
#include <drivers/cadence/cdns_uart.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
void zynqmp_config_setup(void);
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 3a752b2..c340009 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -35,10 +35,6 @@
WORKAROUND_CVE_2017_5715 := 0
-ARM_XLAT_TABLES_LIB_V1 := 1
-$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
-$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
-
ifdef ZYNQMP_ATF_MEM_BASE
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
@@ -96,10 +92,9 @@
include lib/libfdt/libfdt.mk
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
+include lib/xlat_tables_v2/xlat_tables.mk
-PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
- lib/xlat_tables/aarch64/xlat_tables.c \
- drivers/arm/dcc/dcc_console.c \
+PLAT_BL_COMMON_SOURCES := drivers/arm/dcc/dcc_console.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
${GICV2_SOURCES} \
@@ -112,7 +107,8 @@
plat/xilinx/zynqmp/zynqmp_ipi.c \
plat/common/aarch64/crash_console_helpers.S \
plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
- plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+ plat/xilinx/zynqmp/aarch64/zynqmp_common.c \
+ ${XLAT_TABLES_LIB_SRCS}
ZYNQMP_CONSOLE ?= cadence
ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc))
diff --git a/poetry.lock b/poetry.lock
index 08b2b37..6bfbd50 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -1,4 +1,4 @@
-# This file is automatically @generated by Poetry 1.6.1 and should not be changed by hand.
+# This file is automatically @generated by Poetry 1.8.3 and should not be changed by hand.
[[package]]
name = "alabaster"
@@ -68,13 +68,13 @@
[[package]]
name = "certifi"
-version = "2023.7.22"
+version = "2024.7.4"
description = "Python package for providing Mozilla's CA Bundle."
optional = false
python-versions = ">=3.6"
files = [
- {file = "certifi-2023.7.22-py3-none-any.whl", hash = "sha256:92d6037539857d8206b8f6ae472e8b77db8058fec5937a1ef3f54304089edbb9"},
- {file = "certifi-2023.7.22.tar.gz", hash = "sha256:539cc1d13202e33ca466e88b2807e29f4c13049d6d87031a3c110744495cb082"},
+ {file = "certifi-2024.7.4-py3-none-any.whl", hash = "sha256:c198e21b1289c2ab85ee4e67bb4b4ef3ead0892059901a8d5b622f24a1101e90"},
+ {file = "certifi-2024.7.4.tar.gz", hash = "sha256:5a1e7645bc0ec61a09e26c36f6106dd4cf40c6db3a1fb6352b0244e7fb057c7b"},
]
[[package]]
@@ -199,13 +199,13 @@
[[package]]
name = "idna"
-version = "3.4"
+version = "3.7"
description = "Internationalized Domain Names in Applications (IDNA)"
optional = false
python-versions = ">=3.5"
files = [
- {file = "idna-3.4-py3-none-any.whl", hash = "sha256:90b77e79eaa3eba6de819a0c442c0b4ceefc341a7a2ab77d7562bf49f425c5c2"},
- {file = "idna-3.4.tar.gz", hash = "sha256:814f528e8dead7d329833b91c5faa87d60bf71824cd12a7530b5526063d02cb4"},
+ {file = "idna-3.7-py3-none-any.whl", hash = "sha256:82fee1fc78add43492d3a1898bfa6d8a904cc97d8427f683ed8e798d07761aa0"},
+ {file = "idna-3.7.tar.gz", hash = "sha256:028ff3aadf0609c1fd278d8ea3089299412a7a8b9bd005dd08b9f8285bcb5cfc"},
]
[[package]]
@@ -240,13 +240,13 @@
[[package]]
name = "jinja2"
-version = "3.1.2"
+version = "3.1.4"
description = "A very fast and expressive template engine."
optional = false
python-versions = ">=3.7"
files = [
- {file = "Jinja2-3.1.2-py3-none-any.whl", hash = "sha256:6088930bfe239f0e6710546ab9c19c9ef35e29792895fed6e6e31a023a182a61"},
- {file = "Jinja2-3.1.2.tar.gz", hash = "sha256:31351a702a408a9e7595a8fc6150fc3f43bb6bf7e319770cbc0db9df9437e852"},
+ {file = "jinja2-3.1.4-py3-none-any.whl", hash = "sha256:bc5dd2abb727a5319567b7a813e6a2e7318c39f4f487cfe6c89c6f9c7d25197d"},
+ {file = "jinja2-3.1.4.tar.gz", hash = "sha256:4a3aee7acbbe7303aede8e9648d13b8bf88a429282aa6122a993f0ac800cb369"},
]
[package.dependencies]
@@ -407,13 +407,13 @@
[[package]]
name = "pip"
-version = "23.1.2"
+version = "23.3"
description = "The PyPA recommended tool for installing Python packages."
optional = false
python-versions = ">=3.7"
files = [
- {file = "pip-23.1.2-py3-none-any.whl", hash = "sha256:3ef6ac33239e4027d9a5598a381b9d30880a1477e50039db2eac6e8a8f6d1b18"},
- {file = "pip-23.1.2.tar.gz", hash = "sha256:0e7c86f486935893c708287b30bd050a36ac827ec7fe5e43fe7cb198dd835fba"},
+ {file = "pip-23.3-py3-none-any.whl", hash = "sha256:bc38bb52bc286514f8f7cb3a1ba5ed100b76aaef29b521d48574329331c5ae7b"},
+ {file = "pip-23.3.tar.gz", hash = "sha256:bb7d4f69f488432e4e96394612f43ab43dd478d073ef7422604a570f7157561e"},
]
[[package]]
@@ -556,13 +556,13 @@
[[package]]
name = "requests"
-version = "2.31.0"
+version = "2.32.2"
description = "Python HTTP for Humans."
optional = false
-python-versions = ">=3.7"
+python-versions = ">=3.8"
files = [
- {file = "requests-2.31.0-py3-none-any.whl", hash = "sha256:58cd2187c01e70e6e26505bca751777aa9f2ee0b7f4300988b709f44e013003f"},
- {file = "requests-2.31.0.tar.gz", hash = "sha256:942c5a758f98d790eaed1a29cb6eefc7ffb0d1cf7af05c3d2791656dbd6ad1e1"},
+ {file = "requests-2.32.2-py3-none-any.whl", hash = "sha256:fc06670dd0ed212426dfeb94fc1b983d917c4f9847c863f313c9dfaaffb7c23c"},
+ {file = "requests-2.32.2.tar.gz", hash = "sha256:dd951ff5ecf3e3b3aa26b40703ba77495dab41da839ae72ef3c8e5d8e2433289"},
]
[package.dependencies]
@@ -577,19 +577,18 @@
[[package]]
name = "setuptools"
-version = "67.7.2"
+version = "70.0.0"
description = "Easily download, build, install, upgrade, and uninstall Python packages"
optional = false
-python-versions = ">=3.7"
+python-versions = ">=3.8"
files = [
- {file = "setuptools-67.7.2-py3-none-any.whl", hash = "sha256:23aaf86b85ca52ceb801d32703f12d77517b2556af839621c641fca11287952b"},
- {file = "setuptools-67.7.2.tar.gz", hash = "sha256:f104fa03692a2602fa0fec6c6a9e63b6c8a968de13e17c026957dd1f53d80990"},
+ {file = "setuptools-70.0.0-py3-none-any.whl", hash = "sha256:54faa7f2e8d2d11bcd2c07bed282eef1046b5c080d1c32add737d7b5817b1ad4"},
+ {file = "setuptools-70.0.0.tar.gz", hash = "sha256:f211a66637b8fa059bb28183da127d4e86396c991a942b028c6650d4319c3fd0"},
]
[package.extras]
-docs = ["furo", "jaraco.packaging (>=9)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-hoverxref (<2)", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (==0.8.3)", "sphinx-reredirects", "sphinxcontrib-towncrier"]
-testing = ["build[virtualenv]", "filelock (>=3.4.0)", "flake8 (<5)", "flake8-2020", "ini2toml[lite] (>=0.9)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "pip (>=19.1)", "pip-run (>=8.8)", "pytest (>=6)", "pytest-black (>=0.3.7)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=1.3)", "pytest-flake8", "pytest-mypy (>=0.9.1)", "pytest-perf", "pytest-timeout", "pytest-xdist", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel"]
-testing-integration = ["build[virtualenv]", "filelock (>=3.4.0)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "pytest", "pytest-enabler", "pytest-xdist", "tomli", "virtualenv (>=13.0.0)", "wheel"]
+docs = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier"]
+testing = ["build[virtualenv] (>=1.0.3)", "filelock (>=3.4.0)", "importlib-metadata", "ini2toml[lite] (>=0.14)", "jaraco.develop (>=7.21)", "jaraco.envs (>=2.2)", "jaraco.path (>=3.2.0)", "mypy (==1.9)", "packaging (>=23.2)", "pip (>=19.1)", "pyproject-hooks (!=1.1)", "pytest (>=6,!=8.1.1)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=2.2)", "pytest-home (>=0.5)", "pytest-mypy", "pytest-perf", "pytest-ruff (>=0.2.1)", "pytest-subprocess", "pytest-timeout", "pytest-xdist (>=3)", "tomli", "tomli-w (>=1.0.0)", "virtualenv (>=13.0.0)", "wheel"]
[[package]]
name = "six"
@@ -827,18 +826,18 @@
[[package]]
name = "urllib3"
-version = "2.0.2"
+version = "2.2.2"
description = "HTTP library with thread-safe connection pooling, file post, and more."
optional = false
-python-versions = ">=3.7"
+python-versions = ">=3.8"
files = [
- {file = "urllib3-2.0.2-py3-none-any.whl", hash = "sha256:d055c2f9d38dc53c808f6fdc8eab7360b6fdbbde02340ed25cfbcd817c62469e"},
- {file = "urllib3-2.0.2.tar.gz", hash = "sha256:61717a1095d7e155cdb737ac7bb2f4324a858a1e2e6466f6d03ff630ca68d3cc"},
+ {file = "urllib3-2.2.2-py3-none-any.whl", hash = "sha256:a448b2f64d686155468037e1ace9f2d2199776e17f0a46610480d311f73e3472"},
+ {file = "urllib3-2.2.2.tar.gz", hash = "sha256:dd505485549a7a552833da5e6063639d0d177c04f23bc3864e41e5dc5f612168"},
]
[package.extras]
brotli = ["brotli (>=1.0.9)", "brotlicffi (>=0.8.0)"]
-secure = ["certifi", "cryptography (>=1.9)", "idna (>=2.0.0)", "pyopenssl (>=17.1.0)", "urllib3-secure-extra"]
+h2 = ["h2 (>=4,<5)"]
socks = ["pysocks (>=1.5.6,!=1.5.7,<2.0)"]
zstd = ["zstandard (>=0.18.0)"]
@@ -869,18 +868,18 @@
[[package]]
name = "zipp"
-version = "3.15.0"
+version = "3.19.1"
description = "Backport of pathlib-compatible object wrapper for zip files"
optional = false
-python-versions = ">=3.7"
+python-versions = ">=3.8"
files = [
- {file = "zipp-3.15.0-py3-none-any.whl", hash = "sha256:48904fc76a60e542af151aded95726c1a5c34ed43ab4134b597665c86d7ad556"},
- {file = "zipp-3.15.0.tar.gz", hash = "sha256:112929ad649da941c23de50f356a2b5570c954b65150642bccdd66bf194d224b"},
+ {file = "zipp-3.19.1-py3-none-any.whl", hash = "sha256:2828e64edb5386ea6a52e7ba7cdb17bb30a73a858f5eb6eb93d8d36f5ea26091"},
+ {file = "zipp-3.19.1.tar.gz", hash = "sha256:35427f6d5594f4acf82d25541438348c26736fa9b3afa2754bcd63cdb99d8e8f"},
]
[package.extras]
-docs = ["furo", "jaraco.packaging (>=9)", "jaraco.tidelift (>=1.4)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-lint"]
-testing = ["big-O", "flake8 (<5)", "jaraco.functools", "jaraco.itertools", "more-itertools", "pytest (>=6)", "pytest-black (>=0.3.7)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=1.3)", "pytest-flake8", "pytest-mypy (>=0.9.1)"]
+doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-lint"]
+test = ["big-O", "jaraco.functools", "jaraco.itertools", "jaraco.test", "more-itertools", "pytest (>=6,!=8.1.*)", "pytest-checkdocs (>=2.4)", "pytest-cov", "pytest-enabler (>=2.2)", "pytest-ignore-flaky", "pytest-mypy", "pytest-ruff (>=0.2.1)"]
[metadata]
lock-version = "2.0"
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 0715b13..e3d7fbd 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -52,26 +52,11 @@
static entry_point_info_t *spmc_ep_info;
/*******************************************************************************
- * SPM Core context on CPU based on mpidr.
- ******************************************************************************/
-spmd_spm_core_context_t *spmd_get_context_by_mpidr(uint64_t mpidr)
-{
- int core_idx = plat_core_pos_by_mpidr(mpidr);
-
- if (core_idx < 0) {
- ERROR("Invalid mpidr: %" PRIx64 ", returned ID: %d\n", mpidr, core_idx);
- panic();
- }
-
- return &spm_core_context[core_idx];
-}
-
-/*******************************************************************************
* SPM Core context on current CPU get helper.
******************************************************************************/
spmd_spm_core_context_t *spmd_get_context(void)
{
- return spmd_get_context_by_mpidr(read_mpidr());
+ return &spm_core_context[plat_my_core_pos()];
}
/*******************************************************************************
@@ -217,7 +202,6 @@
{
spmd_spm_core_context_t *ctx = spmd_get_context();
gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx);
- unsigned int linear_id = plat_my_core_pos();
int64_t rc;
/* Sanity check the security state when the exception was generated */
@@ -248,7 +232,7 @@
rc = spmd_spm_core_sync_entry(ctx);
if (rc != 0ULL) {
- ERROR("%s failed (%" PRId64 ") on CPU%u\n", __func__, rc, linear_id);
+ ERROR("%s failed (%" PRId64 ") on CPU%u\n", __func__, rc, plat_my_core_pos());
}
ctx->secure_interrupt_ongoing = false;
@@ -677,6 +661,7 @@
{
unsigned int secure_state_in = (secure_origin) ? SECURE : NON_SECURE;
unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE;
+ void *ctx_out;
#if SPMD_SPM_AT_SEL2
if ((secure_state_out == SECURE) && (is_sve_hint_set(flags) == true)) {
@@ -703,6 +688,7 @@
#endif
cm_set_next_eret_context(secure_state_out);
+ ctx_out = cm_get_context(secure_state_out);
#if SPMD_SPM_AT_SEL2
/*
* If SPMC is at SEL2, save additional registers x8-x17, which may
@@ -715,7 +701,7 @@
* preserved, so the SPMD passes through these registers and expects the
* SPMC to save and restore (potentially also modify) them.
*/
- SMC_RET18(cm_get_context(secure_state_out), smc_fid, x1, x2, x3, x4,
+ SMC_RET18(ctx_out, smc_fid, x1, x2, x3, x4,
SMC_GET_GP(handle, CTX_GPREG_X5),
SMC_GET_GP(handle, CTX_GPREG_X6),
SMC_GET_GP(handle, CTX_GPREG_X7),
@@ -732,7 +718,7 @@
);
#else
- SMC_RET8(cm_get_context(secure_state_out), smc_fid, x1, x2, x3, x4,
+ SMC_RET8(ctx_out, smc_fid, x1, x2, x3, x4,
SMC_GET_GP(handle, CTX_GPREG_X5),
SMC_GET_GP(handle, CTX_GPREG_X6),
SMC_GET_GP(handle, CTX_GPREG_X7));
@@ -852,7 +838,6 @@
void *handle,
uint64_t flags)
{
- unsigned int linear_id = plat_my_core_pos();
spmd_spm_core_context_t *ctx = spmd_get_context();
bool secure_origin;
int ret;
@@ -863,7 +848,7 @@
VERBOSE("SPM(%u): 0x%x 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64
" 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 "\n",
- linear_id, smc_fid, x1, x2, x3, x4,
+ plat_my_core_pos(), smc_fid, x1, x2, x3, x4,
SMC_GET_GP(handle, CTX_GPREG_X5),
SMC_GET_GP(handle, CTX_GPREG_X6),
SMC_GET_GP(handle, CTX_GPREG_X7));
diff --git a/tools/renesas/rcar_layout_create/makefile b/tools/renesas/rcar_layout_create/makefile
index 8c2c054..115ca5c 100644
--- a/tools/renesas/rcar_layout_create/makefile
+++ b/tools/renesas/rcar_layout_create/makefile
@@ -1,4 +1,5 @@
#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -85,27 +86,31 @@
# command
.PHONY: all
-all: $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA6)
+
+all: $(FILE_NAME_SA0).srec $(FILE_NAME_SA0).bin
+all: $(FILE_NAME_SA6).srec $(FILE_NAME_SA6).bin
+
###################################################
# Linker
###################################################
-$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
- $(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib \
- -T $(MEMORY_DEF_SA0) \
- -o $(OUTPUT_FILE_SA0) \
- -Wl,-Map $(FILE_NAME_SA0).map \
- $(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
- $(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
+$(FILE_NAME_SA0).srec: $(OUTPUT_FILE_SA0)
+ $(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
-$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
- $(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib \
- -T $(MEMORY_DEF_SA6) \
- -o $(OUTPUT_FILE_SA6) \
- -Wl,-Map $(FILE_NAME_SA6).map \
+$(FILE_NAME_SA0).bin: $(OUTPUT_FILE_SA0)
+ $(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
- $(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
- $(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
+$(OUTPUT_FILE_SA0): $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
+ $(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib -T $(MEMORY_DEF_SA0) -o $(OUTPUT_FILE_SA0) -Wl,-Map $(FILE_NAME_SA0).map
+
+$(FILE_NAME_SA6).srec: $(OUTPUT_FILE_SA6)
+ $(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
+
+$(FILE_NAME_SA6).bin: $(OUTPUT_FILE_SA6)
+ $(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
+
+$(OUTPUT_FILE_SA6): $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
+ $(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib -T $(MEMORY_DEF_SA6) -o $(OUTPUT_FILE_SA6) -Wl,-Map $(FILE_NAME_SA6).map
###################################################
# Compile
diff --git a/tools/renesas/rzg_layout_create/makefile b/tools/renesas/rzg_layout_create/makefile
index d2a54ea..1e8f7ff 100644
--- a/tools/renesas/rzg_layout_create/makefile
+++ b/tools/renesas/rzg_layout_create/makefile
@@ -1,4 +1,5 @@
#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -82,27 +83,31 @@
# command
.PHONY: all
-all: $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA6)
+
+all: $(FILE_NAME_SA0).srec $(FILE_NAME_SA0).bin
+all: $(FILE_NAME_SA6).srec $(FILE_NAME_SA6).bin
+
###################################################
# Linker
###################################################
-$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
- $(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib \
- -T $(MEMORY_DEF_SA0) \
- -o $(OUTPUT_FILE_SA0) \
- -Wl,-Map $(FILE_NAME_SA0).map \
- $(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
- $(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
+$(FILE_NAME_SA0).srec: $(OUTPUT_FILE_SA0)
+ $(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
-$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
- $(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib \
- -T $(MEMORY_DEF_SA6) \
- -o $(OUTPUT_FILE_SA6) \
- -Wl,-Map $(FILE_NAME_SA6).map \
+$(FILE_NAME_SA0).bin: $(OUTPUT_FILE_SA0)
+ $(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
- $(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
- $(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
+$(OUTPUT_FILE_SA0): $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
+ $(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib -T $(MEMORY_DEF_SA0) -o $(OUTPUT_FILE_SA0) -Wl,-Map $(FILE_NAME_SA0).map
+
+$(FILE_NAME_SA6).srec: $(OUTPUT_FILE_SA6)
+ $(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
+
+$(FILE_NAME_SA6).bin: $(OUTPUT_FILE_SA6)
+ $(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
+
+$(OUTPUT_FILE_SA6): $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
+ $(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib -T $(MEMORY_DEF_SA6) -o $(OUTPUT_FILE_SA6) -Wl,-Map $(FILE_NAME_SA6).map
###################################################
# Compile