lib/cpu: Workaround for Cortex A77 erratum 1946167
Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions
<= r1p1. This erratum is avoided by inserting a DMB ST before acquire
atomic instructions without release semantics through a series of
writes to implementation defined system registers.
SDEN can be found here:
https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token=
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 7c142d1..58b0572 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -260,6 +260,9 @@
- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
+ CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
For Cortex-A78, the following errata build flags are defined :
- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
@@ -385,7 +388,7 @@
--------------
-*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.*
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639