Add exception vector guards

This patch adds guards so that an exception vector exceeding 32
instructions will generate a compile-time error. This keeps the
exception handlers in check from spilling over.

Change-Id: I7aa56dd0071a333664e2814c656d3896032046fe
diff --git a/bl1/aarch64/early_exceptions.S b/bl1/aarch64/early_exceptions.S
index 84bdae1..d06e854 100644
--- a/bl1/aarch64/early_exceptions.S
+++ b/bl1/aarch64/early_exceptions.S
@@ -33,6 +33,7 @@
 #include <bl1.h>
 #include <platform.h>
 #include <runtime_svc.h>
+#include <asm_macros.S>
 
 	.globl	early_exceptions
 	.weak	display_boot_progress
@@ -55,24 +56,28 @@
 	mov	x0, #SYNC_EXCEPTION_SP_EL0
 	bl	plat_report_exception
 	b	SynchronousExceptionSP0
+	check_vector_size SynchronousExceptionSP0
 
 	.align	7
 IrqSP0:
 	mov	x0, #IRQ_SP_EL0
 	bl	plat_report_exception
 	b	IrqSP0
+	check_vector_size IrqSP0
 
 	.align	7
 FiqSP0:
 	mov	x0, #FIQ_SP_EL0
 	bl	plat_report_exception
 	b	FiqSP0
+	check_vector_size FiqSP0
 
 	.align	7
 SErrorSP0:
 	mov	x0, #SERROR_SP_EL0
 	bl	plat_report_exception
 	b	SErrorSP0
+	check_vector_size SErrorSP0
 
 	/* -----------------------------------------------------
 	 * Current EL with SPx: 0x200 - 0x380
@@ -83,24 +88,28 @@
 	mov	x0, #SYNC_EXCEPTION_SP_ELX
 	bl	plat_report_exception
 	b	SynchronousExceptionSPx
+	check_vector_size SynchronousExceptionSPx
 
 	.align	7
 IrqSPx:
 	mov	x0, #IRQ_SP_ELX
 	bl	plat_report_exception
 	b	IrqSPx
+	check_vector_size IrqSPx
 
 	.align	7
 FiqSPx:
 	mov	x0, #FIQ_SP_ELX
 	bl	plat_report_exception
 	b	FiqSPx
+	check_vector_size FiqSPx
 
 	.align	7
 SErrorSPx:
 	mov	x0, #SERROR_SP_ELX
 	bl	plat_report_exception
 	b	SErrorSPx
+	check_vector_size SErrorSPx
 
 	/* -----------------------------------------------------
 	 * Lower EL using AArch64 : 0x400 - 0x580
@@ -115,24 +124,28 @@
 	 * ---------------------------------------------
 	 */
 	b	process_exception
+	check_vector_size SynchronousExceptionA64
 
 	.align	7
 IrqA64:
 	mov	x0, #IRQ_AARCH64
 	bl	plat_report_exception
 	b	IrqA64
+	check_vector_size IrqA64
 
 	.align	7
 FiqA64:
 	mov	x0, #FIQ_AARCH64
 	bl	plat_report_exception
 	b	FiqA64
+	check_vector_size FiqA64
 
 	.align	7
 SErrorA64:
 	mov	x0, #SERROR_AARCH64
 	bl	plat_report_exception
 	b   	SErrorA64
+	check_vector_size SErrorA64
 
 	/* -----------------------------------------------------
 	 * Lower EL using AArch32 : 0x0 - 0x180
@@ -143,24 +156,28 @@
 	mov	x0, #SYNC_EXCEPTION_AARCH32
 	bl	plat_report_exception
 	b	SynchronousExceptionA32
+	check_vector_size SynchronousExceptionA32
 
 	.align	7
 IrqA32:
 	mov	x0, #IRQ_AARCH32
 	bl	plat_report_exception
 	b	IrqA32
+	check_vector_size IrqA32
 
 	.align	7
 FiqA32:
 	mov	x0, #FIQ_AARCH32
 	bl	plat_report_exception
 	b	FiqA32
+	check_vector_size FiqA32
 
 	.align	7
 SErrorA32:
 	mov	x0, #SERROR_AARCH32
 	bl	plat_report_exception
 	b	SErrorA32
+	check_vector_size SErrorA32
 
 	.align	7