commit | 79626f460f115cc32b0dbeb48e72828d2dbf662a | [log] [tgz] |
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author | Jit Loon Lim <jit.loon.lim@intel.com> | Wed May 17 12:26:11 2023 +0800 |
committer | Jit Loon Lim <jit.loon.lim@intel.com> | Wed Jul 05 09:08:34 2023 +0800 |
tree | 1fbc1025514baa088cd5773791ae7bae762102c5 | |
parent | 9b8d813cc96173ce8ab7634dea17fb7f89b21626 [diff] |
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA This patch is used to implement 1. Cold/Warm reset and SMP support for Agilex5 SoC FPGA 2. Updated product name -> Agilex5 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I2c0645bcbf3a5907a4c79f35cffe674920b48f9d