)]}' { "commit": "ad6eb1951b986f30635025bbdf29e257b6b1e362", "tree": "3a81c724402e867ded4b457ec38fe566d3099646", "parents": [ "36d18c542e1a9c444fc50e955b793fcf1428465e" ], "author": { "name": "Shawn Guo", "email": "shawn.guo@linaro.org", "time": "Wed Oct 26 16:38:53 2022 +0800" }, "committer": { "name": "Shawn Guo", "email": "shawn.guo@linaro.org", "time": "Wed Oct 26 18:57:39 2022 +0800" }, "message": "fix(imx8m): update poweroff related SNVS_LPCR bits only\n\nFunction imx_system_off() writes SNVS_LPCR register to power off the SoC\nwithout bit masking. This clears other bits like LPWUI_EN and breaks\nthe function of SoC wake-up using RTC alarm. Fix it by updating poweroff\nrelated bits only.\n\nSigned-off-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nChange-Id: If641af4dc1103c67e1a645c03bb36a5f56665aef\n", "tree_diff": [ { "type": "modify", "old_id": "4df4f8edc7b1ce21dc0e17b5debadf789626d007", "old_mode": 33188, "old_path": "plat/imx/imx8m/imx8m_psci_common.c", "new_id": "d396902cd1dfa81ebd4c95fa93787f99d58a4fec", "new_mode": 33188, "new_path": "plat/imx/imx8m/imx8m_psci_common.c" } ] }