Enable asynchronous abort exceptions during boot
Asynchronous abort exceptions generated by the platform during cold boot are
not taken in EL3 unless SCR_EL3.EA is set.
Therefore EA bit is set along with RES1 bits in early BL1 and BL31 architecture
initialisation. Further write accesses to SCR_EL3 preserve these bits during
cold boot.
A build flag controls SCR_EL3.EA value to keep asynchronous abort exceptions
being trapped by EL3 after cold boot or not.
For further reference SError Interrupts are also known as asynchronous external
aborts.
On Cortex-A53 revisions below r0p2, asynchronous abort exceptions are taken in
EL3 whatever the SCR_EL3.EA value is.
Fixes arm-software/tf-issues#368
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
diff --git a/include/common/el3_common_macros.S b/include/common/el3_common_macros.S
index 0cd85c3..ba80d95 100644
--- a/include/common/el3_common_macros.S
+++ b/include/common/el3_common_macros.S
@@ -70,8 +70,15 @@
isb
/* ---------------------------------------------------------------------
- * Enable the SError interrupt now that the exception vectors have been
- * setup.
+ * Early set RES1 bits in SCR_EL3. Set EA bit as well to catch both
+ * External Aborts and SError Interrupts in EL3.
+ * ---------------------------------------------------------------------
+ */
+ mov x0, #(SCR_RES1_BITS | SCR_EA_BIT)
+ msr scr_el3, x0
+ /* ---------------------------------------------------------------------
+ * Enable External Aborts and SError Interrupts now that the exception
+ * vectors have been setup.
* ---------------------------------------------------------------------
*/
msr daifclr, #DAIF_ABT_BIT