)]}' { "commit": "aee2f33a675891f660fc0d06e739ce85f3472075", "tree": "45fd80bb3588e3ed6506872215cf50d3f4cd597e", "parents": [ "42c4760afad48714f807c65ddea9d0146a03f0c7" ], "author": { "name": "Andrew Davis", "email": "afd@ti.com", "time": "Tue Jan 10 13:14:37 2023 -0600" }, "committer": { "name": "Andrew Davis", "email": "afd@ti.com", "time": "Thu Jan 12 18:42:57 2023 -0600" }, "message": "feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles\n\nThe Cortex-A72 based cores on K3 platforms can be clocked fast\nenough that an extra latency cycle is needed to ensure correct\nL2 access. Set the latency here for all A72 cores.\n\nSigned-off-by: Andrew Davis \u003cafd@ti.com\u003e\nChange-Id: I639091dd0d2de09572bf0f73ac404e306e336883\n", "tree_diff": [ { "type": "modify", "old_id": "4b1af61ca3f243275b338f79b6afe24b584acca5", "old_mode": 33188, "old_path": "include/lib/cpus/aarch32/cortex_a72.h", "new_id": "c77484026f872710b6d244e08d37c8d91507258f", "new_mode": 33188, "new_path": "include/lib/cpus/aarch32/cortex_a72.h" }, { "type": "modify", "old_id": "17776458b825280786e192a4a39875e1274c2224", "old_mode": 33188, "old_path": "include/lib/cpus/aarch64/cortex_a72.h", "new_id": "a666617f96775c39308bfda3d02f3706b2da5087", "new_mode": 33188, "new_path": "include/lib/cpus/aarch64/cortex_a72.h" }, { "type": "modify", "old_id": "92433ab65844b37bceaee35c493c266a8db6df19", "old_mode": 33188, "old_path": "plat/ti/k3/board/j784s4/board.mk", "new_id": "c7fcb00160341bee33b4aba319856542448729a6", "new_mode": 33188, "new_path": "plat/ti/k3/board/j784s4/board.mk" }, { "type": "modify", "old_id": "f4f7d18eacdda9f57ee68ba7915f62b8f8a33975", "old_mode": 33188, "old_path": "plat/ti/k3/common/k3_helpers.S", "new_id": "cc9934c4e9343e31f2d8851e8063c896eacf3dd5", "new_mode": 33188, "new_path": "plat/ti/k3/common/k3_helpers.S" } ] }