Merge changes from topic "snprintf-fix" into integration
* changes:
fix(libc): snprintf: include stdint.h
fix(libc): limit snprintf radix value
fix(libc): fix snprintf corner cases
diff --git a/Makefile b/Makefile
index a238ee4..1baacf0 100644
--- a/Makefile
+++ b/Makefile
@@ -277,6 +277,10 @@
ENABLE_FEAT_ECV = 1
endif
+ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_DIT = 1
+endif
+
ifneq ($(findstring armclang,$(notdir $(CC))),)
TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi $(march64-directive)
@@ -1040,6 +1044,7 @@
USE_SP804_TIMER \
ENABLE_FEAT_RNG \
ENABLE_FEAT_SB \
+ ENABLE_FEAT_DIT \
PSA_FWU_SUPPORT \
ENABLE_TRBE_FOR_NS \
ENABLE_SYS_REG_TRACE_FOR_NS \
@@ -1154,6 +1159,7 @@
USE_SP804_TIMER \
ENABLE_FEAT_RNG \
ENABLE_FEAT_SB \
+ ENABLE_FEAT_DIT \
NR_OF_FW_BANKS \
NR_OF_IMAGES_IN_FW_BANK \
PSA_FWU_SUPPORT \
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 9dc9e6c..c54219f 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -224,7 +224,7 @@
* TODO: Revisit to store only SMCCC specified registers.
* -----------------------------------------------------
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* -----------------------------------------------------
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index f9c789f..fa6ede82 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,8 +92,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* Load and program APIAKey firmware key */
@@ -139,8 +140,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* Load and program APIAKey firmware key */
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 0d0a12d..bf5bd8d 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -71,8 +71,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
bl handle_lower_el_ea_esb
@@ -209,8 +210,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* Load and program APIAKey firmware key */
@@ -462,8 +464,9 @@
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
+ * Also set the PSTATE to a known state.
*/
- bl save_gp_pmcr_pauth_regs
+ bl prepare_el3_entry
#if ENABLE_PAUTH
/* Load and program APIAKey firmware key */
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 55e1532..522c1b4 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -370,6 +370,7 @@
uint64_t service_arg1;
uint64_t results[2];
uint32_t linear_id = plat_my_core_pos();
+ u_register_t dit;
/* Update this cpu's statistics */
tsp_stats[linear_id].smc_count++;
@@ -424,6 +425,23 @@
results[0] /= service_arg0 ? service_arg0 : 1;
results[1] /= service_arg1 ? service_arg1 : 1;
break;
+ case TSP_CHECK_DIT:
+ if (!is_armv8_4_dit_present()) {
+#if LOG_LEVEL >= LOG_LEVEL_ERROR
+ spin_lock(&console_lock);
+ ERROR("DIT not supported\n");
+ spin_unlock(&console_lock);
+#endif
+ results[0] = 0;
+ results[1] = 0xffff;
+ break;
+ }
+ dit = read_dit();
+ results[0] = dit == service_arg0;
+ results[1] = dit;
+ /* Toggle the dit bit */
+ write_dit(service_arg0 != 0U ? 0 : DIT_BIT);
+ break;
default:
break;
}
diff --git a/changelog.yaml b/changelog.yaml
index c4ed59b..9a4a8a7 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -113,6 +113,9 @@
- title: Self-hosted Trace Extensions (FEAT_TRF)
scope: trf
+ - title: Statistical profiling Extension (FEAT_SPE)
+ scope: spe
+
- title: Platforms
subsections:
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index d6f61d6..f80389d 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -1,8 +1,8 @@
Contributor's Guide
-===================
+*******************
Getting Started
----------------
+===============
- Make sure you have a Github account and you are logged on both
`developer.trustedfirmware.org`_ and `review.trustedfirmware.org`_.
@@ -24,7 +24,7 @@
branch.
Making Changes
---------------
+==============
- Ensure commits adhere to the the project's :ref:`Commit Style`.
@@ -91,7 +91,7 @@
block a patch, depending on how critical they are.
Submitting Changes
-------------------
+==================
- Submit your changes for review at https://review.trustedfirmware.org
targeting the ``integration`` branch.
@@ -164,13 +164,17 @@
revert your patches and ask you to resubmit a reworked version of them or
they may ask you to provide a fix-up patch.
-Add Build Configurations
-------------------------
+Add CI Configurations
+=====================
- TF-A uses Jenkins tool for Continuous Integration and testing activities.
Various CI Jobs are deployed which run tests on every patch before being
merged. So each of your patches go through a series of checks before they
- get merged on to the master branch.
+ get merged on to the master branch. Kindly ensure, that everytime you add
+ new files under your platform, they are covered under the following two sections:
+
+Coverity Scan
+-------------
- ``Coverity Scan analysis`` is one of the tests we perform on our source code
at regular intervals. We maintain a build script ``tf-cov-make`` which contains the
@@ -182,7 +186,7 @@
respective build configurations in the ``tf-cov-make`` build script.
- In this section you find the details on how to append your new build
- configurations for Coverity Scan analysis:
+ configurations for Coverity scan analysis illustrated with examples:
#. We maintain a separate repository named `tf-a-ci-scripts repository`_
for placing all the test scripts which will be executed by the CI Jobs.
@@ -223,8 +227,51 @@
of various other platforms listed in the ``tf-cov-make`` script. Kindly refer
them and append your build configurations respectively.
+Test Build Configuration (``tf-l1-build-plat``)
+-----------------------------------------------
+
+- Coverity Scan analysis, runs on a daily basis and will not be triggered for
+ every individual trusted-firmware patch.
+
+- Considering this, we have other distinguished CI jobs which run a set of test
+ configurations on every patch, before they are being passed to ``Coverity scan analysis``.
+
+- ``tf-l1-build-plat`` is the test group, which holds the test configurations
+ to build all the platforms. So be kind enough to verify that your newly added
+ files are built as part of one of the existing platform configurations present
+ in ``tf-l1-build-plat`` test group.
+
+- In this section you find the details on how to add the appropriate files,
+ needed to build your newly introduced platform as part of ``tf-l1-build-plat``
+ test group, illustrated with an example:
+
+- Lets consider ``Hikey`` platform:
+ In the `tf-a-ci-scripts repository`_ we need to add a build configuration file ``hikey-default``
+ under tf_config folder, ``tf_config/hikey-default`` listing all the build parameters
+ relevant to it.
+
+.. code:: shell
+
+ #Hikey Build Parameters
+ CROSS_COMPILE=aarch64-none-elf-
+ PLAT=hikey
+
+- Further a test-configuration file ``hikey-default:nil`` need to be added under the
+ test group, ``tf-l1-build-plat`` located at ``tf-a-ci-scripts/group/tf-l1-build-plat``,
+ to allow the platform to be built as part of this group.
+
+.. code:: shell
+
+ #
+ # Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+
+- As illustrated above, you need to add the similar files supporting your platform.
+
Binary Components
------------------
+=================
- Platforms may depend on binary components submitted to the `Trusted Firmware
binary repository`_ if they require code that the contributor is unable or
@@ -242,7 +289,7 @@
--------------
-*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
.. _developer.trustedfirmware.org: https://developer.trustedfirmware.org
.. _review.trustedfirmware.org: https://review.trustedfirmware.org
diff --git a/drivers/measured_boot/event_log/event_log.mk b/drivers/measured_boot/event_log/event_log.mk
index d3fbbb5..1ff4aa8 100644
--- a/drivers/measured_boot/event_log/event_log.mk
+++ b/drivers/measured_boot/event_log/event_log.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -30,10 +30,7 @@
EVENT_LOG_LEVEL \
)))
-MEASURED_BOOT_SRC_DIR := drivers/measured_boot/event_log/
+EVENT_LOG_SRC_DIR := drivers/measured_boot/event_log/
-MEASURED_BOOT_SOURCES := ${MEASURED_BOOT_SRC_DIR}event_log.c \
- ${MEASURED_BOOT_SRC_DIR}event_print.c
-
-BL2_SOURCES += ${MEASURED_BOOT_SOURCES}
-BL1_SOURCES += ${MEASURED_BOOT_SOURCES}
+EVENT_LOG_SOURCES := ${EVENT_LOG_SRC_DIR}event_log.c \
+ ${EVENT_LOG_SRC_DIR}event_print.c
diff --git a/drivers/mtd/nand/raw_nand.c b/drivers/mtd/nand/raw_nand.c
index 1fb5fac..021e30b 100644
--- a/drivers/mtd/nand/raw_nand.c
+++ b/drivers/mtd/nand/raw_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,13 +8,13 @@
#include <errno.h>
#include <stddef.h>
-#include <platform_def.h>
-
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <drivers/raw_nand.h>
#include <lib/utils.h>
+#include <platform_def.h>
+
#define ONFI_SIGNATURE_ADDR 0x20U
/* CRC calculation */
@@ -24,9 +24,6 @@
/* Status register */
#define NAND_STATUS_READY BIT(6)
-#define SZ_128M 0x08000000U
-#define SZ_512 0x200U
-
static struct rawnand_device rawnand_dev;
#pragma weak plat_get_raw_nand_data
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index af8b71e..f525741 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1837,11 +1837,6 @@
return -FDT_ERR_NOTFOUND;
}
- /* Check status field to disable security */
- if (!fdt_get_rcc_secure_status()) {
- mmio_write_32(rcc_base + RCC_TZCR, 0);
- }
-
ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB,
clksrc);
if (ret < 0) {
@@ -2358,6 +2353,12 @@
int stm32mp1_clk_probe(void)
{
+#if defined(IMAGE_BL32)
+ if (!fdt_get_rcc_secure_state()) {
+ mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U);
+ }
+#endif
+
stm32mp1_osc_init();
sync_earlyboot_clocks_state();
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c
index a013a82..80c2f41 100644
--- a/drivers/st/clk/stm32mp_clkfunc.c
+++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -250,24 +250,22 @@
}
/*
- * Get the secure status for rcc node in device tree.
- * @return: true if rcc is available from secure world, false if not.
+ * Get the secure state for rcc node in device tree.
+ * @return: true if rcc is configured for secure world access, false if not.
*/
-bool fdt_get_rcc_secure_status(void)
+bool fdt_get_rcc_secure_state(void)
{
- int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return false;
}
- node = fdt_get_rcc_node(fdt);
- if (node < 0) {
+ if (fdt_node_offset_by_compatible(fdt, -1, DT_RCC_SEC_CLK_COMPAT) < 0) {
return false;
}
- return !!(fdt_get_status(node) & DT_SECURE);
+ return true;
}
/*
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index edac46a..5c20932 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -726,7 +726,6 @@
(ufs_params.desc_base != 0) &&
(ufs_params.desc_size >= UFS_DESC_SIZE));
- memset((void *)buf, 0, size);
get_utrd(&utrd);
ufs_prepare_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size);
ufs_send_request(utrd.task_tag);
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 46cd1c9..a260f03 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -46,6 +46,12 @@
return (read_id_aa64isar1_el1() & mask) != 0U;
}
+static inline bool is_armv8_4_dit_present(void)
+{
+ return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) &
+ ID_AA64PFR0_DIT_MASK) == 1U;
+}
+
static inline bool is_armv8_4_ttst_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 733bb23..009eb90 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -529,6 +529,9 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
+/* Armv8.4 Data Independent Timing Register */
+DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
+
/* Armv8.5 MTE Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index f29def7..d47244e 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <arch.h>
#include <asm_macros.S>
+#include <assert_macros.S>
#include <context.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
@@ -237,15 +238,20 @@
/*
* If Data Independent Timing (DIT) functionality is implemented,
- * always enable DIT in EL3
+ * always enable DIT in EL3.
+ * First assert that the FEAT_DIT build flag matches the feature id
+ * register value for DIT.
*/
+#if ENABLE_FEAT_DIT
+#if ENABLE_ASSERTIONS
mrs x0, id_aa64pfr0_el1
ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
- bne 1f
+ ASM_ASSERT(eq)
+#endif /* ENABLE_ASSERTIONS */
mov x0, #DIT_BIT
msr DIT, x0
-1:
+#endif
.endm
/* -----------------------------------------------------------------------------
diff --git a/include/bl32/tsp/tsp.h b/include/bl32/tsp/tsp.h
index 637e14a..285bfbe 100644
--- a/include/bl32/tsp/tsp.h
+++ b/include/bl32/tsp/tsp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -41,6 +41,7 @@
#define TSP_MUL 0x2002
#define TSP_DIV 0x2003
#define TSP_HANDLE_SEL1_INTR_AND_RETURN 0x2004
+#define TSP_CHECK_DIT 0x2005
/*
* Identify a TSP service from function ID filtering the last 16 bits from the
diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h
index 9df38d6..61286b2 100644
--- a/include/drivers/st/stm32mp_clkfunc.h
+++ b/include/drivers/st/stm32mp_clkfunc.h
@@ -23,7 +23,7 @@
uint32_t *array);
int fdt_rcc_subnode_offset(const char *name);
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
-bool fdt_get_rcc_secure_status(void);
+bool fdt_get_rcc_secure_state(void);
int fdt_get_clock_id(int node);
unsigned long fdt_get_uart_clock_freq(uintptr_t instance);
diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
index 632f122..1d3ac15 100644
--- a/include/plat/common/common_def.h
+++ b/include/plat/common/common_def.h
@@ -1,17 +1,48 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef COMMON_DEF_H
#define COMMON_DEF_H
-#include <platform_def.h>
-
#include <common/bl_common.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <platform_def.h>
+
+#define SZ_32 U(0x00000020)
+#define SZ_64 U(0x00000040)
+#define SZ_128 U(0x00000080)
+#define SZ_256 U(0x00000100)
+#define SZ_512 U(0x00000200)
+
+#define SZ_1K U(0x00000400)
+#define SZ_2K U(0x00000800)
+#define SZ_4K U(0x00001000)
+#define SZ_8K U(0x00002000)
+#define SZ_16K U(0x00004000)
+#define SZ_32K U(0x00008000)
+#define SZ_64K U(0x00010000)
+#define SZ_128K U(0x00020000)
+#define SZ_256K U(0x00040000)
+#define SZ_512K U(0x00080000)
+
+#define SZ_1M U(0x00100000)
+#define SZ_2M U(0x00200000)
+#define SZ_4M U(0x00400000)
+#define SZ_8M U(0x00800000)
+#define SZ_16M U(0x01000000)
+#define SZ_32M U(0x02000000)
+#define SZ_64M U(0x04000000)
+#define SZ_128M U(0x08000000)
+#define SZ_256M U(0x10000000)
+#define SZ_512M U(0x20000000)
+
+#define SZ_1G U(0x40000000)
+#define SZ_2G U(0x80000000)
+
/******************************************************************************
* Required platform porting definitions that are expected to be common to
* all platforms
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index c9035e8..c1c0612 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,7 +21,7 @@
.global fpregs_context_save
.global fpregs_context_restore
#endif
- .global save_gp_pmcr_pauth_regs
+ .global prepare_el3_entry
.global restore_gp_pmcr_pauth_regs
.global save_and_update_ptw_el1_sys_regs
.global el3_exit
@@ -682,8 +682,24 @@
endfunc fpregs_context_restore
#endif /* CTX_INCLUDE_FPREGS */
+ /*
+ * Set the PSTATE bits not set when the exception was taken as
+ * described in the AArch64.TakeException() pseudocode function
+ * in ARM DDI 0487F.c page J1-7635 to a default value.
+ */
+ .macro set_unset_pstate_bits
+ /*
+ * If Data Independent Timing (DIT) functionality is implemented,
+ * always enable DIT in EL3
+ */
+#if ENABLE_FEAT_DIT
+ mov x8, #DIT_BIT
+ msr DIT, x8
+#endif /* ENABLE_FEAT_DIT */
+ .endm /* set_unset_pstate_bits */
+
/* ------------------------------------------------------------------
- * The following function is used to save and restore all the general
+ * The following macro is used to save and restore all the general
* purpose and ARMv8.3-PAuth (if enabled) registers.
* It also checks if Secure Cycle Counter is not disabled in MDCR_EL3
* when ARMv8.5-PMU is implemented, and if called from Non-secure
@@ -693,12 +709,10 @@
* when a world switch occurs but that type of implementation is more
* complex. So currently we will always save and restore these
* registers on entry and exit of EL3.
- * These are not macros to ensure their invocation fits within the 32
- * instructions per exception vector.
* clobbers: x18
* ------------------------------------------------------------------
*/
-func save_gp_pmcr_pauth_regs
+ .macro save_gp_pmcr_pauth_regs
stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
@@ -769,9 +783,28 @@
stp x26, x27, [x19, #CTX_PACDBKEY_LO]
stp x28, x29, [x19, #CTX_PACGAKEY_LO]
#endif /* CTX_INCLUDE_PAUTH_REGS */
+ .endm /* save_gp_pmcr_pauth_regs */
+/* -----------------------------------------------------------------
+ * This function saves the context and sets the PSTATE to a known
+ * state, preparing entry to el3.
+ * Save all the general purpose and ARMv8.3-PAuth (if enabled)
+ * registers.
+ * Then set any of the PSTATE bits that are not set by hardware
+ * according to the Aarch64.TakeException pseudocode in the Arm
+ * Architecture Reference Manual to a default value for EL3.
+ * clobbers: x17
+ * -----------------------------------------------------------------
+ */
+func prepare_el3_entry
+ save_gp_pmcr_pauth_regs
+ /*
+ * Set the PSTATE bits not described in the Aarch64.TakeException
+ * pseudocode to their default values.
+ */
+ set_unset_pstate_bits
ret
-endfunc save_gp_pmcr_pauth_regs
+endfunc prepare_el3_entry
/* ------------------------------------------------------------------
* This function restores ARMv8.3-PAuth (if enabled) and all general
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index f0d7342..d747efc 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,9 +54,14 @@
* MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
* and disabled in secure state. Accesses to SPE registers at
* S-EL1 generate trap exceptions to EL3.
+ *
+ * MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
+ * register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
+ * Setting this bit to 1 doesn't have any effect on it when
+ * FEAT_SPEv1p2 not implemented.
*/
v = read_mdcr_el3();
- v |= MDCR_NSPB(MDCR_NSPB_EL1);
+ v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
write_mdcr_el3(v);
}
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 551b689..b39dcf4 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2016-2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -145,6 +145,9 @@
# Flag to enable access to the CNTPOFF_EL2 register
ENABLE_FEAT_ECV := 0
+# Flag to enable use of the DIT feature.
+ENABLE_FEAT_DIT := 0
+
# By default BL31 encryption disabled
ENCRYPT_BL31 := 0
diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h
index 194814f..e4015f7 100644
--- a/plat/arm/board/rdn2/include/platform_def.h
+++ b/plat/arm/board/rdn2/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,8 @@
#if (CSS_SGI_PLATFORM_VARIANT == 1)
#define PLAT_ARM_CLUSTER_COUNT U(8)
+#elif (CSS_SGI_PLATFORM_VARIANT == 2)
+#define PLAT_ARM_CLUSTER_COUNT U(4)
#else
#define PLAT_ARM_CLUSTER_COUNT U(16)
#endif
@@ -34,6 +36,8 @@
#if (CSS_SGI_PLATFORM_VARIANT == 1)
#define TZC400_COUNT U(2)
+#elif (CSS_SGI_PLATFORM_VARIANT == 2)
+#define TZC400_COUNT U(4)
#else
#define TZC400_COUNT U(8)
#endif
@@ -64,8 +68,15 @@
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
#ifdef __aarch64__
+#if (CSS_SGI_PLATFORM_VARIANT == 2)
+#define PLAT_PHY_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+ CSS_SGI_CHIP_COUNT)
+#define PLAT_VIRT_ADDR_SPACE_SIZE CSS_SGI_REMOTE_CHIP_MEM_OFFSET( \
+ CSS_SGI_CHIP_COUNT)
+#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42)
+#endif
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
@@ -75,6 +86,9 @@
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
+/* Virtual address used by dynamic mem_protect for chunk_base */
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
+
#if (CSS_SGI_PLATFORM_VARIANT == 1)
#define PLAT_ARM_GICR_BASE UL(0x30100000)
#else
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index 5b24c32..753ba32 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -3,9 +3,27 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+RD_N2_VARIANTS := 0 1 2
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
+ $(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0, 1 or 2, currently set \
+ to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
+
+$(eval $(call CREATE_SEQ,SEQ,4))
+ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
+ $(error "Chip count for RD-N2-MC should be either $(SEQ) \
+ currently it is set to ${CSS_SGI_CHIP_COUNT}.")
+endif
+
# RD-N2 platform uses GIC-700 which is based on GICv4.1
GIC_ENABLE_V4_EXTN := 1
+#Enable GIC Multichip Extension only for Multichip Platforms
+ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
+GICV3_IMPL_GIC600_MULTICHIP := 1
+endif
+
include plat/arm/css/sgi/sgi-common.mk
RDN2_BASE = plat/arm/board/rdn2
@@ -39,6 +57,13 @@
BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
endif
+ifeq (${CSS_SGI_PLATFORM_VARIANT}, 2)
+BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
+
+# Enable dynamic addition of MMAP regions in BL31
+BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
+endif
+
# Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \
${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts
@@ -58,10 +83,3 @@
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_AMU := 1
-
-RD_N2_VARIANTS := 0 1
-ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
- $(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
- $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0 or 1, currently set \
- to ${CSS_SGI_PLATFORM_VARIANT}.")
-endif
diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c
index 5bf14e3..8cf1929 100644
--- a/plat/arm/board/rdn2/rdn2_plat.c
+++ b/plat/arm/board/rdn2/rdn2_plat.c
@@ -1,12 +1,87 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <common/debug.h>
+#include <drivers/arm/gic600_multichip.h>
+#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
+#include <sgi_soc_platform_def_v2.h>
#include <sgi_plat.h>
+#if defined(IMAGE_BL31)
+#if (CSS_SGI_PLATFORM_VARIANT == 2)
+static const mmap_region_t rdn2mc_dynamic_mmap[] = {
+#if CSS_SGI_CHIP_COUNT > 1
+ ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
+ CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+#endif
+#if CSS_SGI_CHIP_COUNT > 2
+ ARM_MAP_SHARED_RAM_REMOTE_CHIP(2),
+ CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
+#endif
+#if CSS_SGI_CHIP_COUNT > 3
+ ARM_MAP_SHARED_RAM_REMOTE_CHIP(3),
+ CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
+#endif
+};
+#endif
+
+#if (CSS_SGI_PLATFORM_VARIANT == 2)
+static struct gic600_multichip_data rdn2mc_multichip_data __init = {
+ .rt_owner_base = PLAT_ARM_GICD_BASE,
+ .rt_owner = 0,
+ .chip_count = CSS_SGI_CHIP_COUNT,
+ .chip_addrs = {
+ PLAT_ARM_GICD_BASE >> 16,
+#if CSS_SGI_CHIP_COUNT > 1
+ (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
+#endif
+#if CSS_SGI_CHIP_COUNT > 2
+ (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
+#endif
+#if CSS_SGI_CHIP_COUNT > 3
+ (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
+#endif
+ },
+ .spi_ids = {
+ {32, 479},
+ #if CSS_SGI_CHIP_COUNT > 1
+ {0, 0},
+ #endif
+ #if CSS_SGI_CHIP_COUNT > 2
+ {0, 0},
+ #endif
+ #if CSS_SGI_CHIP_COUNT > 3
+ {0, 0},
+ #endif
+ }
+};
+#endif
+
+#if (CSS_SGI_PLATFORM_VARIANT == 2)
+static uintptr_t rdn2mc_multichip_gicr_frames[] = {
+ /* Chip 0's GICR Base */
+ PLAT_ARM_GICR_BASE,
+#if CSS_SGI_CHIP_COUNT > 1
+ /* Chip 1's GICR BASE */
+ PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
+#endif
+#if CSS_SGI_CHIP_COUNT > 2
+ /* Chip 2's GICR BASE */
+ PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
+#endif
+#if CSS_SGI_CHIP_COUNT > 3
+ /* Chip 3's GICR BASE */
+ PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
+#endif
+ UL(0) /* Zero Termination */
+};
+#endif
+#endif /* IMAGE_BL31 */
+
unsigned int plat_arm_sgi_get_platform_id(void)
{
return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
@@ -25,7 +100,39 @@
SID_MULTI_CHIP_MODE_SHIFT;
}
+#if defined(IMAGE_BL31)
void bl31_platform_setup(void)
{
+#if (CSS_SGI_PLATFORM_VARIANT == 2)
+ int ret;
+ unsigned int i;
+
+ if (plat_arm_sgi_get_multi_chip_mode() == 0) {
+ ERROR("Chip Count is set to %u but multi-chip mode is not "
+ "enabled\n", CSS_SGI_CHIP_COUNT);
+ panic();
+ } else {
+ INFO("Enabling multi-chip support for RD-N2 variant\n");
+
+ for (i = 0; i < ARRAY_SIZE(rdn2mc_dynamic_mmap); i++) {
+ ret = mmap_add_dynamic_region(
+ rdn2mc_dynamic_mmap[i].base_pa,
+ rdn2mc_dynamic_mmap[i].base_va,
+ rdn2mc_dynamic_mmap[i].size,
+ rdn2mc_dynamic_mmap[i].attr);
+ if (ret != 0) {
+ ERROR("Failed to add dynamic mmap entry for"
+ " i: %d " "(ret=%d)\n", i, ret);
+ panic();
+ }
+ }
+
+ plat_arm_override_gicr_frames(
+ rdn2mc_multichip_gicr_frames);
+ gic600_multichip_init(&rdn2mc_multichip_data);
+ }
+#endif
+
sgi_bl31_common_platform_setup();
}
+#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/rdn2/rdn2_security.c b/plat/arm/board/rdn2/rdn2_security.c
index 9568b60..dff6a19 100644
--- a/plat/arm/board/rdn2/rdn2_security.c
+++ b/plat/arm/board/rdn2/rdn2_security.c
@@ -1,25 +1,63 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <common/debug.h>
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
-
static const arm_tzc_regions_info_t tzc_regions[] = {
ARM_TZC_REGIONS_DEF,
{}
};
+#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
+static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
+ {
+ /* TZC memory regions for second chip */
+ SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
+ {}
+ },
+#if CSS_SGI_CHIP_COUNT > 2
+ {
+ /* TZC memory regions for third chip */
+ SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
+ {}
+ },
+#endif
+#if CSS_SGI_CHIP_COUNT > 3
+ {
+ /* TZC memory regions for fourth chip */
+ SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
+ {}
+ },
+#endif
+};
+#endif /* CSS_SGI_PLATFORM_VARIANT && CSS_SGI_CHIP_COUNT */
+
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
+ unsigned int i;
- int i;
+ INFO("Configuring TrustZone Controller for Chip 0\n");
- for (i = 0; i < TZC400_COUNT; i++)
+ for (i = 0; i < TZC400_COUNT; i++) {
arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
+ }
+#if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)
+ unsigned int j;
+
+ for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
+ INFO("Configuring TrustZone Controller for Chip %u\n", i);
+
+ for (j = 0; j < TZC400_COUNT; j++) {
+ arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
+ + TZC400_BASE(j), tzc_regions_mc[i-1]);
+ }
+ }
+#endif
}
diff --git a/plat/arm/board/rdn2/rdn2_topology.c b/plat/arm/board/rdn2/rdn2_topology.c
index cad6c37..89300f8 100644
--- a/plat/arm/board/rdn2/rdn2_topology.c
+++ b/plat/arm/board/rdn2/rdn2_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,20 +11,24 @@
* The power domain tree descriptor.
******************************************************************************/
const unsigned char rd_n2_pd_tree_desc[] = {
- PLAT_ARM_CLUSTER_COUNT,
+ (PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT),
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#if (CSS_SGI_PLATFORM_VARIANT != 2 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1))
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
-#if (CSS_SGI_PLATFORM_VARIANT == 0)
+#endif
+#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 2))
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#endif
+#if (CSS_SGI_PLATFORM_VARIANT == 0 || (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 3))
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
@@ -44,6 +48,32 @@
* The array mapping platform core position (implemented by plat_my_core_pos())
* to the SCMI power domain ID implemented by SCP.
******************************************************************************/
+#if (CSS_SGI_PLATFORM_VARIANT == 2)
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+#if (CSS_SGI_CHIP_COUNT > 1)
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (CSS_SGI_CHIP_COUNT > 2)
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (CSS_SGI_CHIP_COUNT > 3)
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+};
+#else
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
@@ -64,3 +94,4 @@
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
#endif
};
+#endif
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 711ed03..c45e045 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -400,6 +400,9 @@
MEASURED_BOOT_MK := drivers/measured_boot/event_log/event_log.mk
$(info Including ${MEASURED_BOOT_MK})
include ${MEASURED_BOOT_MK}
+
+ BL1_SOURCES += ${EVENT_LOG_SOURCES}
+ BL2_SOURCES += ${EVENT_LOG_SOURCES}
endif
ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT}),)
diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
index bebc597..639b687 100644
--- a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
+++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
@@ -92,6 +92,12 @@
SOC_MEMCNTRL_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
+#define SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(n) \
+ MAP_REGION_FLAT( \
+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + SOC_MEMCNTRL_BASE, \
+ SOC_MEMCNTRL_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
/*
* The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
*/
diff --git a/plat/arm/css/sgi/sgi_plat_v2.c b/plat/arm/css/sgi/sgi_plat_v2.c
index 131cdf2..1a2a966 100644
--- a/plat/arm/css/sgi/sgi_plat_v2.c
+++ b/plat/arm/css/sgi/sgi_plat_v2.c
@@ -42,6 +42,15 @@
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
+#if CSS_SGI_CHIP_COUNT > 1
+ SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(1),
+#endif
+#if CSS_SGI_CHIP_COUNT > 2
+ SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(2),
+#endif
+#if CSS_SGI_CHIP_COUNT > 3
+ SOC_MEMCNTRL_MAP_DEVICE_REMOTE_CHIP(3),
+#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index a13e9e5..d8d1c13 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -62,6 +62,14 @@
/* Setup the UART console */
int stm32mp_uart_console_setup(void);
+#if STM32MP_EARLY_CONSOLE
+void stm32mp_setup_early_console(void);
+#else
+static inline void stm32mp_setup_early_console(void)
+{
+}
+#endif
+
/*
* Platform util functions for the GPIO driver
* @bank: Target GPIO bank ID as per DT bindings
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index 2297cd6..f99cad5 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -205,10 +205,27 @@
}
#endif
+static void set_console(uintptr_t base, uint32_t clk_rate)
+{
+ unsigned int console_flags;
+
+ if (console_stm32_register(base, clk_rate,
+ STM32MP_UART_BAUDRATE, &console) == 0) {
+ panic();
+ }
+
+ console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
+ CONSOLE_FLAG_TRANSLATE_CRLF;
+#if !defined(IMAGE_BL2) && defined(DEBUG)
+ console_flags |= CONSOLE_FLAG_RUNTIME;
+#endif
+
+ console_set_scope(&console, console_flags);
+}
+
int stm32mp_uart_console_setup(void)
{
struct dt_node_info dt_uart_info;
- unsigned int console_flags;
uint32_t clk_rate = 0U;
int result;
uint32_t boot_itf __unused;
@@ -249,21 +266,19 @@
clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock);
#endif
- if (console_stm32_register(dt_uart_info.base, clk_rate,
- STM32MP_UART_BAUDRATE, &console) == 0) {
- panic();
- }
-
- console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
- CONSOLE_FLAG_TRANSLATE_CRLF;
-#if !defined(IMAGE_BL2) && defined(DEBUG)
- console_flags |= CONSOLE_FLAG_RUNTIME;
-#endif
- console_set_scope(&console, console_flags);
+ set_console(dt_uart_info.base, clk_rate);
return 0;
}
+#if STM32MP_EARLY_CONSOLE
+void stm32mp_setup_early_console(void)
+{
+ plat_crash_console_init();
+ set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ);
+}
+#endif /* STM32MP_EARLY_CONSOLE */
+
/*****************************************************************************
* plat_is_smccc_feature_available() - This function checks whether SMCCC
* feature is availabile for platform.
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 1504360..33ad56f 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -139,6 +139,8 @@
u_register_t arg2 __unused,
u_register_t arg3 __unused)
{
+ stm32mp_setup_early_console();
+
stm32mp_save_boot_ctx_address(arg0);
}
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 65eaa74..8d4320a 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -9,6 +9,8 @@
BL2_AT_EL3 := 1
USE_COHERENT_MEM := 0
+STM32MP_EARLY_CONSOLE ?= 0
+
# Allow TF-A to concatenate BL2 & BL32 binaries in a single file,
# share DTB file between BL2 and BL32
# If it is set to 0, then FIP is used
@@ -157,6 +159,7 @@
PLAT_XLAT_TABLES_DYNAMIC \
STM32MP_DDR_32BIT_INTERFACE \
STM32MP_DDR_DUAL_AXI_PORT \
+ STM32MP_EARLY_CONSOLE \
STM32MP_EMMC \
STM32MP_EMMC_BOOT \
STM32MP_RAW_NAND \
@@ -183,6 +186,7 @@
STM32_TF_VERSION \
STM32MP_DDR_32BIT_INTERFACE \
STM32MP_DDR_DUAL_AXI_PORT \
+ STM32MP_EARLY_CONSOLE \
STM32MP_EMMC \
STM32MP_EMMC_BOOT \
STM32MP_RAW_NAND \
diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c
index 714ab80..27dbf4e 100644
--- a/plat/st/stm32mp1/stm32mp1_boot_device.c
+++ b/plat/st/stm32mp1/stm32mp1_boot_device.c
@@ -14,9 +14,6 @@
#include <lib/utils.h>
#include <plat/common/platform.h>
-#define SZ_512 0x200U
-#define SZ_64M 0x4000000U
-
#if STM32MP_RAW_NAND || STM32MP_SPI_NAND
static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc)
{
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 76f3585..aabe81f 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -429,7 +429,7 @@
#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
-static inline uint32_t tamp_bkpr(uint32_t idx)
+static inline uintptr_t tamp_bkpr(uint32_t idx)
{
return TAMP_BKP_REGISTER_BASE + (idx << 2);
}
@@ -492,5 +492,6 @@
#define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout"
#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
+#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
#endif /* STM32MP1_DEF_H */
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index ed4d5e5..3892151 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,6 @@
#include <assert.h>
#include <errno.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
#include <bl32/sp_min/platform_sp_min.h>
#include <common/debug.h>
@@ -20,6 +18,8 @@
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
+
static uintptr_t stm32_sec_entrypoint;
static uint32_t cntfrq_core0;
@@ -60,9 +60,9 @@
static int stm32_pwr_domain_on(u_register_t mpidr)
{
unsigned long current_cpu_mpidr = read_mpidr_el1();
- uint32_t bkpr_core1_addr =
+ uintptr_t bkpr_core1_addr =
tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
- uint32_t bkpr_core1_magic =
+ uintptr_t bkpr_core1_magic =
tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX);
if (mpidr == current_cpu_mpidr) {
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 9b39b9d..1125a69 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -568,7 +568,7 @@
void stm32_save_boot_interface(uint32_t interface, uint32_t instance)
{
- uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
+ uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
clk_enable(RTCAPB);
@@ -585,7 +585,7 @@
static uint32_t itf;
if (itf == 0U) {
- uint32_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
+ uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID);
clk_enable(RTCAPB);
diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c
index 29fc238..6cb4992 100644
--- a/services/spd/tspd/tspd_main.c
+++ b/services/spd/tspd/tspd_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -570,6 +570,11 @@
case TSP_YIELD_FID(TSP_SUB):
case TSP_YIELD_FID(TSP_MUL):
case TSP_YIELD_FID(TSP_DIV):
+ /*
+ * Request from non-secure client to perform a check
+ * of the DIT PSTATE bit.
+ */
+ case TSP_YIELD_FID(TSP_CHECK_DIT):
if (ns) {
/*
* This is a fresh request from the non-secure client.