diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 650181d..5479a49 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -109,7 +109,8 @@
 		int32_t rc = (*bl32_init)();
 
 		if (rc != 0) {
-			ERROR("BL31: BL32 initialization failed (rc = %d)", rc);
+			WARN("BL31: BL32 initialization failed (rc = %d)\n",
+			     rc);
 		}
 	}
 	/*
diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h
index 86c8512..9af8f8c 100644
--- a/include/plat/arm/board/common/board_arm_def.h
+++ b/include/plat/arm/board/common/board_arm_def.h
@@ -102,7 +102,7 @@
  * little space for growth.
  */
 #if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE		0x1C000
+# define PLAT_ARM_MAX_BL2_SIZE		0x1D000
 #else
 # define PLAT_ARM_MAX_BL2_SIZE		0x11000
 #endif
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index f2570a8..95fe2c5 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -21,6 +21,7 @@
 
 /* Variable to store the address of TB_FW_CONFIG file */
 static void *tb_fw_cfg_dtb;
+static size_t tb_fw_cfg_dtb_size;
 
 
 #if TRUSTED_BOARD_BOOT
@@ -62,11 +63,15 @@
 	int err;
 
 	/* If in BL2, retrieve the already allocated heap's info from DTB */
-	err = arm_get_dtb_mbedtls_heap_info(tb_fw_cfg_dtb, heap_addr,
-		heap_size);
-	if (err < 0) {
-		ERROR("BL2: unable to retrieve shared Mbed TLS heap "
-			"information from DTB\n");
+	if (tb_fw_cfg_dtb != NULL) {
+		err = arm_get_dtb_mbedtls_heap_info(tb_fw_cfg_dtb, heap_addr,
+			heap_size);
+		if (err < 0) {
+			ERROR("BL2: unable to retrieve shared Mbed TLS heap information from DTB\n");
+			panic();
+		}
+	} else {
+		ERROR("BL2: DTB missing, cannot get Mbed TLS heap\n");
 		panic();
 	}
 #endif
@@ -98,10 +103,16 @@
 		err = arm_set_dtb_mbedtls_heap_info(tb_fw_cfg_dtb,
 			mbedtls_heap_addr, mbedtls_heap_size);
 		if (err < 0) {
-			ERROR("BL1: unable to write shared Mbed TLS heap "
-				"information to DTB\n");
+			ERROR("BL1: unable to write shared Mbed TLS heap information to DTB\n");
 			panic();
 		}
+		/*
+		 * Ensure that the info written to the DTB is visible to other
+		 * images. It's critical because BL2 won't be able to proceed
+		 * without the heap info.
+		 */
+		flush_dcache_range((uintptr_t)tb_fw_cfg_dtb,
+			tb_fw_cfg_dtb_size);
 	}
 }
 
@@ -122,7 +133,8 @@
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
 				VERSION_2, image_info_t, 0),
 		.image_info.image_base = ARM_TB_FW_CONFIG_BASE,
-		.image_info.image_max_size = ARM_TB_FW_CONFIG_LIMIT - ARM_TB_FW_CONFIG_BASE,
+		.image_info.image_max_size =
+			ARM_TB_FW_CONFIG_LIMIT - ARM_TB_FW_CONFIG_BASE
 	};
 
 	VERBOSE("BL1: Loading TB_FW_CONFIG\n");
@@ -136,6 +148,7 @@
 	/* At this point we know that a DTB is indeed available */
 	config_base = arm_tb_fw_info.image_info.image_base;
 	tb_fw_cfg_dtb = (void *)config_base;
+	tb_fw_cfg_dtb_size = (size_t)arm_tb_fw_info.image_info.image_max_size;
 
 	/* The BL2 ep_info arg0 is modified to point to TB_FW_CONFIG */
 	image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c
index e610903..d12d09c 100644
--- a/plat/arm/common/arm_dyn_cfg_helpers.c
+++ b/plat/arm/common/arm_dyn_cfg_helpers.c
@@ -167,8 +167,6 @@
 	return 0;
 }
 
-
-#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
 /*
  * Reads and returns the Mbed TLS shared heap information from the DTB.
  * This function is supposed to be called *only* when a DTB is present.
@@ -187,8 +185,7 @@
 	/* Verify the DTB is valid and get the root node */
 	err = arm_dyn_tb_fw_cfg_init(dtb, &dtb_root);
 	if (err < 0) {
-		ERROR("%s: Invalid TB_FW_CONFIG. Cannot retrieve Mbed TLS "
-			"heap information from DTB\n", __func__);
+		ERROR("Invalid TB_FW_CONFIG. Cannot retrieve Mbed TLS heap information from DTB\n");
 		return -1;
 	}
 
@@ -196,14 +193,14 @@
 	err = fdtw_read_cells(dtb, dtb_root,
 		DTB_PROP_MBEDTLS_HEAP_ADDR, 2, heap_addr);
 	if (err < 0) {
-		ERROR("%s: error while reading %s from DTB\n", __func__,
+		ERROR("Error while reading %s from DTB\n",
 			DTB_PROP_MBEDTLS_HEAP_ADDR);
 		return -1;
 	}
 	err = fdtw_read_cells(dtb, dtb_root,
 		DTB_PROP_MBEDTLS_HEAP_SIZE, 1, heap_size);
 	if (err < 0) {
-		ERROR("%s: error while reading %s from DTB\n", __func__,
+		ERROR("Error while reading %s from DTB\n",
 			DTB_PROP_MBEDTLS_HEAP_SIZE);
 		return -1;
 	}
@@ -234,8 +231,7 @@
 	 */
 	err = arm_dyn_tb_fw_cfg_init(dtb, &dtb_root);
 	if (err < 0) {
-		ERROR("%s: Invalid TB_FW_CONFIG loaded. Unable to get "
-			"root node\n", __func__);
+		ERROR("Invalid TB_FW_CONFIG loaded. Unable to get root node\n");
 		return -1;
 	}
 
@@ -249,19 +245,18 @@
 	err = fdtw_write_inplace_cells(dtb, dtb_root,
 		DTB_PROP_MBEDTLS_HEAP_ADDR, 2, &heap_addr);
 	if (err < 0) {
-		ERROR("%s: unable to write DTB property %s\n",
-			__func__, DTB_PROP_MBEDTLS_HEAP_ADDR);
+		ERROR("Unable to write DTB property %s\n",
+			DTB_PROP_MBEDTLS_HEAP_ADDR);
 		return -1;
 	}
 
 	err = fdtw_write_inplace_cells(dtb, dtb_root,
 		DTB_PROP_MBEDTLS_HEAP_SIZE, 1, &heap_size);
 	if (err < 0) {
-		ERROR("%s: unable to write DTB property %s\n",
-			__func__, DTB_PROP_MBEDTLS_HEAP_SIZE);
+		ERROR("Unable to write DTB property %s\n",
+			DTB_PROP_MBEDTLS_HEAP_SIZE);
 		return -1;
 	}
 
 	return 0;
 }
-#endif /* TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2 */
diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index 9b78d7f..990d028 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c
@@ -81,6 +81,17 @@
 	return NULL;
 }
 
+/* CPU initialisation after wakeup from suspend */
+static void *sdei_cpu_wakeup_init(const void *arg)
+{
+	SDEI_LOG("Events masked on %lx\n", read_mpidr_el1());
+
+	/* All PEs wake up with SDEI events masked */
+	sdei_pe_mask();
+
+	return 0;
+}
+
 /* Initialise an SDEI class */
 static void sdei_class_init(sdei_class_t class)
 {
@@ -1075,3 +1086,6 @@
 
 /* Subscribe to PSCI CPU on to initialize per-CPU SDEI configuration */
 SUBSCRIBE_TO_EVENT(psci_cpu_on_finish, sdei_cpu_on_init);
+
+/* Subscribe to PSCI CPU suspend finisher for per-CPU configuration */
+SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, sdei_cpu_wakeup_init);