)]}' { "commit": "bb0fcc7e011ec4319a79734ba44353015860e39f", "tree": "98ed67adba942403174930384999e90356a864ec", "parents": [ "b7bd9863dc2f0a055e0c4bc065e071c4b1863647" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu May 05 23:42:55 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu May 05 23:47:20 2022 +0800" }, "message": "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC\n\nSMPLSEL and DRVSEL values need to updated in\nDWMMC for the IP to work correctly. This apply\non Stratix 10 device only.\n\nSigned-off-by: Loh Tien Hock \u003ctien.hock.loh@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: Ibd799a65890690682e27e4cbbc85e83ea03d51fc\n", "tree_diff": [ { "type": "modify", "old_id": "faff898d0c041c6c88a34110766e46dab759cb2b", "old_mode": 33188, "old_path": "plat/intel/soc/stratix10/bl2_plat_setup.c", "new_id": "cca564a8551ac42d6bc45cc3c46c107d1f1ec0ab", "new_mode": 33188, "new_path": "plat/intel/soc/stratix10/bl2_plat_setup.c" }, { "type": "modify", "old_id": "acc700a07b18003a84d8feb0fe1914ecc7bfc320", "old_mode": 33188, "old_path": "plat/intel/soc/stratix10/include/s10_clock_manager.h", "new_id": "1829fa6dd34bb1e919642cf20b8d9a98808a38e9", "new_mode": 33188, "new_path": "plat/intel/soc/stratix10/include/s10_clock_manager.h" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "99f86f54d474e504113d0c61efc960da3912a1fc", "new_mode": 33188, "new_path": "plat/intel/soc/stratix10/include/s10_mmc.h" }, { "type": "modify", "old_id": "b7808ae4fd6b793727c480af6b0af05fb6aa569f", "old_mode": 33188, "old_path": "plat/intel/soc/stratix10/platform.mk", "new_id": "0fdb8a1077dffd3b14e8e4ef530b52850c6411e8", "new_mode": 33188, "new_path": "plat/intel/soc/stratix10/platform.mk" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "333bdd61c0b7ab41636c8e6ad43f08bb4fae5b03", "new_mode": 33188, "new_path": "plat/intel/soc/stratix10/soc/s10_mmc.c" } ] }