)]}' { "commit": "bc0f84de40d4f1efddfb50071fff09d32f0ea9b2", "tree": "356aac39011bbd030432ce3b3103f4589ba7c645", "parents": [ "0051ff871403f6b4b1caeb615b9830860d2ea960" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Jul 12 17:13:01 2022 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Jul 21 14:26:59 2022 -0500" }, "message": "fix(errata): workaround for Cortex-X2 erratum 2371105\n\nCortex-X2 erratum 2371105 is a cat B erratum that applies to\nrevisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to\nset bit[40] of CPUACTLR2_EL1 to disable folding of demand requests\ninto older prefetches with L2 miss requests outstanding.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1775100/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: Ib4f0caac36e1ecf049871acdea45526b394b7bad\n", "tree_diff": [ { "type": "modify", "old_id": "de3b9bcd3d04873da6d7549e9f6396ea18ec3ee3", "old_mode": 33188, "old_path": "docs/design/cpu-specific-build-macros.rst", "new_id": "aafd00679e692c85ca6a6a63f79c0b155665f519", "new_mode": 33188, "new_path": "docs/design/cpu-specific-build-macros.rst" }, { "type": "modify", "old_id": "92140b1e27784c55242e24cdbe23c4176307c086", "old_mode": 33188, "old_path": "include/lib/cpus/aarch64/cortex_x2.h", "new_id": "863b8c8d3787c47fa171adffbe26a772e8dd0b9f", "new_mode": 33188, "new_path": "include/lib/cpus/aarch64/cortex_x2.h" }, { "type": "modify", "old_id": "3e0810ba08bc8e441359c8fa2570076b86df342c", "old_mode": 33188, "old_path": "lib/cpus/aarch64/cortex_x2.S", "new_id": "c810be6b0d27c5ac2d545e95d73ec50d3a0a175a", "new_mode": 33188, "new_path": "lib/cpus/aarch64/cortex_x2.S" }, { "type": "modify", "old_id": "5be0a55d66447d24fdb2b2462ffd67455467d152", "old_mode": 33188, "old_path": "lib/cpus/cpu-ops.mk", "new_id": "777c9a6a7f3d99d71417b1e4b6d88e03ae8a52e6", "new_mode": 33188, "new_path": "lib/cpus/cpu-ops.mk" } ] }