PSCI: Build option to enable D-Caches early in warmboot
This patch introduces a build option to enable D-cache early on the CPU
after warm boot. This is applicable for platforms which do not require
interconnect programming to enable cache coherency (eg: single cluster
platforms). If this option is enabled, then warm boot path enables
D-caches immediately after enabling MMU.
Fixes ARM-Software/tf-issues#456
Change-Id: I44c8787d116d7217837ced3bcf0b1d3441c8d80e
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index c7f60b5..477b55b 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -236,24 +236,27 @@
*
* The PSCI implementation invokes platform routines that enable CPUs to
* participate in coherency. On a system where CPUs are not
- * cache-coherent out of reset, having caches enabled until such time
- * might lead to coherency issues (resulting from stale data getting
- * speculatively fetched, among others). Therefore we keep data caches
- * disabled while enabling the MMU, thereby forcing data accesses to
- * have non-cacheable, nGnRnE attributes (these will always be coherent
- * with main memory).
+ * cache-coherent without appropriate platform specific programming,
+ * having caches enabled until such time might lead to coherency issues
+ * (resulting from stale data getting speculatively fetched, among
+ * others). Therefore we keep data caches disabled even after enabling
+ * the MMU for such platforms.
*
- * On systems where CPUs are cache-coherent out of reset, however, PSCI
- * need not invoke platform routines to enter coherency (as CPUs already
- * are), and there's no reason to have caches disabled either.
+ * On systems with hardware-assisted coherency, or on single cluster
+ * platforms, such platform specific programming is not required to
+ * enter coherency (as CPUs already are); and there's no reason to have
+ * caches disabled either.
*/
-#if HW_ASSISTED_COHERENCY
- mov r0, #0
-#else
mov r0, #DISABLE_DCACHE
-#endif
bl bl32_plat_enable_mmu
+#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
+ ldcopr r0, SCTLR
+ orr r0, r0, #SCTLR_C_BIT
+ stcopr r0, SCTLR
+ isb
+#endif
+
bl sp_min_warm_boot
/* Program the registers in cpu_context and exit monitor mode */