diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 94fed3a..22be419 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -35,12 +35,24 @@
 #define CAD_QSPIDATA_OFST			0xff900000
 #define CAD_QSPI_OFFSET				0xff8d2000
 
+/* FIP Setting */
+#define PLAT_FIP_BASE				(0)
+#if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_FIP_MAX_SIZE			(0x8000000)
+#else
+#define PLAT_FIP_MAX_SIZE			(0x1000000)
+#endif
+
 /* SDMMC Setting */
-# if ARM_LINUX_KERNEL_AS_BL33
+#if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_MMC_DATA_BASE			(0x10000000)
+#define PLAT_MMC_DATA_SIZE			(0x100000)
 #define SOCFPGA_MMC_BLOCK_SIZE			U(32768)
-# else
+#else
+#define PLAT_MMC_DATA_BASE			(0xffe3c000)
+#define PLAT_MMC_DATA_SIZE			(0x2000
 #define SOCFPGA_MMC_BLOCK_SIZE			U(8192)
-# endif
+#endif
 
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000
@@ -112,7 +124,7 @@
 /*******************************************************************************
  * SDMMC related pointer function
  ******************************************************************************/
-#define SDMMC_READ_BLOCKS			mmc_read_blocks
+#define SDMMC_READ_BLOCKS			sdmmc_read_blocks
 #define SDMMC_WRITE_BLOCKS			mmc_write_blocks
 
 /*******************************************************************************
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index 21cc6a3..2f0fc17 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -28,6 +28,7 @@
 			plat/intel/soc/common/aarch64/platform_common.c \
 			plat/intel/soc/common/aarch64/plat_helpers.S	\
 			plat/intel/soc/common/drivers/ccu/ncore_ccu.c	\
+			plat/intel/soc/common/drivers/sdmmc/sdmmc.c			\
 			plat/intel/soc/common/lib/sha/sha.c				\
 			plat/intel/soc/common/socfpga_delay_timer.c
 
diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index 6d0f183..11fecc4 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -103,6 +103,15 @@
 	/* Configure the pinmux */
 	config_pinmux(&reverse_handoff_ptr);
 
+	/* Configure OCRAM to NON SECURE ACCESS */
+	mmio_write_32(OCRAM_REGION_0_REG_BASE, OCRAM_NON_SECURE_ENABLE);
+	mmio_write_32(SOCFPGA_L4_PER_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
+		SOCFPGA_SDMMC_SECU_BIT_ENABLE);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR_REG_BASE + SOCFPGA_SDMMC_SECU_BIT,
+		SOCFPGA_SDMMC_SECU_BIT_ENABLE);
+	mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE,
+		SOCFPGA_LWSOC2FPGA_ENABLE);
+
 	/* Configure the clock manager */
 	if ((config_clkmgr_handoff(&reverse_handoff_ptr)) != 0) {
 		ERROR("SOCFPGA: Failed to initialize the clock manager\n");
@@ -156,7 +165,7 @@
 	switch (boot_source) {
 	case BOOT_SOURCE_SDMMC:
 		NOTICE("SDMMC boot\n");
-		sdmmc_init(&reverse_handoff_ptr, &params, &mmc_info);
+		cdns_mmc_init(&params, &mmc_info);
 		socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE);
 		break;
 
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index 3a0aea1..3e98c28 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -46,12 +46,24 @@
 #define CAD_QSPIDATA_OFST					0x10900000
 #define CAD_QSPI_OFFSET						0x108d2000
 
+/* FIP Setting */
+#define PLAT_FIP_BASE						(0)
+#if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_FIP_MAX_SIZE					(0x8000000)
+#else
+#define PLAT_FIP_MAX_SIZE					(0x1000000)
+#endif
+
 /* SDMMC Setting */
-# if ARM_LINUX_KERNEL_AS_BL33
+#if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_MMC_DATA_BASE					(0x90000000)
+#define PLAT_MMC_DATA_SIZE					(0x100000)
 #define SOCFPGA_MMC_BLOCK_SIZE					U(32768)
-# else
+#else
+#define PLAT_MMC_DATA_BASE					(0x0007D000)
+#define PLAT_MMC_DATA_SIZE					(0x2000)
 #define SOCFPGA_MMC_BLOCK_SIZE					U(8192)
-# endif
+#endif
 
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE				0x1c000000
@@ -69,10 +81,22 @@
 #define SOCFPGA_L4_SYS_SCR_REG_BASE				0x10d21100
 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE				0x10d21200
 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE				0x10d21300
+#define SOCFPGA_SDMMC_SECU_BIT					0x40
+#define SOCFPGA_LWSOC2FPGA_ENABLE				0xffe0301
+#define SOCFPGA_SDMMC_SECU_BIT_ENABLE				0x1010001
+
 
 /* Define maximum page size for NAND flash devices */
 #define PLATFORM_MTD_MAX_PAGE_SIZE				U(0x2000)
 
+/* OCRAM Register*/
+
+#define OCRAM_REG_BASE						0x108CC400
+#define OCRAM_REGION_0_OFFSET					0x18
+#define OCRAM_REGION_0_REG_BASE					(OCRAM_REG_BASE + \
+								OCRAM_REGION_0_OFFSET)
+#define OCRAM_NON_SECURE_ENABLE					0x0
+
 /*******************************************************************************
  * Platform memory map related constants
  ******************************************************************************/
diff --git a/plat/intel/soc/common/drivers/sdmmc/sdmmc.c b/plat/intel/soc/common/drivers/sdmmc/sdmmc.c
index 48f91eb..62698a9 100644
--- a/plat/intel/soc/common/drivers/sdmmc/sdmmc.c
+++ b/plat/intel/soc/common/drivers/sdmmc/sdmmc.c
@@ -18,53 +18,26 @@
 #include <lib/mmio.h>
 #include <lib/utils.h>
 
-#include "agilex5_pinmux.h"
 #include "sdmmc.h"
 #include "socfpga_mailbox.h"
+#include "wdt/watchdog.h"
 
 static const struct mmc_ops *ops;
 static unsigned int mmc_ocr_value;
-static struct mmc_csd_emmc mmc_csd;
-static struct sd_switch_status sd_switch_func_status;
-static unsigned char mmc_ext_csd[512] __aligned(16);
 static unsigned int mmc_flags;
-static struct mmc_device_info *mmc_dev_info;
 static unsigned int rca;
-static unsigned int scr[2]__aligned(16) = { 0 };
 
 extern const struct mmc_ops cdns_sdmmc_ops;
 extern struct cdns_sdmmc_params cdns_params;
 extern struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg;
 extern struct cdns_sdmmc_sdhc sdmmc_sdhc_reg;
 
-static bool is_cmd23_enabled(void)
+bool is_cmd23_enabled(void)
 {
 	return ((mmc_flags & MMC_FLAG_CMD23) != 0U);
 }
 
-static bool is_sd_cmd6_enabled(void)
-{
-	return ((mmc_flags & MMC_FLAG_SD_CMD6) != 0U);
-}
-
-/* TODO: Will romove once ATF driver is developed */
-void sdmmc_pin_config(void)
-{
-	/* temp use base + addr. Official must change to common method */
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x00, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x04, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x08, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x0C, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x10, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x14, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x18, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x1C, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x20, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x24, 0x0);
-	mmio_write_32(AGX5_PINMUX_PIN0SEL+0x28, 0x0);
-}
-
-static int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
+int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
 			unsigned int r_type, unsigned int *r_data)
 {
 	struct mmc_cmd cmd;
@@ -94,7 +67,7 @@
 	return ret;
 }
 
-static int sdmmc_device_state(void)
+int sdmmc_device_state(void)
 {
 	int retries = DEFAULT_SDMMC_MAX_RETRIES;
 	unsigned int resp_data[4];
@@ -125,521 +98,12 @@
 	return MMC_GET_STATE(resp_data[0]);
 }
 
-static int sdmmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
-{
-	int ret;
-
-	ret = sdmmc_send_cmd(MMC_CMD(6),
-			   EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
-			   EXTCSD_VALUE(value) | EXTCSD_CMD_SET_NORMAL,
-			   MMC_RESPONSE_R1B, NULL);
-	if (ret != 0) {
-		return ret;
-	}
-
-	do {
-		ret = sdmmc_device_state();
-		if (ret < 0) {
-			return ret;
-		}
-	} while (ret == MMC_STATE_PRG);
-
-	return 0;
-}
-
-static int sdmmc_mmc_sd_switch(unsigned int bus_width)
-{
-	int ret;
-	int retries = DEFAULT_SDMMC_MAX_RETRIES;
-	unsigned int bus_width_arg = 0;
-
-	/* CMD55: Application Specific Command */
-	ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET,
-			   MMC_RESPONSE_R5, NULL);
-	if (ret != 0) {
-		return ret;
-	}
-
-	ret = ops->prepare(0, (uintptr_t)&scr, sizeof(scr));
-	if (ret != 0) {
-		return ret;
-	}
-
-	/* ACMD51: SEND_SCR */
-	do {
-		ret = sdmmc_send_cmd(MMC_ACMD(51), 0, MMC_RESPONSE_R1, NULL);
-		if ((ret != 0) && (retries == 0)) {
-			ERROR("ACMD51 failed after %d retries (ret=%d)\n",
-			      DEFAULT_SDMMC_MAX_RETRIES, ret);
-			return ret;
-		}
-
-		retries--;
-	} while (ret != 0);
-
-	ret = ops->read(0, (uintptr_t)&scr, sizeof(scr));
-	if (ret != 0) {
-		return ret;
-	}
-
-	if (((scr[0] & SD_SCR_BUS_WIDTH_4) != 0U) &&
-	    (bus_width == MMC_BUS_WIDTH_4)) {
-		bus_width_arg = 2;
-	}
-
-	/* CMD55: Application Specific Command */
-	ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET,
-			   MMC_RESPONSE_R5, NULL);
-	if (ret != 0) {
-		return ret;
-	}
-
-	/* ACMD6: SET_BUS_WIDTH */
-	ret = sdmmc_send_cmd(MMC_ACMD(6), bus_width_arg, MMC_RESPONSE_R1, NULL);
-	if (ret != 0) {
-		return ret;
-	}
-
-	do {
-		ret = sdmmc_device_state();
-		if (ret < 0) {
-			return ret;
-		}
-	} while (ret == MMC_STATE_PRG);
-
-	return 0;
-}
-
-static int sdmmc_set_ios(unsigned int clk, unsigned int bus_width)
-{
-	int ret;
-	unsigned int width = bus_width;
-
-	if (mmc_dev_info->mmc_dev_type != MMC_IS_EMMC) {
-		if (width == MMC_BUS_WIDTH_8) {
-			WARN("Wrong bus config for SD-card, force to 4\n");
-			width = MMC_BUS_WIDTH_4;
-		}
-		ret = sdmmc_mmc_sd_switch(width);
-		if (ret != 0) {
-			return ret;
-		}
-	} else if (mmc_csd.spec_vers == 4U) {
-		ret = sdmmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH,
-				      (unsigned int)width);
-		if (ret != 0) {
-			return ret;
-		}
-	} else {
-		VERBOSE("Wrong MMC type or spec version\n");
-	}
-
-	return ops->set_ios(clk, width);
-}
-
-static int sdmmc_fill_device_info(void)
-{
-	unsigned long long c_size;
-	unsigned int speed_idx;
-	unsigned int nb_blocks;
-	unsigned int freq_unit;
-	int ret = 0;
-	struct mmc_csd_sd_v2 *csd_sd_v2;
-
-	switch (mmc_dev_info->mmc_dev_type) {
-	case MMC_IS_EMMC:
-		mmc_dev_info->block_size = MMC_BLOCK_SIZE;
-
-		ret = ops->prepare(0, (uintptr_t)&mmc_ext_csd,
-				   sizeof(mmc_ext_csd));
-		if (ret != 0) {
-			return ret;
-		}
-
-		/* MMC CMD8: SEND_EXT_CSD */
-		ret = sdmmc_send_cmd(MMC_CMD(8), 0, MMC_RESPONSE_R1, NULL);
-		if (ret != 0) {
-			return ret;
-		}
-
-		ret = ops->read(0, (uintptr_t)&mmc_ext_csd,
-				sizeof(mmc_ext_csd));
-		if (ret != 0) {
-			return ret;
-		}
-
-		do {
-			ret = sdmmc_device_state();
-			if (ret < 0) {
-				return ret;
-			}
-		} while (ret != MMC_STATE_TRAN);
-
-		nb_blocks = (mmc_ext_csd[CMD_EXTCSD_SEC_CNT] << 0) |
-			    (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 1] << 8) |
-			    (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 2] << 16) |
-			    (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 3] << 24);
-
-		mmc_dev_info->device_size = (unsigned long long)nb_blocks *
-			mmc_dev_info->block_size;
-
-		break;
-
-	case MMC_IS_SD:
-		/*
-		 * Use the same mmc_csd struct, as required fields here
-		 * (READ_BL_LEN, C_SIZE, CSIZE_MULT) are common with eMMC.
-		 */
-		mmc_dev_info->block_size = BIT_32(mmc_csd.read_bl_len);
-
-		c_size = ((unsigned long long)mmc_csd.c_size_high << 2U) |
-			 (unsigned long long)mmc_csd.c_size_low;
-		assert(c_size != 0xFFFU);
-
-		mmc_dev_info->device_size = (c_size + 1U) *
-					    BIT_64(mmc_csd.c_size_mult + 2U) *
-					    mmc_dev_info->block_size;
-
-		break;
-
-	case MMC_IS_SD_HC:
-		assert(mmc_csd.csd_structure == 1U);
-
-		mmc_dev_info->block_size = MMC_BLOCK_SIZE;
-
-		/* Need to use mmc_csd_sd_v2 struct */
-		csd_sd_v2 = (struct mmc_csd_sd_v2 *)&mmc_csd;
-		c_size = ((unsigned long long)csd_sd_v2->c_size_high << 16) |
-			 (unsigned long long)csd_sd_v2->c_size_low;
-
-		mmc_dev_info->device_size = (c_size + 1U) << SDMMC_MULT_BY_512K_SHIFT;
-
-		break;
-
-	default:
-		ret = -EINVAL;
-		break;
-	}
-
-	if (ret < 0) {
-		return ret;
-	}
-
-	speed_idx = (mmc_csd.tran_speed & CSD_TRAN_SPEED_MULT_MASK) >>
-			 CSD_TRAN_SPEED_MULT_SHIFT;
-
-	assert(speed_idx > 0U);
-
-	if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
-		mmc_dev_info->max_bus_freq = tran_speed_base[speed_idx];
-	} else {
-		mmc_dev_info->max_bus_freq = sd_tran_speed_base[speed_idx];
-	}
-
-	freq_unit = mmc_csd.tran_speed & CSD_TRAN_SPEED_UNIT_MASK;
-	while (freq_unit != 0U) {
-		mmc_dev_info->max_bus_freq *= 10U;
-		--freq_unit;
-	}
-
-	mmc_dev_info->max_bus_freq *= 10000U;
-
-	return 0;
-}
-
-static int sdmmc_sd_switch(unsigned int mode, unsigned char group,
-		     unsigned char func)
-{
-	unsigned int group_shift = (group - 1U) * 4U;
-	unsigned int group_mask = GENMASK(group_shift + 3U,  group_shift);
-	unsigned int arg;
-	int ret;
-
-	ret = ops->prepare(0, (uintptr_t)&sd_switch_func_status,
-			   sizeof(sd_switch_func_status));
-	if (ret != 0) {
-		return ret;
-	}
-
-	/* MMC CMD6: SWITCH_FUNC */
-	arg = mode | SD_SWITCH_ALL_GROUPS_MASK;
-	arg &= ~group_mask;
-	arg |= func << group_shift;
-	ret = sdmmc_send_cmd(MMC_CMD(6), arg, MMC_RESPONSE_R1, NULL);
-	if (ret != 0) {
-		return ret;
-	}
-
-	return ops->read(0, (uintptr_t)&sd_switch_func_status,
-			 sizeof(sd_switch_func_status));
-}
-
-static int sdmmc_sd_send_op_cond(void)
-{
-	int n;
-	unsigned int resp_data[4];
-
-	for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) {
-		int ret;
-
-		/* CMD55: Application Specific Command */
-		ret = sdmmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R1, NULL);
-		if (ret != 0) {
-			return ret;
-		}
-
-		/* ACMD41: SD_SEND_OP_COND */
-		ret = sdmmc_send_cmd(MMC_ACMD(41), OCR_HCS |
-			mmc_dev_info->ocr_voltage, MMC_RESPONSE_R3,
-			&resp_data[0]);
-		if (ret != 0) {
-			return ret;
-		}
-
-		if ((resp_data[0] & OCR_POWERUP) != 0U) {
-			mmc_ocr_value = resp_data[0];
-
-			if ((mmc_ocr_value & OCR_HCS) != 0U) {
-				mmc_dev_info->mmc_dev_type = MMC_IS_SD_HC;
-			} else {
-				mmc_dev_info->mmc_dev_type = MMC_IS_SD;
-			}
-
-			return 0;
-		}
-
-		mdelay(10);
-	}
-
-	ERROR("ACMD41 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES);
-
-	return -EIO;
-}
-
-static int sdmmc_reset_to_idle(void)
-{
-	int ret;
-
-	/* CMD0: reset to IDLE */
-	ret = sdmmc_send_cmd(MMC_CMD(0), 0, 0, NULL);
-	if (ret != 0) {
-		return ret;
-	}
-
-	mdelay(2);
-
-	return 0;
-}
-
-static int sdmmc_send_op_cond(void)
-{
-	int ret, n;
-	unsigned int resp_data[4];
-
-	ret = sdmmc_reset_to_idle();
-	if (ret != 0) {
-		return ret;
-	}
-
-	for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) {
-		ret = sdmmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
-				   OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7,
-				   MMC_RESPONSE_R3, &resp_data[0]);
-		if (ret != 0) {
-			return ret;
-		}
-
-		if ((resp_data[0] & OCR_POWERUP) != 0U) {
-			mmc_ocr_value = resp_data[0];
-			return 0;
-		}
-
-		mdelay(10);
-	}
-
-	ERROR("CMD1 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES);
-
-	return -EIO;
-}
-
-static int sdmmc_enumerate(unsigned int clk, unsigned int bus_width)
-{
-	int ret;
-	unsigned int resp_data[4];
-
-	ops->init();
-
-	ret = sdmmc_reset_to_idle();
-	if (ret != 0) {
-		return ret;
-	}
-
-	if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
-		ret = sdmmc_send_op_cond();
-	} else {
-		/* CMD8: Send Interface Condition Command */
-		ret = sdmmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN,
-				   MMC_RESPONSE_R5, &resp_data[0]);
-
-		if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) {
-			ret = sdmmc_sd_send_op_cond();
-		}
-	}
-	if (ret != 0) {
-		return ret;
-	}
-
-	/* CMD2: Card Identification */
-	ret = sdmmc_send_cmd(MMC_CMD(2), 0, MMC_RESPONSE_R2, NULL);
-	if (ret != 0) {
-		return ret;
-	}
-
-	/* CMD3: Set Relative Address */
-	if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
-		rca = MMC_FIX_RCA;
-		ret = sdmmc_send_cmd(MMC_CMD(3), rca << RCA_SHIFT_OFFSET,
-				   MMC_RESPONSE_R1, NULL);
-		if (ret != 0) {
-			return ret;
-		}
-	} else {
-		ret = sdmmc_send_cmd(MMC_CMD(3), 0,
-				   MMC_RESPONSE_R6, &resp_data[0]);
-		if (ret != 0) {
-			return ret;
-		}
-
-		rca = (resp_data[0] & 0xFFFF0000U) >> 16;
-	}
-
-	/* CMD9: CSD Register */
-	ret = sdmmc_send_cmd(MMC_CMD(9), rca << RCA_SHIFT_OFFSET,
-			   MMC_RESPONSE_R2, &resp_data[0]);
-	if (ret != 0) {
-		return ret;
-	}
-
-	memcpy_s(&mmc_csd, sizeof(mmc_csd) / MBOX_WORD_BYTE,
-		&resp_data, sizeof(resp_data) / MBOX_WORD_BYTE);
-
-	/* CMD7: Select Card */
-	ret = sdmmc_send_cmd(MMC_CMD(7), rca << RCA_SHIFT_OFFSET,
-			   MMC_RESPONSE_R1, NULL);
-	if (ret != 0) {
-		return ret;
-	}
-
-	do {
-		ret = sdmmc_device_state();
-		if (ret < 0) {
-			return ret;
-		}
-	} while (ret != MMC_STATE_TRAN);
-
-	ret = sdmmc_set_ios(clk, bus_width);
-	if (ret != 0) {
-		return ret;
-	}
-
-	ret = sdmmc_fill_device_info();
-	if (ret != 0) {
-		return ret;
-	}
-
-	if (is_sd_cmd6_enabled() &&
-	    (mmc_dev_info->mmc_dev_type == MMC_IS_SD_HC)) {
-		/* Try to switch to High Speed Mode */
-		ret = sdmmc_sd_switch(SD_SWITCH_FUNC_CHECK, 1U, 1U);
-		if (ret != 0) {
-			return ret;
-		}
-
-		if ((sd_switch_func_status.support_g1 & BIT(9)) == 0U) {
-			/* High speed not supported, keep default speed */
-			return 0;
-		}
-
-		ret = sdmmc_sd_switch(SD_SWITCH_FUNC_SWITCH, 1U, 1U);
-		if (ret != 0) {
-			return ret;
-		}
-
-		if ((sd_switch_func_status.sel_g2_g1 & 0x1U) == 0U) {
-			/* Cannot switch to high speed, keep default speed */
-			return 0;
-		}
-
-		mmc_dev_info->max_bus_freq = 50000000U;
-		ret = ops->set_ios(clk, bus_width);
-	}
-
-	return ret;
-}
-
 size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size)
 {
-	int ret;
-	unsigned int cmd_idx, cmd_arg;
+	mmc_read_blocks(lba, buf, size);
 
-	assert((ops != NULL) &&
-	       (ops->read != NULL) &&
-	       (size != 0U) &&
-	       ((size & MMC_BLOCK_MASK) == 0U));
-
-	ret = ops->prepare(lba, buf, size);
-	if (ret != 0) {
-		return 0;
-	}
-
-	if (is_cmd23_enabled()) {
-		/* Set block count */
-		ret = sdmmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE,
-				   MMC_RESPONSE_R1, NULL);
-		if (ret != 0) {
-			return 0;
-		}
-
-		cmd_idx = MMC_CMD(18);
-	} else {
-		if (size > MMC_BLOCK_SIZE) {
-			cmd_idx = MMC_CMD(18);
-		} else {
-			cmd_idx = MMC_CMD(17);
-		}
-	}
-
-	if (((mmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) &&
-	    (mmc_dev_info->mmc_dev_type != MMC_IS_SD_HC)) {
-		cmd_arg = lba * MMC_BLOCK_SIZE;
-	} else {
-		cmd_arg = lba;
-	}
-
-	ret = sdmmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL);
-	if (ret != 0) {
-		return 0;
-	}
-
-	ret = ops->read(lba, buf, size);
-	if (ret != 0) {
-		return 0;
-	}
-
-	/* Wait buffer empty */
-	do {
-		ret = sdmmc_device_state();
-		if (ret < 0) {
-			return 0;
-		}
-	} while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_DATA));
-
-	if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) {
-		ret = sdmmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL);
-		if (ret != 0) {
-			return 0;
-		}
-	}
+	/* Restart watchdog for reading each chunk byte */
+	watchdog_sw_rst();
 
 	return size;
 }
@@ -710,64 +174,3 @@
 
 	return size;
 }
-
-int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
-	     unsigned int width, unsigned int flags,
-	     struct mmc_device_info *device_info)
-{
-	assert((ops_ptr != NULL) &&
-	       (ops_ptr->init != NULL) &&
-	       (ops_ptr->send_cmd != NULL) &&
-	       (ops_ptr->set_ios != NULL) &&
-	       (ops_ptr->prepare != NULL) &&
-	       (ops_ptr->read != NULL) &&
-	       (ops_ptr->write != NULL) &&
-	       (device_info != NULL) &&
-	       (clk != 0) &&
-	       ((width == MMC_BUS_WIDTH_1) ||
-		(width == MMC_BUS_WIDTH_4) ||
-		(width == MMC_BUS_WIDTH_8) ||
-		(width == MMC_BUS_WIDTH_DDR_4) ||
-		(width == MMC_BUS_WIDTH_DDR_8)));
-
-	ops = ops_ptr;
-	mmc_flags = flags;
-	mmc_dev_info = device_info;
-
-	return sdmmc_enumerate(clk, width);
-}
-
-int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params, struct mmc_device_info *info)
-{
-	int result = 0;
-
-	/* SDMMC pin mux configuration */
-	sdmmc_pin_config();
-	cdns_set_sdmmc_var(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
-	result = cdns_sd_host_init(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg);
-	if (result < 0) {
-		return result;
-	}
-
-	assert((params != NULL) &&
-	       ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
-	       ((params->desc_base & MMC_BLOCK_MASK) == 0) &&
-	       ((params->desc_size & MMC_BLOCK_MASK) == 0) &&
-		   ((params->reg_pinmux & MMC_BLOCK_MASK) == 0) &&
-		   ((params->reg_phy & MMC_BLOCK_MASK) == 0) &&
-	       (params->desc_size > 0) &&
-	       (params->clk_rate > 0) &&
-	       ((params->bus_width == MMC_BUS_WIDTH_1) ||
-		(params->bus_width == MMC_BUS_WIDTH_4) ||
-		(params->bus_width == MMC_BUS_WIDTH_8)));
-
-	memcpy_s(&cdns_params, sizeof(struct cdns_sdmmc_params) / MBOX_WORD_BYTE,
-		params, sizeof(struct cdns_sdmmc_params) / MBOX_WORD_BYTE);
-	cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type;
-	cdns_params.cdn_sdmmc_dev_mode = SD_DS;
-
-	result = sd_or_mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width,
-		params->flags, info);
-
-	return result;
-}
diff --git a/plat/intel/soc/common/drivers/sdmmc/sdmmc.h b/plat/intel/soc/common/drivers/sdmmc/sdmmc.h
index 16c6b04..3f6119c 100644
--- a/plat/intel/soc/common/drivers/sdmmc/sdmmc.h
+++ b/plat/intel/soc/common/drivers/sdmmc/sdmmc.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,10 +34,12 @@
  * @hoff_ptr: Pointer to the hand-off data
  * Return: 0 on success, a negative errno on failure
  */
-int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params,
-	     struct mmc_device_info *info);
-int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
-	     unsigned int width, unsigned int flags,
-	     struct mmc_device_info *device_info);
 void sdmmc_pin_config(void);
+size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size);
+size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size);
+int sdmmc_device_state(void);
+bool is_cmd23_enabled(void);
+int sdmmc_send_cmd(unsigned int idx, unsigned int arg,
+			unsigned int r_type, unsigned int *r_data);
+
 #endif
diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c
index 7679f59..66b5216 100644
--- a/plat/intel/soc/common/socfpga_storage.c
+++ b/plat/intel/soc/common/socfpga_storage.c
@@ -22,22 +22,12 @@
 #include <drivers/partition/partition.h>
 #include <lib/mmio.h>
 #include <tools_share/firmware_image_package.h>
+
 #include "drivers/sdmmc/sdmmc.h"
 #include "socfpga_private.h"
 #include "socfpga_ros.h"
 
 
-#define PLAT_FIP_BASE		(0)
-# if ARM_LINUX_KERNEL_AS_BL33
-#define PLAT_FIP_MAX_SIZE	(0x8000000)
-#define PLAT_MMC_DATA_BASE	(0x10000000)
-#define PLAT_MMC_DATA_SIZE	(0x100000)
-# else
-#define PLAT_FIP_MAX_SIZE	(0x1000000)
-#define PLAT_MMC_DATA_BASE	(0xffe3c000)
-#define PLAT_MMC_DATA_SIZE	(0x2000)
-# endif
-
 static const io_dev_connector_t *fip_dev_con;
 static const io_dev_connector_t *boot_dev_con;
 
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index c477787..1deed84 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -30,12 +30,14 @@
 #define CAD_QSPIDATA_OFST			0xff900000
 #define CAD_QSPI_OFFSET				0xff8d2000
 
+/* FIP Setting */
+#define PLAT_FIP_BASE				(0)
+#define PLAT_FIP_MAX_SIZE			(0x1000000)
+
 /* SDMMC Setting */
-# if ARM_LINUX_KERNEL_AS_BL33
-#define SOCFPGA_MMC_BLOCK_SIZE			U(32768)
-# else
+#define PLAT_MMC_DATA_BASE			(0xffe3c000)
+#define PLAT_MMC_DATA_SIZE			(0x2000)
 #define SOCFPGA_MMC_BLOCK_SIZE			U(8192)
-# endif
 
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		U(0xf7000000)
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index cd5b076..015ae12 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -29,12 +29,14 @@
 #define CAD_QSPIDATA_OFST			0xff900000
 #define CAD_QSPI_OFFSET				0xff8d2000
 
+/* FIP Setting */
+#define PLAT_FIP_BASE				(0)
+#define PLAT_FIP_MAX_SIZE			(0x1000000)
+
 /* SDMMC Setting */
-# if ARM_LINUX_KERNEL_AS_BL33
-#define SOCFPGA_MMC_BLOCK_SIZE			U(32768)
-# else
+#define PLAT_MMC_DATA_BASE			(0xffe3c000)
+#define PLAT_MMC_DATA_SIZE			(0x2000)
 #define SOCFPGA_MMC_BLOCK_SIZE			U(8192)
-# endif
 
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000