)]}' { "commit": "bf1af154db2c89028a8a551c18885add35d38966", "tree": "28621ff2a84e4cfce00ad8787f4992eeef47d78c", "parents": [ "1777ac11a54096de03cff09d212126e8ce077858" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@st.com", "time": "Fri Sep 04 17:39:12 2020 +0200" }, "committer": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Fri Dec 03 09:19:53 2021 +0100" }, "message": "feat(stm32mp1): preserve the PLL4 settings for USB boot\n\nThe PLL4 can be used by ROM code as the source clock of USB PHYC and,\nin this case, the PLL4 configuration must be preserved\nwith pll4_preserve to avoid USB disturbance.\n\nThis patch also adds an error when the clock tree PLL4 configuration\nis not the PLL4 configuration used by ROM code; this error allows to\ndetect a invalid clock tree.\n\nThis commit corrects the coverity issue 343023.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@st.com\u003e\nChange-Id: I4bae9312a2db8dd342a38e649513d689b13976bb\n", "tree_diff": [ { "type": "modify", "old_id": "3ebc376cda76b68265e72f4404e92a37cd875ab0", "old_mode": 33188, "old_path": "drivers/st/clk/stm32mp1_clk.c", "new_id": "5d4b8fbedb85be412e31539869cd3a4f8f7a3caf", "new_mode": 33188, "new_path": "drivers/st/clk/stm32mp1_clk.c" } ] }