diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c
index bf262c4..a0900c4 100644
--- a/plat/xilinx/common/plat_startup.c
+++ b/plat/xilinx/common/plat_startup.c
@@ -24,36 +24,36 @@
  * CPU#			5:6		00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3
  */
 
-#define FSBL_FLAGS_ESTATE_SHIFT		0
-#define FSBL_FLAGS_ESTATE_MASK		(1 << FSBL_FLAGS_ESTATE_SHIFT)
-#define FSBL_FLAGS_ESTATE_A64		0
-#define FSBL_FLAGS_ESTATE_A32		1
+#define FSBL_FLAGS_ESTATE_SHIFT		0U
+#define FSBL_FLAGS_ESTATE_MASK		(1U << FSBL_FLAGS_ESTATE_SHIFT)
+#define FSBL_FLAGS_ESTATE_A64		0U
+#define FSBL_FLAGS_ESTATE_A32		1U
 
-#define FSBL_FLAGS_ENDIAN_SHIFT		1
-#define FSBL_FLAGS_ENDIAN_MASK		(1 << FSBL_FLAGS_ENDIAN_SHIFT)
-#define FSBL_FLAGS_ENDIAN_LE		0
-#define FSBL_FLAGS_ENDIAN_BE		1
+#define FSBL_FLAGS_ENDIAN_SHIFT		1U
+#define FSBL_FLAGS_ENDIAN_MASK		(1U << FSBL_FLAGS_ENDIAN_SHIFT)
+#define FSBL_FLAGS_ENDIAN_LE		0U
+#define FSBL_FLAGS_ENDIAN_BE		1U
 
-#define FSBL_FLAGS_TZ_SHIFT		2
-#define FSBL_FLAGS_TZ_MASK		(1 << FSBL_FLAGS_TZ_SHIFT)
-#define FSBL_FLAGS_NON_SECURE		0
-#define FSBL_FLAGS_SECURE		1
+#define FSBL_FLAGS_TZ_SHIFT		2U
+#define FSBL_FLAGS_TZ_MASK		(1U << FSBL_FLAGS_TZ_SHIFT)
+#define FSBL_FLAGS_NON_SECURE		0U
+#define FSBL_FLAGS_SECURE		1U
 
-#define FSBL_FLAGS_EL_SHIFT		3
-#define FSBL_FLAGS_EL_MASK		(3 << FSBL_FLAGS_EL_SHIFT)
-#define FSBL_FLAGS_EL0			0
-#define FSBL_FLAGS_EL1			1
-#define FSBL_FLAGS_EL2			2
-#define FSBL_FLAGS_EL3			3
+#define FSBL_FLAGS_EL_SHIFT		3U
+#define FSBL_FLAGS_EL_MASK		(3U << FSBL_FLAGS_EL_SHIFT)
+#define FSBL_FLAGS_EL0			0U
+#define FSBL_FLAGS_EL1			1U
+#define FSBL_FLAGS_EL2			2U
+#define FSBL_FLAGS_EL3			3U
 
-#define FSBL_FLAGS_CPU_SHIFT		5
-#define FSBL_FLAGS_CPU_MASK		(3 << FSBL_FLAGS_CPU_SHIFT)
-#define FSBL_FLAGS_A53_0		0
-#define FSBL_FLAGS_A53_1		1
-#define FSBL_FLAGS_A53_2		2
-#define FSBL_FLAGS_A53_3		3
+#define FSBL_FLAGS_CPU_SHIFT		5U
+#define FSBL_FLAGS_CPU_MASK		(3U << FSBL_FLAGS_CPU_SHIFT)
+#define FSBL_FLAGS_A53_0		0U
+#define FSBL_FLAGS_A53_1		1U
+#define FSBL_FLAGS_A53_2		2U
+#define FSBL_FLAGS_A53_3		3U
 
-#define FSBL_MAX_PARTITIONS		8
+#define FSBL_MAX_PARTITIONS		8U
 
 /* Structure corresponding to each partition entry */
 struct xfsbl_partition {
@@ -193,8 +193,8 @@
 	 */
 	for (size_t i = 0; i < ATFHandoffParams->num_entries; i++) {
 		entry_point_info_t *image;
-		int32_t target_estate, target_secure;
-		int32_t target_cpu, target_endianness, target_el;
+		int32_t target_estate, target_secure, target_cpu;
+		uint32_t target_endianness, target_el;
 
 		VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i,
 			ATFHandoffParams->partition[i].entry_point,
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 5890311..3946e9b 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -215,8 +215,8 @@
 #define ZYNQMP_PL_STATUS_MASK	BIT(ZYNQMP_PL_STATUS_BIT)
 #define ZYNQMP_CSU_VERSION_MASK	~(ZYNQMP_PL_STATUS_MASK)
 
-#define SILICON_ID_XCK24	0x4714093
-#define SILICON_ID_XCK26	0x4724093
+#define SILICON_ID_XCK24	0x4714093U
+#define SILICON_ID_XCK26	0x4724093U
 
 static char *zynqmp_get_silicon_idcode_name(void)
 {
@@ -317,7 +317,7 @@
 	ver &= ZYNQMP_PS_VER_MASK;
 	ver >>= ZYNQMP_PS_VER_SHIFT;
 
-	return ver + 1;
+	return ver + 1U;
 }
 
 static void zynqmp_print_platform_name(void)
diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index 19b6937..877127b 100644
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -163,40 +163,40 @@
 #define ZYNQMP_CSU_VERSION_SILICON	0
 #define ZYNQMP_CSU_VERSION_QEMU		3
 
-#define ZYNQMP_RTL_VER_MASK		0xFF0
+#define ZYNQMP_RTL_VER_MASK		0xFF0U
 #define ZYNQMP_RTL_VER_SHIFT		4
 
-#define ZYNQMP_PS_VER_MASK		0xF
+#define ZYNQMP_PS_VER_MASK		0xFU
 #define ZYNQMP_PS_VER_SHIFT		0
 
 #define ZYNQMP_CSU_BASEADDR		U(0xFFCA0000)
-#define ZYNQMP_CSU_IDCODE_OFFSET	0x40
+#define ZYNQMP_CSU_IDCODE_OFFSET	0x40U
 
-#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT	0
-#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK	(0xFFF << \
+#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT	0U
+#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK	(0xFFFU << \
 					ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
 #define ZYNQMP_CSU_IDCODE_XILINX_ID		0x093
 
-#define ZYNQMP_CSU_IDCODE_SVD_SHIFT		12
-#define ZYNQMP_CSU_IDCODE_SVD_MASK		(0x7 << \
+#define ZYNQMP_CSU_IDCODE_SVD_SHIFT		12U
+#define ZYNQMP_CSU_IDCODE_SVD_MASK		(0x7U << \
 						 ZYNQMP_CSU_IDCODE_SVD_SHIFT)
-#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15
-#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xF << \
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15U
+#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xFU << \
 					ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
-#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT	19
-#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK	(0x3 << \
+#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT	19U
+#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK	(0x3U << \
 					ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
-#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT		21
-#define ZYNQMP_CSU_IDCODE_FAMILY_MASK		(0x7F << \
+#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT		21U
+#define ZYNQMP_CSU_IDCODE_FAMILY_MASK		(0x7FU << \
 					ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
 #define ZYNQMP_CSU_IDCODE_FAMILY		0x23
 
-#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT	28
-#define ZYNQMP_CSU_IDCODE_REVISION_MASK		(0xF << \
+#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT	28U
+#define ZYNQMP_CSU_IDCODE_REVISION_MASK		(0xFU << \
 					ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
-#define ZYNQMP_CSU_IDCODE_REVISION		0
+#define ZYNQMP_CSU_IDCODE_REVISION		0U
 
-#define ZYNQMP_CSU_VERSION_OFFSET	0x44
+#define ZYNQMP_CSU_VERSION_OFFSET	0x44U
 
 /* Efuse */
 #define EFUSE_BASEADDR		U(0xFFCC0000)
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index 655a776..b7408b1 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -176,7 +176,7 @@
 {
 	VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
 
-	int32_t pstate = psci_get_pstate_type(power_state);
+	uint32_t pstate = psci_get_pstate_type(power_state);
 
 	assert(req_state);
 
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index bfc6e44..c6bed7d 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -2610,7 +2610,7 @@
 		}
 	}
 
-	for (i = 0; i < 3; i++) {
+	for (i = 0; i < 3U; i++) {
 		parents[i] = clk_parents[index + i];
 		if (clk_parents[index + i] == CLK_NA_PARENT) {
 			break;
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index 1380895..8a5a25a 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -35,7 +35,7 @@
 
 	val = mmio_read_32(ZYNQMP_RPU_GLBL_CNTL);
 	val &= ZYNQMP_SLSPLIT_MASK;
-	if (val == 0) {
+	if (val == 0U) {
 		*mode = PM_RPU_MODE_LOCKSTEP;
 	} else {
 		*mode = PM_RPU_MODE_SPLIT;
@@ -309,7 +309,7 @@
 		return ret;
 	}
 
-	if ((val & mask) == 0) {
+	if ((val & mask) == 0U) {
 		ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
 		if (ret != PM_RET_SUCCESS) {
 			return ret;
@@ -325,7 +325,7 @@
 			goto reset_release;
 		}
 
-		if (value == 0) {
+		if (value == 0U) {
 			ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
 					    (ZYNQMP_SD_ITAPDLYENA_MASK <<
 					     shift), 0);
diff --git a/plat/xilinx/zynqmp/pm_service/pm_defs.h b/plat/xilinx/zynqmp/pm_service/pm_defs.h
index 8eb197a..d48df55 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_defs.h
@@ -17,10 +17,10 @@
  * Version number is a 32bit value, like:
  * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
  */
-#define PM_VERSION_MAJOR	1
-#define PM_VERSION_MINOR	1
+#define PM_VERSION_MAJOR	1U
+#define PM_VERSION_MINOR	1U
 
-#define PM_VERSION	((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
+#define PM_VERSION	((PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR)
 
 /**
  * PM API versions
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
index 0b366d7..a136ebc 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -214,7 +214,7 @@
 		ERROR("BL31: Platform Management API version error. Expected: "
 		      "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR,
 		      PM_VERSION_MINOR, pm_ctx.api_version >> 16,
-		      pm_ctx.api_version & 0xFFFF);
+		      pm_ctx.api_version & 0xFFFFU);
 		return -EINVAL;
 	}