diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c
index f5f91e3..e910ee5 100644
--- a/plat/allwinner/common/sunxi_bl31_setup.c
+++ b/plat/allwinner/common/sunxi_bl31_setup.c
@@ -64,6 +64,22 @@
 
 void bl31_platform_setup(void)
 {
+	const char *soc_name;
+	uint16_t soc_id = sunxi_read_soc_id();
+
+	switch (soc_id) {
+	case 0x1689:
+		soc_name = "A64/H64/R18";
+		break;
+	case 0x1718:
+		soc_name = "H5";
+		break;
+	default:
+		soc_name = "unknown";
+		break;
+	}
+	NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id);
+
 	generic_delay_timer_init();
 
 	/* Configure the interrupt controller */
diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
index 9069a17..fc9bf20 100644
--- a/plat/allwinner/common/sunxi_common.c
+++ b/plat/allwinner/common/sunxi_common.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <mmio.h>
 #include <platform.h>
 #include <platform_def.h>
 #include <sunxi_def.h>
@@ -54,3 +55,19 @@
 
 	enable_mmu_el3(0);
 }
+
+#define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24)
+uint16_t sunxi_read_soc_id(void)
+{
+	uint32_t reg = mmio_read_32(SRAM_VER_REG);
+
+	/* Set bit 15 to prepare for the SOCID read. */
+	mmio_write_32(SRAM_VER_REG, reg | BIT(15));
+
+	reg = mmio_read_32(SRAM_VER_REG);
+
+	/* deactivate the SOCID access again */
+	mmio_write_32(SRAM_VER_REG, reg & ~BIT(15));
+
+	return reg >> 16;
+}
diff --git a/plat/allwinner/common/sunxi_private.h b/plat/allwinner/common/sunxi_private.h
index b9f0fb4..e45f494 100644
--- a/plat/allwinner/common/sunxi_private.h
+++ b/plat/allwinner/common/sunxi_private.h
@@ -12,6 +12,7 @@
 void sunxi_cpu_on(unsigned int cluster, unsigned int core);
 void sunxi_disable_secondary_cpus(unsigned int primary_cpu);
 
+uint16_t sunxi_read_soc_id(void);
 void sunxi_security_setup(void);
 
 #endif /* __SUNXI_PRIVATE_H__ */