Cortex-Axx: Unconditionally apply CPU reset operations
In the Cortex-A35/A53/A57 CPUs library code, some of the CPU specific
reset operations are skipped if they have already been applied in a
previous invocation of the reset handler. This precaution is not
required, as all these operations can be reapplied safely.
This patch removes the unneeded test-before-set instructions in
the reset handler for these CPUs.
Change-Id: Ib175952c814dc51f1b5125f76ed6c06a22b95167
diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S
index 6a447c0..ba29d6d 100644
--- a/lib/cpus/aarch64/cortex_a35.S
+++ b/lib/cpus/aarch64/cortex_a35.S
@@ -67,16 +67,12 @@
*/
func cortex_a35_reset_func
/* ---------------------------------------------
- * As a bare minimum enable the SMP bit if it is
- * not already set.
+ * Enable the SMP bit.
* ---------------------------------------------
*/
mrs x0, CORTEX_A35_CPUECTLR_EL1
- tst x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
- b.ne skip_smp_setup
orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
msr CORTEX_A35_CPUECTLR_EL1, x0
-skip_smp_setup:
isb
ret
endfunc cortex_a35_reset_func
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 00ceadb..c33ba57 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -151,16 +151,12 @@
#endif
/* ---------------------------------------------
- * As a bare minimum enable the SMP bit if it is
- * not already set.
+ * Enable the SMP bit.
* ---------------------------------------------
*/
mrs x0, CPUECTLR_EL1
- tst x0, #CPUECTLR_SMP_BIT
- b.ne skip_smp_setup
orr x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0
-skip_smp_setup:
isb
ret x19
endfunc cortex_a53_reset_func
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 8bcb5dd..99db25b 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -105,17 +105,9 @@
ret
#endif
apply_806969:
- /*
- * Test if errata has already been applied in an earlier
- * invocation of the reset handler and does not need to
- * be applied again.
- */
mrs x1, CPUACTLR_EL1
- tst x1, #CPUACTLR_NO_ALLOC_WBWA
- b.ne skip_806969
orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA
msr CPUACTLR_EL1, x1
-skip_806969:
ret
endfunc errata_a57_806969_wa
@@ -139,17 +131,9 @@
ret
#endif
apply_813420:
- /*
- * Test if errata has already been applied in an earlier
- * invocation of the reset handler and does not need to
- * be applied again.
- */
mrs x1, CPUACTLR_EL1
- tst x1, #CPUACTLR_DCC_AS_DCCI
- b.ne skip_813420
orr x1, x1, #CPUACTLR_DCC_AS_DCCI
msr CPUACTLR_EL1, x1
-skip_813420:
ret
endfunc errata_a57_813420_wa
@@ -216,16 +200,12 @@
#endif
/* ---------------------------------------------
- * As a bare minimum enable the SMP bit if it is
- * not already set.
+ * Enable the SMP bit.
* ---------------------------------------------
*/
mrs x0, CPUECTLR_EL1
- tst x0, #CPUECTLR_SMP_BIT
- b.ne skip_smp_setup
orr x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0
-skip_smp_setup:
isb
ret x19
endfunc cortex_a57_reset_func