AMU: Implement context save/restore for aarch32
Add amu_context_save() and amu_context_restore() functions for aarch32
Change-Id: I4df83d447adeaa9d9f203e16dc5a919ffc04d87a
Signed-off-by: Joel Hutton <joel.hutton@arm.com>
diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c
index effc5bd..68cc4b3 100644
--- a/lib/extensions/amu/aarch32/amu.c
+++ b/lib/extensions/amu/aarch32/amu.c
@@ -5,6 +5,7 @@
*/
#include <amu.h>
+#include <amu_private.h>
#include <arch.h>
#include <arch_helpers.h>
#include <platform.h>
@@ -14,21 +15,26 @@
struct amu_ctx {
uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
+ uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
};
static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
-void amu_enable(int el2_unused)
+int amu_supported(void)
{
uint64_t features;
features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
- if ((features & ID_PFR0_AMU_MASK) != 1)
+ return (features & ID_PFR0_AMU_MASK) == 1;
+}
+
+void amu_enable(int el2_unused)
+{
+ if (!amu_supported())
return;
if (el2_unused) {
uint64_t v;
-
/*
* Non-secure access from EL0 or EL1 to the Activity Monitor
* registers do not trap to EL2.
@@ -40,15 +46,64 @@
/* Enable group 0 counters */
write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
+
+ /* Enable group 1 counters */
+ write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
+}
+
+/* Read the group 0 counter identified by the given `idx`. */
+uint64_t amu_group0_cnt_read(int idx)
+{
+ assert(amu_supported());
+ assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
+
+ return amu_group0_cnt_read_internal(idx);
+}
+
+/* Write the group 0 counter identified by the given `idx` with `val`. */
+void amu_group0_cnt_write(int idx, uint64_t val)
+{
+ assert(amu_supported());
+ assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS);
+
+ amu_group0_cnt_write_internal(idx, val);
+ isb();
+}
+
+/* Read the group 1 counter identified by the given `idx`. */
+uint64_t amu_group1_cnt_read(int idx)
+{
+ assert(amu_supported());
+ assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+
+ return amu_group1_cnt_read_internal(idx);
+}
+
+/* Write the group 1 counter identified by the given `idx` with `val`. */
+void amu_group1_cnt_write(int idx, uint64_t val)
+{
+ assert(amu_supported());
+ assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+
+ amu_group1_cnt_write_internal(idx, val);
+ isb();
+}
+
+void amu_group1_set_evtype(int idx, unsigned int val)
+{
+ assert(amu_supported());
+ assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS);
+
+ amu_group1_set_evtype_internal(idx, val);
+ isb();
}
static void *amu_context_save(const void *arg)
{
struct amu_ctx *ctx;
- uint64_t features;
+ int i;
- features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
- if ((features & ID_PFR0_AMU_MASK) != 1)
+ if (!amu_supported())
return (void *)-1;
ctx = &amu_ctxs[plat_my_core_pos()];
@@ -61,12 +116,14 @@
* counter values from the future via the memory mapped view.
*/
write_amcntenclr0(AMU_GROUP0_COUNTERS_MASK);
+ write_amcntenclr1(AMU_GROUP1_COUNTERS_MASK);
isb();
- ctx->group0_cnts[0] = read64_amevcntr00();
- ctx->group0_cnts[1] = read64_amevcntr01();
- ctx->group0_cnts[2] = read64_amevcntr02();
- ctx->group0_cnts[3] = read64_amevcntr03();
+ for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
+ ctx->group0_cnts[i] = amu_group0_cnt_read(i);
+
+ for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
+ ctx->group1_cnts[i] = amu_group1_cnt_read(i);
return 0;
}
@@ -75,6 +132,7 @@
{
struct amu_ctx *ctx;
uint64_t features;
+ int i;
features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
if ((features & ID_PFR0_AMU_MASK) != 1)
@@ -86,19 +144,16 @@
assert(read_amcntenset0() == 0);
/* Restore group 0 counters */
- if (AMU_GROUP0_COUNTERS_MASK & (1U << 0))
- write64_amevcntr00(ctx->group0_cnts[0]);
- if (AMU_GROUP0_COUNTERS_MASK & (1U << 1))
- write64_amevcntr01(ctx->group0_cnts[1]);
- if (AMU_GROUP0_COUNTERS_MASK & (1U << 2))
- write64_amevcntr02(ctx->group0_cnts[2]);
- if (AMU_GROUP0_COUNTERS_MASK & (1U << 3))
- write64_amevcntr03(ctx->group0_cnts[3]);
- isb();
+ for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++)
+ amu_group0_cnt_write(i, ctx->group0_cnts[i]);
+ for (i = 0; i < AMU_GROUP1_NR_COUNTERS; i++)
+ amu_group1_cnt_write(i, ctx->group1_cnts[i]);
/* Enable group 0 counters */
write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
+ /* Enable group 1 counters */
+ write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
return 0;
}