Create BL stage specific translation tables
This patch uses the IMAGE_BL<x> constants to create translation tables specific
to a boot loader stage. This allows each stage to create mappings only for areas
in the memory map that it needs.
Fixes ARM-software/tf-issues#209
Change-Id: Ie4861407ddf9317f0fb890fc7575eaa88d0de51c
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index a25c4f0..e393ced 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -36,6 +36,7 @@
#include <debug.h>
#include <mmio.h>
#include <platform.h>
+#include <platform_def.h>
#include <plat_config.h>
#include <xlat_tables.h>
#include "../fvp_def.h"
@@ -49,33 +50,70 @@
******************************************************************************/
plat_config_t plat_config;
+#define MAP_SHARED_RAM MAP_REGION_FLAT(FVP_SHARED_RAM_BASE, \
+ FVP_SHARED_RAM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
+ FLASH0_SIZE, \
+ MT_MEMORY | MT_RO | MT_SECURE)
+
+#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
+ DEVICE0_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
+ DEVICE1_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_DRAM1 MAP_REGION_FLAT(DRAM1_BASE, \
+ DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define MAP_TSP_SEC_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
+ TSP_SEC_MEM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
/*
- * Table of regions to map using the MMU.
+ * Table of regions for various BL stages to map using the MMU.
* This doesn't include TZRAM as the 'mem_layout' argument passed to
* configure_mmu_elx() will give the available subset of that,
*/
+#if IMAGE_BL1
const mmap_region_t fvp_mmap[] = {
- { FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_SIZE,
- MT_MEMORY | MT_RW | MT_SECURE },
- { FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_SIZE,
- MT_MEMORY | MT_RW | MT_SECURE },
- { FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE,
- MT_MEMORY | MT_RO | MT_SECURE },
- { FLASH1_BASE, FLASH1_BASE, FLASH1_SIZE,
- MT_MEMORY | MT_RO | MT_SECURE },
- { VRAM_BASE, VRAM_BASE, VRAM_SIZE,
- MT_MEMORY | MT_RW | MT_SECURE },
- { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE,
- MT_DEVICE | MT_RW | MT_SECURE },
- { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE,
- MT_DEVICE | MT_RW | MT_SECURE },
- /* 2nd GB as device for now...*/
- { 0x40000000, 0x40000000, 0x40000000,
- MT_DEVICE | MT_RW | MT_SECURE },
- { DRAM1_BASE, DRAM1_BASE, DRAM1_SIZE,
- MT_MEMORY | MT_RW | MT_NS },
+ MAP_SHARED_RAM,
+ MAP_FLASH0,
+ MAP_DEVICE0,
+ MAP_DEVICE1,
{0}
};
+#endif
+#if IMAGE_BL2
+const mmap_region_t fvp_mmap[] = {
+ MAP_SHARED_RAM,
+ MAP_FLASH0,
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ MAP_DRAM1,
+ MAP_TSP_SEC_MEM,
+ {0}
+};
+#endif
+#if IMAGE_BL31
+const mmap_region_t fvp_mmap[] = {
+ MAP_SHARED_RAM,
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ {0}
+};
+#endif
+#if IMAGE_BL32
+const mmap_region_t fvp_mmap[] = {
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ {0}
+};
+#endif
/* Array of secure interrupts to be configured by the gic driver */
const unsigned int irq_sec_array[] = {