diff --git a/plat/nvidia/tegra/common/tegra_fiq_glue.c b/plat/nvidia/tegra/common/tegra_fiq_glue.c
index b036690..60b5595 100644
--- a/plat/nvidia/tegra/common/tegra_fiq_glue.c
+++ b/plat/nvidia/tegra/common/tegra_fiq_glue.c
@@ -16,9 +16,15 @@
 #include <lib/el3_runtime/context_mgmt.h>
 #include <plat/common/platform.h>
 
+#if ENABLE_WDT_LEGACY_FIQ_HANDLING
+#include <flowctrl.h>
+#endif
 #include <tegra_def.h>
 #include <tegra_private.h>
 
+/* Legacy FIQ used by earlier Tegra platforms */
+#define LEGACY_FIQ_PPI_WDT		28U
+
 static DEFINE_BAKERY_LOCK(tegra_fiq_lock);
 
 /*******************************************************************************
@@ -79,6 +85,20 @@
 		cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr);
 	}
 
+#if ENABLE_WDT_LEGACY_FIQ_HANDLING
+	/*
+	 * Tegra platforms that use LEGACY_FIQ as the watchdog timer FIQ
+	 * need to issue an IPI to other CPUs, to allow them to handle
+	 * the "system hung" scenario. This interrupt is passed to the GICD
+	 * via the Flow Controller. So, once we receive this interrupt,
+	 * disable the routing so that we can mark it as "complete" in the
+	 * GIC later.
+	 */
+	if (irq == LEGACY_FIQ_PPI_WDT) {
+		tegra_fc_disable_fiq_to_ccplex_routing();
+	}
+#endif
+
 	/*
 	 * Mark this interrupt as complete to avoid a FIQ storm.
 	 */
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index e23d7e3..59077eb 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -22,6 +22,9 @@
 MAX_MMAP_REGIONS			:= 15
 $(eval $(call add_define,MAX_MMAP_REGIONS))
 
+ENABLE_WDT_LEGACY_FIQ_HANDLING		:= 1
+$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
+
 PLAT_INCLUDES		+=	-I${SOC_DIR}/drivers/se
 
 BL31_SOURCES		+=	drivers/ti/uart/aarch64/16550_console.S		\