plat/arm: Restrict PIE support to FVP
The patch SHA 55cf015c enabled PIE support when RESET_TO_BL31=1 for
all ARM platforms. But it seems n1sdp platform doesn't work with PIE
support yet. Hence restrict the ENABLE_PIE=1 to fvp platform.
Change-Id: If44e42528e4b0b57c69084503f346576fe0748bd
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index c63fddb..4e9c70a 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -405,16 +405,21 @@
#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
PLAT_ARM_MAX_BL31_SIZE)
#elif (RESET_TO_BL31)
-/* Ensure Position Independent support (PIE) is enabled for this config.*/
-# if !ENABLE_PIE
-# error "BL31 must be a PIE if RESET_TO_BL31=1."
-# endif
+
+# if ENABLE_PIE
/*
* Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
- * used for building BL31 when RESET_TO_BL31=1.
+ * used for building BL31 and not used for loading BL31.
*/
-#define BL31_BASE 0x0
-#define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
+# define BL31_BASE 0x0
+# define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
+# else
+/* Put BL31_BASE in the middle of the Trusted SRAM.*/
+# define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \
+ (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
+# define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+# endif /* ENABLE_PIE */
+
#else
/* Put BL31 below BL2 in the Trusted SRAM.*/
#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\