Add support for BL3-1 as a reset vector
This change adds optional reset vector support to BL3-1
which means BL3-1 entry point can detect cold/warm boot,
initialise primary cpu, set up cci and mail box.
When using BL3-1 as a reset vector it is assumed that
the BL3-1 platform code can determine the location of
the BL3-2 images, or load them as there are no parameters
that can be passed to BL3-1 at reset.
It also fixes the incorrect initialisation of mailbox
registers on the FVP platform
This feature can be enabled by building the code with
make variable RESET_TO_BL31 set as 1
Fixes ARM-software/TF-issues#133
Fixes ARM-software/TF-issues#20
Change-Id: I4e23939b1c518614b899f549f1e8d412538ee570
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index c67d029..f582e76 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -50,8 +50,28 @@
* specific structure
* ---------------------------------------------------------------
*/
+#if !RESET_TO_BL31
mov x20, x0
mov x21, x1
+#else
+
+ /* -----------------------------------------------------
+ * Perform any processor specific actions upon reset
+ * e.g. cache, tlb invalidations etc. Override the
+ * Boot ROM(BL0) programming sequence
+ * -----------------------------------------------------
+ */
+ bl cpu_reset_handler
+#endif
+
+ /* ---------------------------------------------
+ * Enable the instruction cache.
+ * ---------------------------------------------
+ */
+ mrs x1, sctlr_el3
+ orr x1, x1, #SCTLR_I_BIT
+ msr sctlr_el3, x1
+ isb
/* ---------------------------------------------
* Set the exception vector to something sane.
@@ -83,15 +103,10 @@
bic w1, w1, #TFP_BIT
msr cptr_el3, x1
- /* ---------------------------------------------
- * Enable the instruction cache.
- * ---------------------------------------------
- */
- mrs x1, sctlr_el3
- orr x1, x1, #SCTLR_I_BIT
- msr sctlr_el3, x1
- isb
-
+#if RESET_TO_BL31
+ wait_for_entrypoint
+ bl platform_mem_init
+#else
/* ---------------------------------------------
* This is BL31 which is expected to be executed
* only by the primary cpu (at least for now).
@@ -101,6 +116,7 @@
mrs x0, mpidr_el1
bl platform_is_primary_cpu
cbz x0, _panic
+#endif
/* ---------------------------------------------
* Zero out NOBITS sections. There are 2 of them:
@@ -134,8 +150,14 @@
* Perform platform specific early arch. setup
* ---------------------------------------------
*/
+#if RESET_TO_BL31
+ mov x0, 0
+ mov x1, 0
+#else
mov x0, x20
mov x1, x21
+#endif
+
bl bl31_early_platform_setup
bl bl31_plat_arch_setup
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index c0dc2fd..6c9650f 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -37,6 +37,7 @@
bl31/aarch64/runtime_exceptions.S \
bl31/aarch64/crash_reporting.S \
common/aarch64/early_exceptions.S \
+ lib/aarch64/cpu_helpers.S \
lib/locks/bakery/bakery_lock.c \
lib/locks/exclusive/spinlock.S \
services/std_svc/std_svc_setup.c \