diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index c67d029..f582e76 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -50,8 +50,28 @@
 	 * specific structure
 	 * ---------------------------------------------------------------
 	 */
+#if !RESET_TO_BL31
 	mov	x20, x0
 	mov	x21, x1
+#else
+
+	/* -----------------------------------------------------
+	 * Perform any processor specific actions upon reset
+	 * e.g. cache, tlb invalidations etc. Override the
+	 * Boot ROM(BL0) programming sequence
+	 * -----------------------------------------------------
+	 */
+	bl	cpu_reset_handler
+#endif
+
+	/* ---------------------------------------------
+	 * Enable the instruction cache.
+	 * ---------------------------------------------
+	 */
+	mrs	x1, sctlr_el3
+	orr	x1, x1, #SCTLR_I_BIT
+	msr	sctlr_el3, x1
+	isb
 
 	/* ---------------------------------------------
 	 * Set the exception vector to something sane.
@@ -83,15 +103,10 @@
 	bic	w1, w1, #TFP_BIT
 	msr	cptr_el3, x1
 
-	/* ---------------------------------------------
-	 * Enable the instruction cache.
-	 * ---------------------------------------------
-	 */
-	mrs	x1, sctlr_el3
-	orr	x1, x1, #SCTLR_I_BIT
-	msr	sctlr_el3, x1
-	isb
-
+#if RESET_TO_BL31
+	wait_for_entrypoint
+	bl	platform_mem_init
+#else
 	/* ---------------------------------------------
 	 * This is BL31 which is expected to be executed
 	 * only by the primary cpu (at least for now).
@@ -101,6 +116,7 @@
 	mrs	x0, mpidr_el1
 	bl	platform_is_primary_cpu
 	cbz	x0, _panic
+#endif
 
 	/* ---------------------------------------------
 	 * Zero out NOBITS sections. There are 2 of them:
@@ -134,8 +150,14 @@
 	 * Perform platform specific early arch. setup
 	 * ---------------------------------------------
 	 */
+#if RESET_TO_BL31
+	mov	x0, 0
+	mov	x1, 0
+#else
 	mov	x0, x20
 	mov	x1, x21
+#endif
+
 	bl	bl31_early_platform_setup
 	bl	bl31_plat_arch_setup