| commit | dc402531eff62ca54c3f9f360be50c1c113d16f9 | [log] [tgz] |
|---|---|---|
| author | Grzegorz Jaszczyk <jaz@semihalf.com> | Thu Dec 20 17:13:19 2018 +0100 |
| committer | Marcin Wojtas <mw@semihalf.com> | Sun Jun 07 00:06:03 2020 +0200 |
| tree | 614e1bf401628018f9a16eb6589bcba6b5600e8c | |
| parent | 613bbde09e48874658af5a00612fe2a0b0388523 [diff] [blame] |
plat: marvell: add support for PLL 2.2GHz mode Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
diff --git a/drivers/marvell/ap807_clocks_init.c b/drivers/marvell/ap807_clocks_init.c index 04c256b..5604453 100644 --- a/drivers/marvell/ap807_clocks_init.c +++ b/drivers/marvell/ap807_clocks_init.c
@@ -96,6 +96,11 @@ case CPU_2000_DDR_1200_RCLK_1200: pll_set_freq(PLL_FREQ_2000); break; +#ifdef MVEBU_SOC_AP807 + case CPU_2200_DDR_1200_RCLK_1200: + pll_set_freq(PLL_FREQ_2200); + break; +#endif default: break; }