diff --git a/plat/imx/common/imx_clock.c b/plat/imx/common/imx_clock.c
index 929cf8d..8fb42e3 100644
--- a/plat/imx/common/imx_clock.c
+++ b/plat/imx/common/imx_clock.c
@@ -50,3 +50,35 @@
 
 	mmio_write_32(addr, CCM_CCGR_SETTING0_DOM_CLK_ALWAYS);
 }
+
+void imx_clock_enable_uart(unsigned int uart_id, uint32_t uart_clk_en_bits)
+{
+	unsigned int ccm_trgt_id = CCM_TRT_ID_UART1_CLK_ROOT + uart_id;
+	unsigned int ccm_ccgr_id = CCM_CCGR_ID_UART1 + uart_id;
+
+	/* Check for error */
+	if (uart_id > MXC_MAX_UART_NUM)
+		return;
+
+	/* Set target register values */
+	imx_clock_target_set(ccm_trgt_id, uart_clk_en_bits);
+
+	/* Enable the clock gate */
+	imx_clock_gate_enable(ccm_ccgr_id, true);
+}
+
+void imx_clock_disable_uart(unsigned int uart_id)
+{
+	unsigned int ccm_trgt_id = CCM_TRT_ID_UART1_CLK_ROOT + uart_id;
+	unsigned int ccm_ccgr_id = CCM_CCGR_ID_UART1 + uart_id;
+
+	/* Check for error */
+	if (uart_id > MXC_MAX_UART_NUM)
+		return;
+
+	/* Disable the clock gate */
+	imx_clock_gate_enable(ccm_ccgr_id, false);
+
+	/* Clear the target */
+	imx_clock_target_clr(ccm_trgt_id, 0xFFFFFFFF);
+}