commit | dd6efc9ea52e9dbfaeacbb439abbc0f8ecddd89c | [log] [tgz] |
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author | Manish Pandey <manish.pandey2@arm.com> | Fri Apr 30 12:23:04 2021 +0200 |
committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | Fri Apr 30 12:23:04 2021 +0200 |
tree | 56eaafebb56112c237f6e44ea48bacab15f14b9e | |
parent | 674803667e9c4774af2f5c85a1d4cc96ef3cc005 [diff] | |
parent | 3dd87efb2e63249c7896dcae5324e1303bfc7b40 [diff] |
Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration * changes: plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0 plat: ti: k3: board: Lets cast our macros plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing plat: ti: k3: platform_def.h: Define the correct number of max table entries plat: ti: k3: board: lite: Increase SRAM size to account for additional table