Merge changes from topic "certtool-memleak" into integration
* changes:
Use preallocated parts of the HASH struct
Free arguments copied with strdup
Free keys after use
Free X509_EXTENSIONs
diff --git a/.editorconfig b/.editorconfig
index f523ca1..12f786d 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -38,10 +38,10 @@
insert_final_newline = true
# [LCS] Chapter 2: Breaking long lines and strings
-# "The limit on the length of lines is 80 columns"
+# "The limit on the length of lines is 100 columns"
# This is a "soft" requirement for Arm-TF, and should not be the sole
# reason for changes.
-max_line_length = 80
+max_line_length = 100
# [LCS] Chapter 1: Indentation
# "Tabs are 8 characters"
diff --git a/Makefile b/Makefile
index c5073e0..2d5a5bb 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
# Trusted Firmware Version
#
VERSION_MAJOR := 2
-VERSION_MINOR := 3
+VERSION_MINOR := 4
# Default goal is build all images
.DEFAULT_GOAL := all
@@ -185,13 +185,14 @@
else
target32-directive = -target armv8a-none-eabi
-# Set the compiler's target architecture profile based on ARM_ARCH_MINOR option
+# Set the compiler's target architecture profile based on
+# ARM_ARCH_MAJOR ARM_ARCH_MINOR options
ifeq (${ARM_ARCH_MINOR},0)
-march32-directive = -march=armv8-a
-march64-directive = -march=armv8-a
+march32-directive = -march=armv${ARM_ARCH_MAJOR}-a
+march64-directive = -march=armv${ARM_ARCH_MAJOR}-a
else
-march32-directive = -march=armv8.${ARM_ARCH_MINOR}-a
-march64-directive = -march=armv8.${ARM_ARCH_MINOR}-a
+march32-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a
+march64-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a
endif
endif
@@ -203,23 +204,43 @@
endif
endif
-# Enabled required option for memory stack tagging. Currently, these options are
-# enabled only for clang and armclang compiler.
+# Get architecture feature modifiers
+arch-features = ${ARM_ARCH_FEATURE}
+
+# Enable required options for memory stack tagging.
+# Currently, these options are enabled only for clang and armclang compiler.
ifeq (${SUPPORT_STACK_MEMTAG},yes)
ifdef mem_tag_arch_support
+# Check for armclang and clang compilers
ifneq ( ,$(filter $(notdir $(CC)),armclang clang))
-march64-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a+memtag
+# Add "memtag" architecture feature modifier if not specified
+ifeq ( ,$(findstring memtag,$(arch-features)))
+arch-features := $(arch-features)+memtag
+endif # memtag
ifeq ($(notdir $(CC)),armclang)
TF_CFLAGS += -mmemtag-stack
else ifeq ($(notdir $(CC)),clang)
TF_CFLAGS += -fsanitize=memtag
-endif
-endif
+endif # armclang
+endif # armclang clang
else
$(error "Error: stack memory tagging is not supported for architecture \
${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
+endif # mem_tag_arch_support
+endif # SUPPORT_STACK_MEMTAG
+
+# Set the compiler's architecture feature modifiers
+ifneq ($(arch-features), none)
+# Strip "none+" from arch-features
+arch-features := $(subst none+,,$(arch-features))
+ifeq ($(ARCH), aarch32)
+march32-directive := $(march32-directive)+$(arch-features)
+else
+march64-directive := $(march64-directive)+$(arch-features)
endif
-endif
+# Print features
+$(info Arm Architecture Features specified: $(subst +, ,$(arch-features)))
+endif # arch-features
ifneq ($(findstring armclang,$(notdir $(CC))),)
TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
@@ -865,7 +886,9 @@
CTX_INCLUDE_PAUTH_REGS \
CTX_INCLUDE_MTE_REGS \
CTX_INCLUDE_EL2_REGS \
+ CTX_INCLUDE_NEVE_REGS \
DEBUG \
+ DISABLE_MTPMU \
DYN_DISABLE_AUTH \
EL3_EXCEPTION_HANDLING \
ENABLE_AMU \
@@ -953,7 +976,9 @@
EL3_EXCEPTION_HANDLING \
CTX_INCLUDE_MTE_REGS \
CTX_INCLUDE_EL2_REGS \
+ CTX_INCLUDE_NEVE_REGS \
DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
+ DISABLE_MTPMU \
ENABLE_AMU \
ENABLE_ASSERTIONS \
ENABLE_BTI \
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index b839990..d11b4ab 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -16,6 +16,10 @@
plat/common/${ARCH}/platform_up_stack.S \
${MBEDTLS_SOURCES}
+ifeq (${DISABLE_MTPMU},1)
+BL1_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S
+endif
+
ifeq (${ARCH},aarch64)
BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \
lib/el3_runtime/aarch64/context.S
diff --git a/bl2/bl2.mk b/bl2/bl2.mk
index 6dc0f18..735e7e0 100644
--- a/bl2/bl2.mk
+++ b/bl2/bl2.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -25,6 +25,10 @@
lib/cpus/${ARCH}/cpu_helpers.S \
lib/cpus/errata_report.c
+ifeq (${DISABLE_MTPMU},1)
+BL2_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S
+endif
+
ifeq (${ARCH},aarch64)
BL2_SOURCES += lib/cpus/aarch64/dsu_helpers.S
endif
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index cd6549b..e299fe1 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -40,6 +40,9 @@
${SPMD_SOURCES} \
${SPM_SOURCES}
+ifeq (${DISABLE_MTPMU},1)
+BL31_SOURCES += lib/extensions/mtpmu/aarch64/mtpmu.S
+endif
ifeq (${ENABLE_PMF}, 1)
BL31_SOURCES += lib/pmf/pmf_main.c
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index 6233299..afd7ae1 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -19,6 +19,10 @@
services/std_svc/std_svc_setup.c \
${PSCI_LIB_SOURCES}
+ifeq (${DISABLE_MTPMU},1)
+BL32_SOURCES += lib/extensions/mtpmu/aarch32/mtpmu.S
+endif
+
ifeq (${ENABLE_PMF}, 1)
BL32_SOURCES += lib/pmf/pmf_main.c
endif
diff --git a/bl32/tsp/aarch64/tsp_request.S b/bl32/tsp/aarch64/tsp_request.S
index 5ad16da..6e238ea 100644
--- a/bl32/tsp/aarch64/tsp_request.S
+++ b/bl32/tsp/aarch64/tsp_request.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,28 +9,19 @@
.globl tsp_get_magic
-
/*
* This function raises an SMC to retrieve arguments from secure
* monitor/dispatcher, saves the returned arguments the array received in x0,
* and then returns to the caller
*/
func tsp_get_magic
- /* Save address to stack */
- stp x0, xzr, [sp, #-16]!
-
/* Load arguments */
ldr w0, _tsp_fid_get_magic
/* Raise SMC */
smc #0
- /* Restore address from stack */
- ldp x4, xzr, [sp], #16
-
- /* Store returned arguments to the array */
- stp x0, x1, [x4, #0]
-
+ /* Return arguments in x1:x0 */
ret
endfunc tsp_get_magic
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index e947838..01c9ec5 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -363,8 +363,10 @@
uint64_t arg6,
uint64_t arg7)
{
+ uint128_t service_args;
+ uint64_t service_arg0;
+ uint64_t service_arg1;
uint64_t results[2];
- uint64_t service_args[2];
uint32_t linear_id = plat_my_core_pos();
/* Update this cpu's statistics */
@@ -387,10 +389,12 @@
results[1] = arg2;
/*
- * Request a service back from dispatcher/secure monitor. This call
- * return and thereafter resume execution
+ * Request a service back from dispatcher/secure monitor.
+ * This call returns and thereafter resumes execution.
*/
- tsp_get_magic(service_args);
+ service_args = tsp_get_magic();
+ service_arg0 = (uint64_t)service_args;
+ service_arg1 = (uint64_t)(service_args >> 64U);
#if CTX_INCLUDE_MTE_REGS
/*
@@ -403,20 +407,20 @@
/* Determine the function to perform based on the function ID */
switch (TSP_BARE_FID(func)) {
case TSP_ADD:
- results[0] += service_args[0];
- results[1] += service_args[1];
+ results[0] += service_arg0;
+ results[1] += service_arg1;
break;
case TSP_SUB:
- results[0] -= service_args[0];
- results[1] -= service_args[1];
+ results[0] -= service_arg0;
+ results[1] -= service_arg1;
break;
case TSP_MUL:
- results[0] *= service_args[0];
- results[1] *= service_args[1];
+ results[0] *= service_arg0;
+ results[1] *= service_arg1;
break;
case TSP_DIV:
- results[0] /= service_args[0] ? service_args[0] : 1;
- results[1] /= service_args[1] ? service_args[1] : 1;
+ results[0] /= service_arg0 ? service_arg0 : 1;
+ results[1] /= service_arg1 ? service_arg1 : 1;
break;
default:
break;
diff --git a/bl32/tsp/tsp_private.h b/bl32/tsp/tsp_private.h
index cbd527f..38d9732 100644
--- a/bl32/tsp/tsp_private.h
+++ b/bl32/tsp/tsp_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -61,7 +61,7 @@
*/
CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch);
-void tsp_get_magic(uint64_t args[4]);
+uint128_t tsp_get_magic(void);
tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
uint64_t arg1,
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index ab2d3f9..91a5621 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -516,8 +516,8 @@
Texas Instruments platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Andrew F. Davis <afd@ti.com>
-:G: `glneo`_
+:M: Nishanth Menon <nm@ti.com>
+:G: `nmenon`_
:F: docs/plat/ti-k3.rst
:F: plat/ti/
@@ -529,8 +529,10 @@
Xilinx platform port
^^^^^^^^^^^^^^^^^^^^
-:M: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
-:G: `sivadur`_
+:M: Michal Simek <michal.simek@xilinx.com>
+:G: `michalsimek`_
+:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
+:G: `venkatesh`_
:F: docs/plat/xilinx-zynqmp.rst
:F: plat/xilinx/
@@ -614,6 +616,7 @@
.. _ldts: https://github.com/ldts
.. _marex: https://github.com/marex
.. _masahir0y: https://github.com/masahir0y
+.. _michalsimek: https://github.com/michalsimek
.. _mmind: https://github.com/mmind
.. _mtk09422: https://github.com/mtk09422
.. _niej: https://github.com/niej
@@ -624,13 +627,13 @@
.. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
.. _sgorecha: https://github.com/sgorecha
.. _shawnguo2: https://github.com/shawnguo2
-.. _sivadur: https://github.com/sivadur
.. _smaeul: https://github.com/smaeul
.. _soby-mathew: https://github.com/soby-mathew
.. _thloh85-intel: https://github.com/thloh85-intel
.. _thomas-arm: https://github.com/thomas-arm
.. _TonyXie06: https://github.com/TonyXie06
.. _vwadekar: https://github.com/vwadekar
+.. _venkatesh: https://github.com/vabbarap
.. _Yann-lms: https://github.com/Yann-lms
.. _manish-pandey-arm: https://github.com/manish-pandey-arm
.. _mardyk01: https://github.com/mardyk01
@@ -648,5 +651,6 @@
.. _john-powell-arm: https://github.com/john-powell-arm
.. _raghuncstate: https://github.com/raghuncstate
.. _CJKay: https://github.com/cjkay
+.. _nmenon: https://github.com/nmenon
.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 7befba4..3b8f836 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -4,6 +4,560 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
+Version 2.4
+-----------
+
+New Features
+^^^^^^^^^^^^
+
+- Architecture support
+ - Armv8.6-A
+ - Added support for Armv8.6 Enhanced Counter Virtualization (ECV)
+ - Added support for Armv8.6 Fine Grained Traps (FGT)
+ - Added support for Armv8.6 WFE trap delays
+
+- Bootloader images
+ - Added support for Measured Boot
+
+- Build System
+ - Added build option ``COT_DESC_IN_DTB`` to create Chain of Trust at runtime
+ - Added build option ``OPENSSL_DIR`` to direct tools to OpenSSL libraries
+ - Added build option ``RAS_TRAP_LOWER_EL_ERR_ACCESS`` to enable trapping RAS
+ register accesses from EL1/EL2 to EL3
+ - Extended build option ``BRANCH_PROTECTION`` to support branch target
+ identification
+
+- Common components
+ - Added support for exporting CPU nodes to the device tree
+ - Added support for single and dual-root Chains of Trust in secure
+ partitions
+
+- Drivers
+ - Added Broadcom RNG driver
+ - Added Marvell ``mg_conf_cm3`` driver
+ - Added System Control and Management Interface (SCMI) driver
+ - Added STMicroelectronics ETZPC driver
+
+ - Arm GICv3
+ - Added support for detecting topology at runtime
+
+ - Dual Root
+ - Added support for platform certificates
+
+ - Marvell Cache LLC
+ - Added support for mapping the entire LLC into SRAM
+
+ - Marvell CCU
+ - Added workaround for erratum 3033912
+
+ - Marvell CP110 COMPHY
+ - Added support for SATA COMPHY polarity inversion
+ - Added support for USB COMPHY polarity inversion
+ - Added workaround for erratum IPCE_COMPHY-1353
+
+ - STM32MP1 Clocks
+ - Added ``RTC`` as a gateable clock
+ - Added support for shifted clock selector bit masks
+ - Added support for using additional clocks as parents
+
+- Libraries
+ - C standard library
+ - Added support for hexadecimal and pointer format specifiers in
+ ``snprint()``
+ - Added assembly alternatives for various library functions
+
+ - CPU support
+ - Arm Cortex-A53
+ - Added workaround for erratum 1530924
+
+ - Arm Cortex-A55
+ - Added workaround for erratum 1530923
+
+ - Arm Cortex-A57
+ - Added workaround for erratum 1319537
+
+ - Arm Cortex-A76
+ - Added workaround for erratum 1165522
+ - Added workaround for erratum 1791580
+ - Added workaround for erratum 1868343
+
+ - Arm Cortex-A72
+ - Added workaround for erratum 1319367
+
+ - Arm Cortex-A77
+ - Added workaround for erratum 1508412
+ - Added workaround for erratum 1800714
+ - Added workaround for erratum 1925769
+
+ - Arm Neoverse N1
+ - Added workaround for erratum 1868343
+
+ - EL3 Runtime
+ - Added support for saving/restoring registers related to nested
+ virtualization in EL2 context switches if the architecture supports it
+
+ - FCONF
+ - Added support for Measured Boot
+ - Added support for populating Chain of Trust properties
+ - Added support for loading the ``fw_config`` image
+
+ - Measured Boot
+ - Added support for event logging
+
+- Platforms
+ - Added support for Arm Morello
+ - Added support for Arm TC0
+ - Added support for iEi PUZZLE-M801
+ - Added support for Marvell OCTEON TX2 T9130
+ - Added support for MediaTek MT8192
+ - Added support for NXP i.MX 8M Nano
+ - Added support for NXP i.MX 8M Plus
+ - Added support for QTI CHIP SC7180
+ - Added support for STM32MP151F
+ - Added support for STM32MP153F
+ - Added support for STM32MP157F
+ - Added support for STM32MP151D
+ - Added support for STM32MP153D
+ - Added support for STM32MP157D
+
+ - Arm
+ - Added support for platform-owned SPs
+ - Added support for resetting to BL31
+
+ - Arm FPGA
+ - Added support for Klein
+ - Added support for Matterhorn
+ - Added support for additional CPU clusters
+
+ - Arm FVP
+ - Added support for performing SDEI platform setup at runtime
+ - Added support for SMCCC's ``SMCCC_ARCH_SOC_ID`` command
+ - Added an ``id`` field under the NV-counter node in the device tree to
+ differentiate between trusted and non-trusted NV-counters
+ - Added support for extracting the clock frequency from the timer node
+ in the device tree
+
+ - Arm Juno
+ - Added support for SMCCC's ``SMCCC_ARCH_SOC_ID`` command
+
+ - Arm N1SDP
+ - Added support for cross-chip PCI-e
+
+ - Marvell
+ - Added support for AVS reduction
+
+ - Marvell ARMADA
+ - Added support for twin-die combined memory device
+
+ - Marvell ARMADA A8K
+ - Added support for DDR with 32-bit bus width (both ECC and non-ECC)
+
+ - Marvell AP806
+ - Added workaround for erratum FE-4265711
+
+ - Marvell AP807
+ - Added workaround for erratum 3033912
+
+ - Nvidia Tegra
+ - Added debug printouts indicating SC7 entry sequence completion
+ - Added support for SDEI
+ - Added support for stack protection
+ - Added support for GICv3
+ - Added support for SMCCC's ``SMCCC_ARCH_SOC_ID`` command
+
+ - Nvidia Tegra194
+ - Added support for RAS exception handling
+ - Added support for SPM
+
+ - NXP i.MX
+ - Added support for SDEI
+
+ - QEMU SBSA
+ - Added support for the Secure Partition Manager
+
+ - QTI
+ - Added RNG driver
+ - Added SPMI PMIC arbitrator driver
+ - Added support for SMCCC's ``SMCCC_ARCH_SOC_ID`` command
+
+ - STM32MP1
+ - Added support for exposing peripheral interfaces to the non-secure
+ world at runtime
+ - Added support for SCMI clock and reset services
+ - Added support for STM32MP15x CPU revision Z
+ - Added support for SMCCC services in ``SP_MIN``
+
+- Services
+ - Secure Payload Dispatcher
+ - Added a provision to allow clients to retrieve the service UUID
+
+ - SPMC
+ - Added secondary core endpoint information to the SPMC context
+ structure
+
+ - SPMD
+ - Added support for booting OP-TEE as a guest S-EL1 Secure Partition on
+ top of Hafnium in S-EL2
+ - Added a provision for handling SPMC messages to register secondary
+ core entry points
+ - Added support for power management operations
+
+- Tools
+ - CertCreate
+ - Added support for secure partitions
+
+ - CertTool
+ - Added support for the ``fw_config`` image
+
+ - FIPTool
+ - Added support for the ``fw_config`` image
+
+Changed
+^^^^^^^
+
+- Architecture support
+
+- Bootloader images
+
+- Build System
+ - The top-level Makefile now supports building FipTool on Windows
+ - The default value of ``KEY_SIZE`` has been changed to to 2048 when RSA is
+ in use
+ - The previously-deprecated macro ``__ASSEMBLY__`` has now been removed
+
+- Common components
+ - Certain functions that flush the console will no longer return error
+ information
+
+- Drivers
+ - Arm GIC
+ - Usage of ``drivers/arm/gic/common/gic_common.c`` has now been
+ deprecated in favour of ``drivers/arm/gic/vX/gicvX.mk``
+ - Added support for detecting the presence of a GIC600-AE
+ - Added support for detecting the presence of a GIC-Clayton
+
+ - Marvell MCI
+ - Now performs link tuning for all MCI interfaces to improve performance
+
+ - Marvell MoChi
+ - PIDI masters are no longer forced into a non-secure access level when
+ ``LLC_SRAM`` is enabled
+ - The SD/MMC controllers are now accessible from guest virtual machines
+
+ - Mbed TLS
+ - Migrated to Mbed TLS v2.24.0
+
+ - STM32 FMC2 NAND
+ - Adjusted FMC node bindings to include an EBI controller node
+
+ - STM32 Reset
+ - Added an optional timeout argument to assertion functions
+
+ - STM32MP1 Clocks
+ - Enabled several additional system clocks during initialization
+
+- Libraries
+ - C Standard Library
+ - Improved ``memset`` performance by avoiding single-byte writes
+ - Added optimized assembly variants of ``memset``
+
+ - CPU support
+ - Renamed Cortex-Hercules to Cortex-A78
+ - Renamed Cortex-Hercules AE to Cortex-A78 AE
+ - Renamed Neoverse Zeus to Neoverse V1
+
+ - Coreboot
+ - Updated ‘coreboot_get_memory_type’ API to take an extra argument as a
+ ’memory size’ that used to return a valid memory type.
+
+ - libfdt
+ - Updated to latest upstream version
+
+- Platforms
+ - Allwinner
+ - Disabled non-secure access to PRCM power control registers
+
+ - Arm
+ - ``BL32_BASE`` is now platform-dependent when ``SPD_spmd`` is enabled
+ - Added support for loading the Chain of Trust from the device tree
+ - The firmware update check is now executed only once
+ - NV-counter base addresses are now loaded from the device tree when
+ ``COT_DESC_IN_DTB`` is enabled
+ - Now loads and populates ``fw_config`` and ``tb_fw_config``
+ - FCONF population now occurs after caches have been enabled in order
+ to reduce boot times
+
+ - Arm Corstone-700
+ - Platform support has been split into both an FVP and an FPGA variant
+
+ - Arm FPGA
+ - DTB and BL33 load addresses have been given sensible default values
+ - Now reads generic timer counter frequency, GICD and GICR base
+ addresses, and UART address from DT
+ - Now treats the primary PL011 UART as an SBSA Generic UART
+
+ - Arm FVP
+ - Secure interrupt descriptions, UART parameters, clock frequencies and
+ GICv3 parameters are now queried through FCONF
+ - UART parameters are now queried through the device tree
+ - Added an owner field to Cactus secure partitions
+ - Increased the maximum size of BL2 when the Chain of Trust is loaded
+ from the device tree
+ - Reduces the maximum size of BL31
+ - The ``FVP_USE_SP804_TIMER`` and ``FVP_VE_USE_SP804_TIMER`` build
+ options have been removed in favour of a common ``USE_SP804_TIMER``
+ option
+ - Added a third Cactus partition to manifests
+ - Device tree nodes now store UUIDs in big-endian
+
+ - Arm Juno
+ - Increased the maximum size of BL2 when optimizations have not been
+ applied
+ - Reduced the maximum size of BL31 and BL32
+
+ - Marvell AP807
+ - Enabled snoop filters
+
+ - Marvell ARMADA A3K
+ - UART recovery images are now suffixed with ``.bin``
+
+ - Marvell ARMADA A8K
+ - Option ``BL31_CACHE_DISABLE`` is now disabled (``0``) by default
+
+ - Nvidia Tegra
+ - Added VPR resize supported check when processing video memory resize
+ requests
+ - Added SMMU verification to prevent potential issues caused by
+ undetected corruption of the SMMU configuration during boot
+ - The GIC CPU interface is now properly disabled after CPU off
+ - The GICv2 sources list and the ``BL31_SIZE`` definition have been made
+ platform-specific
+ - The SPE driver will no longer flush the console when writing
+ individual characters
+
+ - Nvidia Tegra194
+ - TZDRAM setup has been moved to platform-specific early boot handlers
+ - Increased verbosity of debug prints for RAS SErrors
+ - Support for powering down CPUs during CPU suspend has been removed
+ - Now verifies firewall settings before using resources
+
+ - TI K3
+ - The UART number has been made configurable through ``K3_USART``
+
+ - Rockchip RK3368
+ - The maximum number of memory map regions has been increased to 20
+
+ - Socionext Uniphier
+ - The maximum size of BL33 has been increased to support larger
+ bootloaders
+
+ - STM32
+ - Removed platform-specific DT functions in favour of using existing
+ generic alternatives
+
+ - STM32MP1
+ - Increased verbosity of exception reports in debug builds
+ - Device trees have been updated to align with the Linux kernel
+ - Now uses the ETZPC driver to configure secure-aware interfaces for
+ assignment to the non-secure world
+ - Finished good variants have been added to the board identifier
+ enumerations
+ - Non-secure access to clocks and reset domains now depends on their
+ state of registration
+ - NEON is now disabled in ``SP_MIN``
+ - The last page of ``SYSRAM`` is now used as SCMI shared memory
+ - Checks to verify platform compatibility have been added to verify that
+ an image is compatible with the chip ID of the running platform
+
+ - QEMU SBSA
+ - Removed support for Arm's Cortex-A53
+
+- Services
+ - Renamed SPCI to FF-A
+
+ - SPMD
+ - No longer forwards requests to the non-secure world when retrieving
+ partition information
+ - SPMC manifest size is now retrieved directly from SPMD instead of the
+ device tree
+ - The FF-A version handler now returns SPMD's version when the origin
+ of the call is secure, and SPMC's version when the origin of the call
+ is non-secure
+
+ - SPMC
+ - Updated the manifest to declare CPU nodes in descending order as per
+ the SPM (Hafnium) multicore requirement
+ - Updated the device tree to mark 2GB as device memory for the first
+ partition excluding trusted DRAM region (which is reserved for SPMC)
+ - Increased the number of EC contexts to the maximum number of PEs as
+ per the FF-A specification
+
+- Tools
+ - FIPTool
+ - Now returns ``0`` on ``help`` and ``help <command>``
+
+ - Marvell DoImage
+ - Updated Mbed TLS support to v2.8
+
+ - SPTool
+ - Now appends CertTool arguments
+
+Resolved Issues
+^^^^^^^^^^^^^^^
+
+- Bootloader images
+ - Fixed compilation errors for dual-root Chains of Trust caused by symbol
+ collision
+
+ - BL31
+ - Fixed compilation errors on platforms with fewer than 4 cores caused
+ by initialization code exceeding the end of the stacks
+ - Fixed compilation errors when building a position-independent image
+
+- Build System
+ - Fixed invalid empty version strings
+ - Fixed compilation errors on Windows caused by a non-portable architecture
+ revision comparison
+
+- Drivers
+ - Arm GIC
+ - Fixed spurious interrupts caused by a missing barrier
+
+ - STM32 Flexible Memory Controller 2 (FMC2) NAND driver
+ - Fixed runtime instability caused by incorrect error detection logic
+
+ - STM32MP1 Clock driver
+ - Fixed incorrectly-formatted log messages
+ - Fixed runtime instability caused by improper clock gating procedures
+
+ - STMicroelectronics Raw NAND driver
+ - Fixed runtime instability caused by incorrect unit conversion when
+ waiting for NAND readiness
+
+- Libraries
+ - AMU
+ - Fixed timeout errors caused by excess error logging
+
+ - EL3 Runtime
+ - Fixed runtime instability caused by improper register save/restore
+ routine in EL2
+
+ - FCONF
+ - Fixed failure to initialize GICv3 caused by overly-strict device tree
+ requirements
+
+ - Measured Boot
+ - Fixed driver errors caused by a missing default value for the
+ ``HASH_ALG`` build option
+
+ - SPE
+ - Fixed feature detection check that prevented CPUs supporting SVE from
+ detecting support for SPE in the non-secure world
+
+ - Translation Tables
+ - Fixed various MISRA-C 2012 static analysis violations
+
+- Platforms
+ - Allwinner A64
+ - Fixed USB issues on certain battery-powered device caused by
+ improperly activated USB power rail
+
+ - Arm
+ - Fixed compilation errors caused by increase in BL2 size
+ - Fixed compilation errors caused by missing Makefile dependencies to
+ generated files when building the FIP
+ - Fixed MISRA-C 2012 static analysis violations caused by unused
+ structures in include directives intended to be feature-gated
+
+ - Arm FPGA
+ - Fixed initialization issues caused by incorrect MPIDR topology mapping
+ logic
+
+ - Arm RD-N1-edge
+ - Fixed compilation errors caused by mismatched parentheses in Makefile
+
+ - Arm SGI
+ - Fixed crashes due to the flash memory used for cold reboot attack
+ protection not being mapped
+
+ - Intel Agilex
+ - Fixed initialization issues caused by several compounding bugs
+
+ - Marvell
+ - Fixed compilation warnings caused by multiple Makefile inclusions
+
+ - Marvell ARMADA A3K
+ - Fixed boot issue in debug builds caused by checks on the BL33 load
+ address that are not appropriate for this platform
+
+ - Nvidia Tegra
+ - Fixed incorrect delay timer reads
+ - Fixed spurious interrupts in the non-secure world during cold boot
+ caused by the arbitration bit in the memory controller not being
+ cleared
+ - Fixed faulty video memory resize sequence
+
+ - Nvidia Tegra194
+ - Fixed incorrect alignment of TZDRAM base address
+
+ - NXP iMX8M
+ - Fixed CPU hot-plug issues caused by race condition
+
+ - STM32MP1
+ - Fixed compilation errors in highly-parallel builds caused by incorrect
+ Makefile dependencies
+
+ - STM32MP157C-ED1
+ - Fixed initialization issues caused by missing device tree hash node
+
+ - Raspberry Pi 3
+ - Fixed compilation errors caused by incorrect dependency ordering in
+ Makefile
+
+ - Rockchip
+ - Fixed initialization issues caused by non-critical errors when parsing
+ FDT being treated as critical
+
+ - Rockchip RK3368
+ - Fixed runtime instability caused by incorrect CPUID shift value
+
+ - QEMU
+ - Fixed compilation errors caused by incorrect dependency ordering in
+ Makefile
+
+ - QEMU SBSA
+ - Fixed initialization issues caused by FDT exceeding reserved memory
+ size
+
+ - QTI
+ - Fixed compilation errors caused by inclusion of a non-existent file
+
+- Services
+ - FF-A (previously SPCI)
+ - Fixed SPMD aborts caused by incorrect behaviour when the manifest is
+ page-aligned
+
+- Tools
+ - Fixed compilation issues when compiling tools from within their respective
+ directories
+
+ - FIPTool
+ - Fixed command line parsing issues on Windows when using arguments
+ whose names also happen to be a subset of another's
+
+ - Marvell DoImage
+ - Fixed PKCS signature verification errors at boot on some platforms
+ caused by generation of misaligned images
+
+Known Issues
+^^^^^^^^^^^^
+
+- Platforms
+ - NVIDIA Tegra
+ - Signed comparison compiler warnings occurring in libfdt are currently
+ being worked around by disabling the warning for the platform until
+ the underlying issue is resolved in libfdt
+
Version 2.3
-----------
@@ -32,7 +586,7 @@
- Build System
- Add support for documentation build as a target in Makefile
- - Add ``COT`` build option to select the chain of trust to use when the
+ - Add ``COT`` build option to select the Chain of Trust to use when the
Trusted Boot feature is enabled (default: ``tbbr``).
- Added creation and injection of secure partition packages into the FIP.
diff --git a/docs/components/psa-ffa-manifest-binding.rst b/docs/components/psa-ffa-manifest-binding.rst
index 09894ae..af79074 100644
--- a/docs/components/psa-ffa-manifest-binding.rst
+++ b/docs/components/psa-ffa-manifest-binding.rst
@@ -13,7 +13,7 @@
- compatible [mandatory]
- value type: <string>
- Must be the string "arm,ffa-manifest-X.Y" which specifies the major and
- minor versions fo the device tree binding for the FFA manifest represented
+ minor versions of the device tree binding for the FFA manifest represented
by this node. The minor number is incremented if the binding changes in a
backwards compatible manner.
@@ -240,7 +240,7 @@
- exclusive-access
- value type: <empty>
- Presence of this field implies that this endpoint must be granted exclusive
- access and ownership of this devices's MMIO region.
+ access and ownership of this device's MMIO region.
--------------
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index c976b8b..7c142d1 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -241,9 +241,6 @@
- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
-- ``ERRATA_A76_1800710``: This applies errata 1800710 workaround to Cortex-A76
- CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
-
- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
limitation of errata framework this errata is applied to all revisions
@@ -252,14 +249,14 @@
- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76
+ CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
+
For Cortex-A77, the following errata build flags are defined :
- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
-- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
- CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
-
- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
@@ -268,6 +265,13 @@
- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
+- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
+ CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
+
+- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78
+ CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
+ issue but there is no workaround for that revision.
+
For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
@@ -306,6 +310,10 @@
- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
+ CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
+ revisions r0p0, r1p0, and r2p0 there is no workaround.
+
DSU Errata Workarounds
----------------------
@@ -369,10 +377,11 @@
Cortex-A57 based platform must make its own decision on whether to use
the optimization. This flag is disabled by default.
-- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
+- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
level cache(LLC) is present in the system, and that the DataSource field
on the master CHI interface indicates when data is returned from the LLC.
This is used to control how the LL_CACHE* PMU events count.
+ Default value is 0 (Disabled).
--------------
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 40fc5db..16de410 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -26,6 +26,12 @@
``aarch64`` or ``aarch32`` as values. By default, it is defined to
``aarch64``.
+- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies
+ one or more feature modifiers. This option has the form ``[no]feature+...``
+ and defaults to ``none``. It translates into compiler option
+ ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the
+ list of supported feature modifiers.
+
- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
*Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
@@ -161,6 +167,10 @@
registers to be included when saving and restoring the CPU context. Default
is 0.
+- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the
+ Armv8.4-NV registers to be saved/restored when entering/exiting an EL2
+ execution context. Default value is 0.
+
- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
registers to be included when saving and restoring the CPU context as
@@ -181,6 +191,11 @@
of the binary image. If set to 1, then only the ELF image is built.
0 is the default.
+- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented
+ (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms
+ that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU,
+ check the latest Arm ARM.
+
- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
Board Boot authentication at runtime. This option is meant to be enabled only
for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index 19e26e4..d063ec7 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -116,7 +116,7 @@
by ``plat/common/aarch64/platform_mp_stack.S`` and
``plat/common/aarch64/platform_up_stack.S``.
-- **define : CACHE_WRITEBACK_GRANULE**
+- **#define : CACHE_WRITEBACK_GRANULE**
Defines the size in bits of the largest cache line across all the cache
levels in the platform.
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index 2e50068..a1d2313 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -94,6 +94,10 @@
- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the
SPMC Core manifest. Valid when ``SPD=spmd`` is selected.
+- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in tb_fw_config
+ device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest
+ file name contains pattern optee_sp.
+
For a better understanding of these options, the Arm development platform memory
map is explained in the :ref:`Firmware Design`.
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index 3a13268..ea72962 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -49,7 +49,8 @@
- ``FVP_RD_E1_edge`` (Version 11.9 build 41)
- ``FVP_RD_N1_edge`` (Version 11.10 build 36)
- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36)
-- ``FVP_RD_Daniel`` (Version 11.10 build 36)
+- ``FVP_RD_Daniel`` (Version 11.13 build 10)
+- ``FVP_RD_N2`` (Version 11.13 build 10)
- ``FVP_TC0`` (Version 0.0 build 6114)
- ``Foundation_Platform``
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index 56b627b..2c2bd68 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -61,17 +61,17 @@
Defines the level of logging which will be purged to the default output port.
- LOG_LEVEL_NONE 0
- LOG_LEVEL_ERROR 10
- LOG_LEVEL_NOTICE 20
- LOG_LEVEL_WARNING 30
- LOG_LEVEL_INFO 40
- LOG_LEVEL_VERBOSE 50
+ - 0 - LOG_LEVEL_NONE
+ - 10 - LOG_LEVEL_ERROR
+ - 20 - LOG_LEVEL_NOTICE (default for DEBUG=0)
+ - 30 - LOG_LEVEL_WARNING
+ - 40 - LOG_LEVEL_INFO (default for DEBUG=1)
+ - 50 - LOG_LEVEL_VERBOSE
- USE_COHERENT_MEM
This flag determines whether to include the coherent memory region in the
- BL memory map or not.
+ BL memory map or not. Enabled by default.
- LLC_ENABLE
@@ -86,6 +86,20 @@
There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n.
Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y.
+- CM3_SYSTEM_RESET
+
+ For Armada37x0 only, when ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will
+ be used for system reset.
+ TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the
+ Cortex-M3 secure coprocessor.
+ The firmware running in the coprocessor must either implement this functionality or
+ ignore the 0x0009 command (which is true for the firmware from A3700-utils-marvell
+ repository). If this option is enabled but the firmware does not support this command,
+ an error message will be printed prior trying to reboot via the usual way.
+
+ This option is needed on Turris MOX as a workaround to a HW bug which causes reset to
+ sometime hang the board.
+
- MARVELL_SECURE_BOOT
Build trusted(=1)/non trusted(=0) image, default is non trusted.
@@ -122,24 +136,25 @@
For Armada37x0 only, the DDR topology map index/name, default is 0.
Supported Options:
- - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB)
- - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB)
- - DDR3 2CS (2): EspressoBIN V3-V5 (1GB)
- - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB)
- - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB)
- - DDR4 1CS (5): EspressoBin V7 (1GB)
- - DDR4 2CS (6): EspressoBin V7 (2GB)
- - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB
+ - 0 - DDR3 1CS: DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB)
+ - 1 - DDR4 1CS: DB-88F3720-DDR4-Modular (512MB)
+ - 2 - DDR3 2CS: EspressoBIN V3-V5 (1GB 2CS)
+ - 3 - DDR4 2CS: DB-88F3720-DDR4-Modular (4GB)
+ - 4 - DDR3 1CS: DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS)
+ - 5 - DDR4 1CS: EspressoBin V7 (1GB)
+ - 6 - DDR4 2CS: EspressoBin V7 (2GB)
+ - 7 - DDR3 2CS: EspressoBin V3-V5 (2GB)
+ - CUST - CUSTOMER: Customer board, DDR3 1CS 512MB
- CLOCKSPRESET
For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency,
default is CPU_800_DDR_800.
- - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
- - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
- - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
- - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
+ - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
+ - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
+ - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
+ - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
- BOOTDEV
@@ -175,33 +190,49 @@
- WTP
- For Armada37x0 only, use this parameter to point to wtptools source code
- directory, which can be found as a3700_utils.zip in the release. Usage
- example: ``WTP=/path/to/a3700_utils``
+ For Armada37x0 only, use this parameter to point to wtptools source code
+ directory, which can be found as a3700_utils.zip in the release. Usage
+ example: ``WTP=/path/to/a3700_utils``
- For example, in order to build the image in debug mode with log level up to 'notice' level run
+- CRYPTOPP_PATH
- .. code:: shell
+ For Armada37x0 only, use this parameter tp point to Crypto++ source code
+ directory, which is required for building WTP image tool.
- > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> all fip
- And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level,
- the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
- the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command
- line is as following
+For example, in order to build the image in debug mode with log level up to 'notice' level run
- .. code:: shell
+.. code:: shell
- > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \
- MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip
+ > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> mrvl_flash
- Supported MARVELL_PLATFORM are:
- - a3700 (for both A3720 DB and EspressoBin)
- - a70x0
- - a70x0_amc (for AMC board)
- - a80x0
- - a80x0_mcbin (for MacchiatoBin)
- - t9130 (OcteonTX2 CN913x)
+And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level,
+the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
+the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command
+line is as following
+
+.. code:: shell
+
+ > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \
+ MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \
+ MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \
+ CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \
+ all fip mrvl_bootimage mrvl_flash
+
+To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run following command:
+
+.. code:: shell
+
+ > make USE_COHERENT_MEM=0 PLAT=a3700 CM3_SYSTEM_RESET=1 BL33=/path/to/u-boot.bin \
+ CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
+
+Supported MARVELL_PLATFORM are:
+ - a3700 (for both A3720 DB and EspressoBin)
+ - a70x0
+ - a70x0_amc (for AMC board)
+ - a80x0
+ - a80x0_mcbin (for MacchiatoBin)
+ - t9130 (OcteonTX2 CN913x)
Special Build Flags
--------------------
@@ -223,7 +254,7 @@
Build output
------------
-Marvell's TF-A compilation generates 7 files:
+Marvell's TF-A compilation generates 8 files:
- ble.bin - BLe image
- bl1.bin - BL1 image
@@ -233,6 +264,12 @@
- boot-image.bin - TF-A image (contains BL1 and FIP images)
- flash-image.bin - Image which contains boot-image.bin and SPL image.
Should be placed on the boot flash/device.
+ - uart-images.tgz.bin - GZIPed TAR archive which contains Armada37x0 images
+ for booting via UART. Could be loaded via Marvell's WtpDownload tool from
+ A3700-utils-marvell repository.
+
+Additional make target ``mrvl_bootimage`` produce ``boot-image.bin`` file and target
+``mrvl_flash`` produce final ``flash-image.bin`` and ``uart-images.tgz.bin`` files.
Tools and external components installation
@@ -259,18 +296,23 @@
> export CROSS_CM3=/opt/arm-cross/bin/arm-linux-gnueabi
(2) DDR initialization library sources (mv_ddr) available at the following repository
- (use the "mv_ddr-armada-18.12" branch):
+ (use the "mv-ddr-devel" branch):
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
-(3) Armada3700 tools available at the following repository (use the latest release branch):
+(3) Armada3700 tools available at the following repository
+ (use the "A3700_utils-armada-18.12-fixed" branch):
https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
+(4) Crypto++ library available at the following repository:
+
+ https://github.com/weidai11/cryptopp.git
+
Armada70x0 and Armada80x0 Builds require installation of an additional component
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(1) DDR initialization library sources (mv_ddr) available at the following repository
- (use the "mv_ddr-armada-18.12" branch):
+ (use the "mv-ddr-devel" branch):
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
diff --git a/docs/process/code-review-guidelines.rst b/docs/process/code-review-guidelines.rst
new file mode 100644
index 0000000..67a211f
--- /dev/null
+++ b/docs/process/code-review-guidelines.rst
@@ -0,0 +1,216 @@
+Code Review Guidelines
+======================
+
+This document provides TF-A specific details about the project's code review
+process. It should be read in conjunction with the `Project Maintenance
+Process`_, which it supplements.
+
+
+Why do we do code reviews?
+--------------------------
+
+The main goal of code reviews is to improve the code quality. By reviewing each
+other's code, we can help catch issues that were missed by the author
+before they are integrated in the source tree. Different people bring different
+perspectives, depending on their past work, experiences and their current use
+cases of TF-A in their products.
+
+Code reviews also play a key role in sharing knowledge within the
+community. People with more expertise in one area of the code base can
+help those that are less familiar with it.
+
+Code reviews are meant to benefit everyone through team work. It is not about
+unfairly criticizing or belittling the work of any contributor.
+
+
+Good practices
+--------------
+
+To ensure the code review gives the greatest possible benefit, participants in
+the project should:
+
+- Be considerate of other people and their needs. Participants may be working
+ to different timescales, and have different priorities. Keep this in
+ mind - be gracious while waiting for action from others, and timely in your
+ actions when others are waiting for you.
+
+- Review other people's patches where possible. The more active reviewers there
+ are, the more quickly new patches can be reviewed and merged. Contributing to
+ code review helps everyone in the long run, as it creates a culture of
+ participation which serves everyone's interests.
+
+
+Guidelines for patch contributors
+---------------------------------
+
+In addition to the rules outlined in the :ref:`Contributor's Guide`, as a patch
+contributor you are expected to:
+
+- Answer all comments from people who took the time to review your
+ patches.
+
+- Be patient and resilient. It is quite common for patches to go through
+ several rounds of reviews and rework before they get approved, especially
+ for larger features.
+
+ In the event that a code review takes longer than you would hope for, you
+ may try the following actions to speed it up:
+
+ - Ping the reviewers on Gerrit or on the mailing list. If it is urgent,
+ explain why. Please remain courteous and do not abuse this.
+
+ - If one code owner has become unresponsive, ask the other code owners for
+ help progressing the patch.
+
+ - If there is only one code owner and they have become unresponsive, ask one
+ of the project maintainers for help.
+
+- Do the right thing for the project, not the fastest thing to get code merged.
+
+ For example, if some existing piece of code - say a driver - does not quite
+ meet your exact needs, go the extra mile and extend the code with the missing
+ functionality you require - as opposed to copying the code into some other
+ directory to have the freedom to change it in any way. This way, your changes
+ benefit everyone and will be maintained over time.
+
+
+Guidelines for all reviewers
+----------------------------
+
+There are no good or bad review comments. If you have any doubt about a patch or
+need some clarifications, it's better to ask rather than letting a potential
+issue slip. Examples of review comments could be:
+
+- Questions ("Why do you need to do this?", "What if X happens?")
+- Bugs ("I think you need a logical \|\| rather than a bitwise \|.")
+- Design issues ("This won't scale well when we introduce feature X.")
+- Improvements ("Would it be better if we did Y instead?")
+
+
+Guidelines for code owners
+--------------------------
+
+Code owners are listed on the :ref:`Project Maintenance<code owners>` page,
+along with the module(s) they look after.
+
+When reviewing a patch, code owners are expected to check the following:
+
+- The patch looks good from a technical point of view. For example:
+
+ - The structure of the code is clear.
+
+ - It complies with the relevant standards or technical documentation (where
+ applicable).
+
+ - It leverages existing interfaces rather than introducing new ones
+ unnecessarily.
+
+ - It fits well in the design of the module.
+
+ - It adheres to the security model of the project. In particular, it does not
+ increase the attack surface (e.g. new SMCs) without justification.
+
+- The patch adheres to the TF-A :ref:`Coding Style`. The CI system should help
+ catch coding style violations.
+
+- (Only applicable to generic code) The code is MISRA-compliant (see
+ :ref:`misra-compliance`). The CI system should help catch violations.
+
+- Documentation is provided/updated (where applicable).
+
+- The patch has had an appropriate level of testing. Testing details are
+ expected to be provided by the patch author. If they are not, do not hesitate
+ to request this information.
+
+- All CI automated tests pass.
+
+If a code owner is happy with a patch, they should give their approval
+through the ``Code-Owner-Review+1`` label in Gerrit. If instead, they have
+concerns, questions, or any other type of blocking comment, they should set
+``Code-Owner-Review-1``.
+
+Code owners are expected to behave professionally and responsibly. Here are some
+guidelines for them:
+
+- Once you are engaged in a review, make sure you stay involved until the patch
+ is merged. Rejecting a patch and going away is not very helpful. You are
+ expected to monitor the patch author's answers to your review comments,
+ answer back if needed and review new revisions of their patch.
+
+- Provide constructive feedback. Just saying, "This is wrong, you should do X
+ instead." is usually not very helpful. The patch author is unlikely to
+ understand why you are requesting this change and might feel personally
+ attacked.
+
+- Be mindful when reviewing a patch. As a code owner, you are viewed as
+ the expert for the relevant module. By approving a patch, you are partially
+ responsible for its quality and the effects it has for all TF-A users. Make
+ sure you fully understand what the implications of a patch might be.
+
+
+Guidelines for maintainers
+--------------------------
+
+Maintainers are listed on the :ref:`Project Maintenance<maintainers>` page.
+
+When reviewing a patch, maintainers are expected to check the following:
+
+- The general structure of the patch looks good. This covers things like:
+
+ - Code organization.
+
+ - Files and directories, names and locations.
+
+ For example, platform code should be added under the ``plat/`` directory.
+
+ - Naming conventions.
+
+ For example, platform identifiers should be properly namespaced to avoid
+ name clashes with generic code.
+
+ - API design.
+
+- Interaction of the patch with other modules in the code base.
+
+- The patch aims at complying with any standard or technical documentation
+ that applies.
+
+- New files must have the correct license and copyright headers. See :ref:`this
+ paragraph<copyright-license-guidance>` for more information. The CI system
+ should help catch files with incorrect or no copyright/license headers.
+
+- There is no third party code or binary blobs with potential IP concerns.
+ Maintainers should look for copyright or license notices in code, and use
+ their best judgement. If they are unsure about a patch, they should ask
+ other maintainers for help.
+
+- Generally speaking, new driver code should be placed in the generic
+ layer. There are cases where a driver has to stay into the platform layer but
+ this should be the exception, rather than the rule.
+
+- Existing common drivers (in particular for Arm IPs like the GIC driver) should
+ not be copied into the platform layer to cater for platform quirks. This
+ type of code duplication hurts the maintainability of the project. The
+ duplicate driver is less likely to benefit from bug fixes and future
+ enhancements. In most cases, it is possible to rework a generic driver to
+ make it more flexible and fit slightly different use cases. That way, these
+ enhancements benefit everyone.
+
+- When a platform specific driver really is required, the burden lies with the
+ patch author to prove the need for it. A detailed justification should be
+ posted via the commit message or on the mailing list.
+
+- Before merging a patch, verify that all review comments have been addressed.
+ If this is not the case, encourage the patch author and the relevant
+ reviewers to resolve these together.
+
+If a maintainer is happy with a patch, they should give their approval
+through the ``Maintainer-Review+1`` label in Gerrit. If instead, they have
+concerns, questions, or any other type of blocking comment, they should set
+``Maintainer-Review-1``.
+
+--------------
+
+*Copyright (c) 2020, Arm Limited. All rights reserved.*
+
+.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/process/coding-style.rst b/docs/process/coding-style.rst
index fd1984d..be13b14 100644
--- a/docs/process/coding-style.rst
+++ b/docs/process/coding-style.rst
@@ -42,6 +42,8 @@
Clang does lack support for a small number of GNU extensions. These
missing extensions are rarely used, however, and should not pose a problem.
+.. _misra-compliance:
+
MISRA Compliance
----------------
@@ -99,7 +101,7 @@
parentheses.
Control statements (``if``, ``for``, ``switch``, ``while``, etc) must be
-separated from the following open paranthesis by a single space. The previous
+separated from the following open parenthesis by a single space. The previous
example illustrates this for an ``if`` statement.
Line Length
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index 0b3b848..15c2b45 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -90,6 +90,8 @@
(and nothing else) in the last commit of the series. Otherwise, include
the documentation changes within the single commit.
+.. _copyright-license-guidance:
+
- Ensure that each changed file has the correct copyright and license
information. Files that entirely consist of contributions to this project
should have a copyright notice and BSD-3-Clause SPDX license identifier of
diff --git a/docs/process/index.rst b/docs/process/index.rst
index 1cb5354..37324b0 100644
--- a/docs/process/index.rst
+++ b/docs/process/index.rst
@@ -11,5 +11,6 @@
coding-style
coding-guidelines
contributing
+ code-review-guidelines
faq
security-hardening
diff --git a/docs/resources/diagrams/plantuml/fip-secure-partitions.puml b/docs/resources/diagrams/plantuml/fip-secure-partitions.puml
index 40621db..9457e32 100644
--- a/docs/resources/diagrams/plantuml/fip-secure-partitions.puml
+++ b/docs/resources/diagrams/plantuml/fip-secure-partitions.puml
@@ -13,6 +13,7 @@
===
UUID = xxx
load_address = 0xaaa
+ owner = "Sip"
...
]
}
@@ -24,9 +25,26 @@
===
UUID = yyy
load_address = 0xbbb
+ owner = "Plat"
]
}
+artifact tb_fw_config.dts [
+ tb_fw_config.dts
+ ----
+ secure-partitions
+ ===
+ spkg_1 UUID
+ spkg_1 load_address
+ ---
+ spkg_2 UUID
+ spkg_2 load_address
+ ---
+ ...
+ ===
+ ...<rest of the nodes>
+]
+
artifact config.json [
SP_LAYOUT.json
===
@@ -41,31 +59,22 @@
control sp_mk_generator
-artifact fconf_node [
- fconf_sp.dts
- ===
- spkg_1 UUID
- spkg_1 load_address
- ---
- spkg_2 UUID
- spkg_2 load_address
-]
-
artifact sp_gen [
sp_gen.mk
===
FDT_SOURCE = ...
SPTOOL_ARGS = ...
- FIP_ARG = ...
+ FIP_ARGS = ...
+ CRT_ARGS = ...
]
control dtc
control sptool
-artifact FW_CONFIG
+artifact tb_fw_config.dtb
artifact spkg_1 [
- spkg_1.bin
+ sp1.pkg
===
<i>header</i>
---
@@ -75,7 +84,7 @@
]
artifact spkg_2 [
- spkg_2.bin
+ sp2.pkg
===
<i>header</i>
---
@@ -84,18 +93,47 @@
binary
]
+artifact signed_tb_fw_config.dtb [
+ tb_fw_config.dtb (signed)
+]
+
+artifact signed_spkg_1 [
+ sp1.pkg (signed)
+ ===
+ <i>header</i>
+ ---
+ manifest
+ ---
+ binary
+ ---
+ <i>signature</I>
+]
+
+artifact signed_spkg_2 [
+ sp2.pkg (signed)
+ ===
+ <i>header</i>
+ ---
+ manifest
+ ---
+ binary
+ ---
+ <i>signature</I>
+]
+
+control crttool
control fiptool
artifact fip [
fip.bin
===
- FW_CONFIG.dtb
+ tb_fw_config.dtb (signed)
---
...
---
- SPKG1
+ sp1.pkg (signed & SiP owned)
---
- SPKG2
+ sp2.pkg (signed & Platform owned)
---
...
]
@@ -103,20 +141,27 @@
config.json .up.> SP_vendor_1
config.json .up.> SP_vendor_2
config.json --> sp_mk_generator
-sp_mk_generator --> fconf_node
sp_mk_generator --> sp_gen
-
+sp_gen --> fiptool
+sp_gen --> cert_create
sp_gen --> sptool
+
sptool --> spkg_1
sptool --> spkg_2
-fconf_node -down-> dtc
-dtc --> FW_CONFIG
+spkg_1 --> cert_create
+spkg_2 --> cert_create
+cert_create --> signed_spkg_1
+cert_create --> signed_spkg_2
-sp_gen --> fiptool
-FW_CONFIG --> fiptool
-spkg_1 -down-> fiptool
-spkg_2 -down-> fiptool
+tb_fw_config.dts --> dtc
+dtc --> tb_fw_config.dtb
+tb_fw_config.dtb --> cert_create
+cert_create --> signed_tb_fw_config.dtb
+
+signed_tb_fw_config.dtb --> fiptool
+signed_spkg_1 -down-> fiptool
+signed_spkg_2 -down-> fiptool
fiptool -down-> fip
@enduml
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index d1995e3..4c1a80e 100644
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -105,15 +105,15 @@
cmp w0, #0xA
b.ne 2f
1:
- /* Check if the transmit FIFO is full */
+ /* Check if the transmit FIFO is empty */
ldr w2, [x1, #R_UART_SR]
- tbnz w2, #UART_SR_INTR_TFUL_BIT, 1b
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, 1b
mov w2, #0xD
str w2, [x1, #R_UART_TX]
2:
- /* Check if the transmit FIFO is full */
+ /* Check if the transmit FIFO is empty */
ldr w2, [x1, #R_UART_SR]
- tbnz w2, #UART_SR_INTR_TFUL_BIT, 2b
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, 2b
str w0, [x1, #R_UART_TX]
ret
endfunc console_cdns_core_putc
diff --git a/drivers/marvell/uart/a3700_console.S b/drivers/marvell/uart/a3700_console.S
index d184a2d..dc374ee 100644
--- a/drivers/marvell/uart/a3700_console.S
+++ b/drivers/marvell/uart/a3700_console.S
@@ -232,6 +232,11 @@
* ---------------------------------------------
*/
func console_a3700_core_flush
+ /* Wait for the TX FIFO to be empty */
+1: ldr w1, [x0, #UART_STATUS_REG]
+ and w1, w1, #UARTLSR_TXFIFOEMPTY
+ cmp w1, #UARTLSR_TXFIFOEMPTY
+ b.ne 1b
ret
endfunc console_a3700_core_flush
diff --git a/drivers/renesas/rcar/auth/auth_mod.c b/drivers/renesas/common/auth/auth_mod.c
similarity index 89%
rename from drivers/renesas/rcar/auth/auth_mod.c
rename to drivers/renesas/common/auth/auth_mod.c
index ece3462..4aa86e2 100644
--- a/drivers/renesas/rcar/auth/auth_mod.c
+++ b/drivers/renesas/common/auth/auth_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -7,29 +7,28 @@
#include <stddef.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>
+#include <platform_def.h>
#include "rom_api.h"
typedef int32_t(*secure_boot_api_f) (uint32_t a, uint32_t b, void *c);
extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert_addr);
-#define RCAR_IMAGE_ID_MAX (10)
-#define RCAR_CERT_MAGIC_NUM (0xE291F358U)
+#define RCAR_IMAGE_ID_MAX (10)
+#define RCAR_CERT_MAGIC_NUM (0xE291F358U)
#define RCAR_BOOT_KEY_CERT (0xE6300C00U)
#define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U)
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-#define MFISOFTMDR (0xE6260600U)
-#define MODEMR_MD5_MASK (0x00000020U)
-#define MODEMR_MD5_SHIFT (5U)
-#define SOFTMD_BOOTMODE_MASK (0x00000001U)
-#define SOFTMD_NORMALBOOT (0x1U)
+#define RST_BASE (0xE6160000U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
+#define MFISOFTMDR (0xE6260600U)
+#define MODEMR_MD5_MASK (0x00000020U)
+#define MODEMR_MD5_SHIFT (5U)
+#define SOFTMD_BOOTMODE_MASK (0x00000001U)
+#define SOFTMD_NORMALBOOT (0x1U)
static secure_boot_api_f secure_boot_api;
@@ -125,9 +124,9 @@
#if RCAR_BL2_DCACHE == 1
/* enable */
write_sctlr_el3(read_sctlr_el3() | SCTLR_C_BIT);
-#endif
+#endif /* RCAR_BL2_DCACHE */
-#endif
+#endif /* IMAGE_BL2 */
return ret;
}
diff --git a/drivers/renesas/rcar/avs/avs_driver.c b/drivers/renesas/common/avs/avs_driver.c
similarity index 90%
rename from drivers/renesas/rcar/avs/avs_driver.c
rename to drivers/renesas/common/avs/avs_driver.c
index 647869e..2c939cd 100644
--- a/drivers/renesas/rcar/avs/avs_driver.c
+++ b/drivers/renesas/common/avs/avs_driver.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,8 +8,8 @@
#include <lib/mmio.h>
#include <lib/utils_def.h>
-#include "cpg_registers.h"
#include "avs_driver.h"
+#include "cpg_registers.h"
#include "rcar_def.h"
#include "rcar_private.h"
@@ -22,12 +22,12 @@
#endif /* PMIC_ROHM_BD9571 */
/* Base address of Adaptive Voltage Scaling module registers*/
-#define AVS_BASE (0xE60A0000U)
+#define AVS_BASE (0xE60A0000U)
/* Adaptive Dynamic Voltage ADJust Parameter2 registers */
-#define ADVADJP2 (AVS_BASE + 0x013CU)
+#define ADVADJP2 (AVS_BASE + 0x013CU)
/* Mask VOLCOND bit in ADVADJP2 registers */
-#define ADVADJP2_VOLCOND_MASK (0x000001FFU) /* VOLCOND[8:0] */
+#define ADVADJP2_VOLCOND_MASK (0x000001FFU) /* VOLCOND[8:0] */
#if PMIC_ROHM_BD9571
/* I2C for DVFS bit in CPG registers for module standby and software reset*/
@@ -38,19 +38,19 @@
#if PMIC_ROHM_BD9571
/* Base address of IICDVFS registers*/
-#define IIC_DVFS_BASE (0xE60B0000U)
+#define IIC_DVFS_BASE (0xE60B0000U)
/* IIC bus data register */
-#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U)
+#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U)
/* IIC bus control register */
-#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U)
+#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U)
/* IIC bus status register */
-#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U)
+#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U)
/* IIC interrupt control register */
-#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU)
+#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU)
/* IIC clock control register low */
-#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U)
+#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U)
/* IIC clock control register high */
-#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U)
+#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U)
/* Bit in ICSR register */
#define ICSR_BUSY (0x10U)
@@ -76,20 +76,23 @@
#define ICCR_STOP_RECV (0xC0U)
/* Low-level period of SCL */
-#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */
-#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */
-#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */
-#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */
+#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */
+#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */
+#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */
+#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */
/* High-level period of SCL */
-#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */
-#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */
-#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */
-#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */
+#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */
+#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */
+#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */
+#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */
/* PMIC */
-#define PMIC_W_SLAVE_ADDRESS (0x60U) /* ROHM BD9571 slave address + (W) */
-#define PMIC_R_SLAVE_ADDRESS (0x61U) /* ROHM BD9571 slave address + (R) */
-#define PMIC_DVFS_SETVID (0x54U) /* ROHM BD9571 DVFS SetVID register */
+/* ROHM BD9571 slave address + (W) */
+#define PMIC_W_SLAVE_ADDRESS (0x60U)
+/* ROHM BD9571 slave address + (R) */
+#define PMIC_R_SLAVE_ADDRESS (0x61U)
+/* ROHM BD9571 DVFS SetVID register */
+#define PMIC_DVFS_SETVID (0x54U)
#endif /* PMIC_ROHM_BD9571 */
/* Individual information */
@@ -102,7 +105,7 @@
} initial_voltage_t;
static const initial_voltage_t init_vol_tbl[] = {
- /* AVS code, RHOM BD9571 DVFS SetVID register */
+ /* AVS code, ROHM BD9571 DVFS SetVID register */
{0x00U, 0x53U}, /* AVS0, 0.83V */
{0x01U, 0x52U}, /* AVS1, 0.82V */
{0x02U, 0x51U}, /* AVS2, 0.81V */
@@ -188,7 +191,7 @@
/* Disable I2C module and All internal registers initialized. */
mmio_write_8(IIC_ICCR, 0x00U);
while ((mmio_read_8(IIC_ICCR) & ICCR_ENABLE) != 0U) {
- /* Disable I2C module and All internal registers initialized. */
+ /* Disable I2C module and all internal registers initialized. */
mmio_write_8(IIC_ICCR, 0x00U);
}
@@ -283,8 +286,8 @@
/* Dose efuse_avs exceed the number of */
/* the tables? */
if (efuse_avs >= EFUSE_AVS_NUM) {
- ERROR("AVS number of eFuse is out "
- "of a range. number=%u\n",
+ ERROR("%s%s=%u\n", "AVS number of ",
+ "eFuse is out of range. number",
efuse_avs);
/* Infinite loop */
panic();
@@ -417,7 +420,8 @@
{
uint8_t addr = PMIC_DVFS_SETVID;
uint8_t value = avs_read_pmic_reg(addr);
- NOTICE("Read PMIC register. address=0x%x value=0x%x \n",
+
+ NOTICE("Read PMIC register. address=0x%x value=0x%x\n",
addr, value);
}
#endif
@@ -446,8 +450,8 @@
avs_error_t ret;
if ((mmio_read_8(IIC_ICSR) & ICSR_AL) == ICSR_AL) {
- NOTICE("Loss of arbitration is detected. "
- "AVS status=%d Retry=%u\n", avs_status, avs_retry);
+ NOTICE("%s AVS status=%d Retry=%u\n",
+ "Loss of arbitration is detected.", avs_status, avs_retry);
/* Check of retry number of times */
if (avs_retry >= AVS_RETRY_NUM) {
ERROR("AVS setting failed in retry. max=%u\n",
@@ -458,8 +462,8 @@
/* Set the error detected to error status. */
ret = avs_error_al;
} else if ((mmio_read_8(IIC_ICSR) & ICSR_TACK) == ICSR_TACK) {
- NOTICE("Non-acknowledge is detected. "
- "AVS status=%d Retry=%u\n", avs_status, avs_retry);
+ NOTICE("%s AVS status=%d Retry=%u\n",
+ "Non-acknowledge is detected.", avs_status, avs_retry);
/* Check of retry number of times */
if (avs_retry >= AVS_RETRY_NUM) {
ERROR("AVS setting failed in retry. max=%u\n",
@@ -526,8 +530,10 @@
/* Set frequency of 400kHz */
avs_set_iic_clock();
- /* Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission */
- /* interrupt and wait interrupt. */
+ /*
+ * Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission
+ * interrupt and wait interrupt.
+ */
mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_WAITE | ICIC_DTEE);
/* Write H'94 in ICCR to issue start condition */
diff --git a/drivers/renesas/rcar/avs/avs_driver.h b/drivers/renesas/common/avs/avs_driver.h
similarity index 100%
rename from drivers/renesas/rcar/avs/avs_driver.h
rename to drivers/renesas/common/avs/avs_driver.h
diff --git a/drivers/renesas/common/common.c b/drivers/renesas/common/common.c
new file mode 100644
index 0000000..9b7c1eb
--- /dev/null
+++ b/drivers/renesas/common/common.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+
+#include "rcar_private.h"
+
+#if IMAGE_BL31
+void __attribute__ ((section(".system_ram"))) cpg_write(uintptr_t regadr, uint32_t regval)
+#else
+void cpg_write(uintptr_t regadr, uint32_t regval)
+#endif
+{
+ uint32_t value = regval;
+
+ mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
+ mmio_write_32(regadr, value);
+}
+
+#if IMAGE_BL31
+void __attribute__ ((section(".system_ram"))) mstpcr_write(uint32_t mstpcr, uint32_t mstpsr,
+ uint32_t target_bit)
+#else
+void mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
+#endif
+{
+ uint32_t reg;
+
+ reg = mmio_read_32(mstpcr);
+ reg &= ~target_bit;
+ cpg_write(mstpcr, reg);
+ while ((mmio_read_32(mstpsr) & target_bit) != 0U) {
+ }
+}
diff --git a/drivers/renesas/rcar/console/rcar_console.S b/drivers/renesas/common/console/rcar_console.S
similarity index 100%
rename from drivers/renesas/rcar/console/rcar_console.S
rename to drivers/renesas/common/console/rcar_console.S
diff --git a/drivers/renesas/rcar/console/rcar_printf.c b/drivers/renesas/common/console/rcar_printf.c
similarity index 66%
rename from drivers/renesas/rcar/console/rcar_printf.c
rename to drivers/renesas/common/console/rcar_printf.c
index e75b9f4..ad074fe 100644
--- a/drivers/renesas/rcar/console/rcar_printf.c
+++ b/drivers/renesas/common/console/rcar_printf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,11 +19,22 @@
#define INDEX_TIMER_COUNT (4U)
+#define RCAR_LOG_HEAD (('T' << 0) | ('L' << 8) | ('O' << 16) | ('G' << 24))
+
+/*
+ * The log is initialized and used before BL31 xlat tables are initialized,
+ * therefore the log memory is a device memory at that point. Make sure the
+ * memory is correclty aligned and accessed only with up-to 32bit, aligned,
+ * writes.
+ */
+CASSERT((RCAR_BL31_LOG_BASE & 0x7) == 0, assert_bl31_log_base_unaligned);
+CASSERT((RCAR_BL31_LOG_MAX & 0x7) == 0, assert_bl31_log_max_unaligned);
+
extern RCAR_INSTANTIATE_LOCK typedef struct log_head {
- uint8_t head[4];
+ uint32_t head;
uint32_t index;
uint32_t size;
- uint8_t res[4];
+ uint32_t res;
} loghead_t;
typedef struct log_map {
@@ -66,15 +77,12 @@
int32_t rcar_log_init(void)
{
-
- static const uint8_t const_header[] = "TLOG";
- logmap_t *t_log;
+ logmap_t *t_log = (logmap_t *)RCAR_BL31_LOG_BASE;
+ uint32_t *log_data = (uint32_t *)t_log->log_data;
int16_t init_flag = 0;
+ int i;
- t_log = (logmap_t *) RCAR_BL31_LOG_BASE;
- if (memcmp
- ((const void *)t_log->header.head, (const void *)const_header,
- sizeof(t_log->header.head)) != 0) {
+ if (t_log->header.head != RCAR_LOG_HEAD) {
/*
* Log header is not "TLOG", then log area initialize
*/
@@ -87,11 +95,10 @@
init_flag = 1;
}
if (init_flag == 1) {
- (void)memset((void *)t_log->log_data, 0,
- (size_t) RCAR_BL31_LOG_MAX);
- (void)memcpy((void *)t_log->header.head,
- (const void *)const_header,
- sizeof(t_log->header.head));
+ for (i = 0; i < RCAR_BL31_LOG_MAX; i += 4)
+ *log_data++ = 0;
+
+ t_log->header.head = RCAR_LOG_HEAD;
t_log->header.index = 0U;
t_log->header.size = 0U;
}
diff --git a/drivers/renesas/rcar/console/rcar_printf.h b/drivers/renesas/common/console/rcar_printf.h
similarity index 100%
rename from drivers/renesas/rcar/console/rcar_printf.h
rename to drivers/renesas/common/console/rcar_printf.h
diff --git a/drivers/renesas/rcar/ddr/ddr_regs.h b/drivers/renesas/common/ddr_regs.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_regs.h
rename to drivers/renesas/common/ddr_regs.h
diff --git a/drivers/renesas/rcar/delay/micro_delay.c b/drivers/renesas/common/delay/micro_delay.c
similarity index 80%
rename from drivers/renesas/rcar/delay/micro_delay.c
rename to drivers/renesas/common/delay/micro_delay.c
index aced589..a5e2a69 100644
--- a/drivers/renesas/rcar/delay/micro_delay.c
+++ b/drivers/renesas/common/delay/micro_delay.c
@@ -1,18 +1,19 @@
/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
+
#include "micro_delay.h"
#define RCAR_CONV_MICROSEC 1000000U
void
#if IMAGE_BL31
- __attribute__ ((section (".system_ram")))
+ __attribute__ ((section(".system_ram")))
#endif
rcar_micro_delay(uint64_t micro_sec)
{
diff --git a/drivers/renesas/rcar/delay/micro_delay.h b/drivers/renesas/common/delay/micro_delay.h
similarity index 100%
rename from drivers/renesas/rcar/delay/micro_delay.h
rename to drivers/renesas/common/delay/micro_delay.h
diff --git a/drivers/renesas/rcar/dma/dma_driver.c b/drivers/renesas/common/dma/dma_driver.c
similarity index 76%
rename from drivers/renesas/rcar/dma/dma_driver.c
rename to drivers/renesas/common/dma/dma_driver.c
index e0be46e..44ee985 100644
--- a/drivers/renesas/rcar/dma/dma_driver.c
+++ b/drivers/renesas/common/dma/dma_driver.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,15 +11,15 @@
#include <common/debug.h>
#include <lib/mmio.h>
-#include "rcar_def.h"
#include "cpg_registers.h"
+#include "rcar_def.h"
#include "rcar_private.h"
/* DMA CHANNEL setting (0/16/32) */
#if RCAR_LSI == RCAR_V3M
-#define DMA_CH 16
+#define DMA_CH 16
#else
-#define DMA_CH 0
+#define DMA_CH 0
#endif
#if (DMA_CH == 0)
@@ -39,7 +39,7 @@
/* DMA operation */
#define DMA_DMAOR (DMA_BASE + 0x0060U)
/* DMA secure control */
-#define DMA_DMASEC (DMA_BASE + 0x0030U)
+#define DMA_DMASEC (DMA_BASE + 0x0030U)
/* DMA channel clear */
#define DMA_DMACHCLR (DMA_BASE + 0x0080U)
/* DMA source address */
@@ -53,21 +53,21 @@
/* DMA fixed destination address */
#define DMA_DMAFIXDAR (DMA_BASE + 0x8014U)
-#define DMA_USE_CHANNEL (0x00000001U)
-#define DMAOR_INITIAL (0x0301U)
-#define DMACHCLR_CH_ALL (0x0000FFFFU)
-#define DMAFIXDAR_32BIT_SHIFT (32U)
-#define DMAFIXDAR_DAR_MASK (0x000000FFU)
-#define DMADAR_BOUNDARY_ADDR (0x100000000ULL)
-#define DMATCR_CNT_SHIFT (6U)
-#define DMATCR_MAX (0x00FFFFFFU)
-#define DMACHCR_TRN_MODE (0x00105409U)
-#define DMACHCR_DE_BIT (0x00000001U)
-#define DMACHCR_TE_BIT (0x00000002U)
-#define DMACHCR_CHE_BIT (0x80000000U)
+#define DMA_USE_CHANNEL (0x00000001U)
+#define DMAOR_INITIAL (0x0301U)
+#define DMACHCLR_CH_ALL (0x0000FFFFU)
+#define DMAFIXDAR_32BIT_SHIFT (32U)
+#define DMAFIXDAR_DAR_MASK (0x000000FFU)
+#define DMADAR_BOUNDARY_ADDR (0x100000000ULL)
+#define DMATCR_CNT_SHIFT (6U)
+#define DMATCR_MAX (0x00FFFFFFU)
+#define DMACHCR_TRN_MODE (0x00105409U)
+#define DMACHCR_DE_BIT (0x00000001U)
+#define DMACHCR_TE_BIT (0x00000002U)
+#define DMACHCR_CHE_BIT (0x80000000U)
-#define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT
-#define DMA_FRACTION_MASK (0xFFU)
+#define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT
+#define DMA_FRACTION_MASK (0xFFU)
#define DMA_DST_LIMIT (0x10000000000ULL)
/* transfer length limit */
@@ -129,16 +129,16 @@
}
if (src & DMA_FRACTION_MASK) {
- ERROR("BL2: DMA - source address invalid (0x%x), "
- "length (0x%x)\n", src, dma_len);
+ ERROR("BL2: DMA - src address invalid (0x%x), len=(0x%x)\n",
+ src, dma_len);
panic();
}
if ((dst & UINT32_MAX) + dma_len > DMADAR_BOUNDARY_ADDR ||
- (dst + dma_len > DMA_DST_LIMIT) ||
+ (dst + dma_len > DMA_DST_LIMIT) ||
(dst & DMA_FRACTION_MASK)) {
- ERROR("BL2: DMA - destination address invalid (0x%lx), "
- "length (0x%x)\n", dst, dma_len);
+ ERROR("BL2: DMA - dest address invalid (0x%lx), len=(0x%x)\n",
+ dst, dma_len);
panic();
}
diff --git a/drivers/renesas/rcar/emmc/emmc_cmd.c b/drivers/renesas/common/emmc/emmc_cmd.c
similarity index 92%
rename from drivers/renesas/rcar/emmc/emmc_cmd.c
rename to drivers/renesas/common/emmc/emmc_cmd.c
index a2e25e3..d255bff 100644
--- a/drivers/renesas/rcar/emmc/emmc_cmd.c
+++ b/drivers/renesas/common/emmc/emmc_cmd.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,10 @@
#include <common/debug.h>
#include "emmc_config.h"
-#include "emmc_hal.h"
-#include "emmc_std.h"
-#include "emmc_registers.h"
#include "emmc_def.h"
+#include "emmc_hal.h"
+#include "emmc_registers.h"
+#include "emmc_std.h"
#include "micro_delay.h"
static void emmc_little_to_big(uint8_t *p, uint32_t value)
@@ -22,6 +22,7 @@
p[1] = (uint8_t) (value >> 16);
p[2] = (uint8_t) (value >> 8);
p[3] = (uint8_t) value;
+
}
static void emmc_softreset(void)
@@ -64,7 +65,6 @@
SETR_32(SD_INFO2, SD_INFO2_CLEAR);
SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */
SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
-
}
static void emmc_read_response(uint32_t *response)
@@ -96,8 +96,7 @@
{
HAL_MEMCARD_RESPONSE_TYPE response_type =
- (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
- cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
+ ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
if (response == NULL)
return EMMC_ERR_PARAM;
@@ -117,7 +116,7 @@
}
return EMMC_ERR_CARD_STATUS_BIT;
}
- return EMMC_SUCCESS;;
+ return EMMC_SUCCESS;
}
if (response_type == HAL_MEMCARD_RESPONSE_R4) {
@@ -223,11 +222,11 @@
state = ESTATE_BEGIN;
response_type =
- (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
- cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
+ ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd &
+ HAL_MEMCARD_RESPONSE_TYPE_MASK);
cmd_type =
- (HAL_MEMCARD_COMMAND_TYPE) (mmc_drv_obj.cmd_info.
- cmd & HAL_MEMCARD_COMMAND_TYPE_MASK);
+ ((HAL_MEMCARD_COMMAND_TYPE) mmc_drv_obj.cmd_info.cmd &
+ HAL_MEMCARD_COMMAND_TYPE_MASK);
/* state machine */
while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) {
@@ -427,8 +426,9 @@
case ESTATE_ACCESS_END:
/* clear flag */
- if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
- SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
+ /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
SETR_32(SD_STOP, 0x00000000U);
mmc_drv_obj.during_dma_transfer = FALSE;
}
@@ -448,8 +448,9 @@
case ESTATE_TRANSFER_ERROR:
/* The error occurred in the Data transfer. */
- if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
- SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
+ /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
SETR_32(SD_STOP, 0x00000000U);
mmc_drv_obj.during_dma_transfer = FALSE;
}
@@ -468,8 +469,8 @@
default:
state = ESTATE_END;
break;
- } /* switch (state) */
- } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
+ } /* switch (state) */
+ } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
/* force terminate */
if (mmc_drv_obj.force_terminate == TRUE) {
@@ -481,7 +482,7 @@
ERROR("BL2: emmc exec_cmd:EMMC_ERR_FORCE_TERMINATE\n");
emmc_softreset();
- return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */
+ return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */
}
/* success */
diff --git a/drivers/renesas/common/emmc/emmc_config.h b/drivers/renesas/common/emmc/emmc_config.h
new file mode 100644
index 0000000..16b6b8a
--- /dev/null
+++ b/drivers/renesas/common/emmc/emmc_config.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_CONFIG_H
+#define EMMC_CONFIG_H
+
+/* RCA */
+#define EMMC_RCA 1UL
+/* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
+#define EMMC_RW_DATA_TIMEOUT 0x40UL
+/* how many times to try after fail. Don't change. */
+#define EMMC_RETRY_COUNT 0
+#define EMMC_CMD_MAX 60UL /* Don't change. */
+
+#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL
+
+#endif /* EMMC_CONFIG_H */
diff --git a/drivers/renesas/rcar/emmc/emmc_def.h b/drivers/renesas/common/emmc/emmc_def.h
similarity index 100%
rename from drivers/renesas/rcar/emmc/emmc_def.h
rename to drivers/renesas/common/emmc/emmc_def.h
diff --git a/drivers/renesas/common/emmc/emmc_hal.h b/drivers/renesas/common/emmc/emmc_hal.h
new file mode 100644
index 0000000..0a85517
--- /dev/null
+++ b/drivers/renesas/common/emmc/emmc_hal.h
@@ -0,0 +1,535 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_HAL_H
+#define EMMC_HAL_H
+
+/* memory card error/status types */
+#define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L
+#define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L
+#define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L
+#define HAL_MEMCARD_ERASE_SEQ_ERROR 0x10000000L
+#define HAL_MEMCARD_ERASE_PARAM 0x08000000L
+#define HAL_MEMCARD_WP_VIOLATION 0x04000000L
+#define HAL_MEMCARD_CARD_IS_LOCKED 0x02000000L
+#define HAL_MEMCARD_LOCK_UNLOCK_FAILED 0x01000000L
+#define HAL_MEMCARD_COM_CRC_ERROR 0x00800000L
+#define HAL_MEMCARD_ILEGAL_COMMAND 0x00400000L
+#define HAL_MEMCARD_CARD_ECC_FAILED 0x00200000L
+#define HAL_MEMCARD_CC_ERROR 0x00100000L
+#define HAL_MEMCARD_ERROR 0x00080000L
+#define HAL_MEMCARD_UNDERRUN 0x00040000L
+#define HAL_MEMCARD_OVERRUN 0x00020000L
+#define HAL_MEMCARD_CIDCSD_OVERWRITE 0x00010000L
+#define HAL_MEMCARD_WP_ERASE_SKIP 0x00008000L
+#define HAL_MEMCARD_CARD_ECC_DISABLED 0x00004000L
+#define HAL_MEMCARD_ERASE_RESET 0x00002000L
+#define HAL_MEMCARD_CARD_STATE 0x00001E00L
+#define HAL_MEMCARD_CARD_READY_FOR_DATA 0x00000100L
+#define HAL_MEMCARD_APP_CMD 0x00000020L
+#define HAL_MEMCARD_SWITCH_ERROR 0x00000080L
+#define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L
+#define HAL_MEMCARD_NO_ERRORS 0x00000000L
+
+/* Memory card response types */
+#define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f
+
+/* Type of the return value. */
+typedef enum {
+ HAL_MEMCARD_FAIL = 0U,
+ HAL_MEMCARD_OK = 1U,
+ HAL_MEMCARD_DMA_ALLOC_FAIL = 2U, /* DMA channel allocation failed */
+ HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U, /* DMA transfer failed */
+ HAL_MEMCARD_CARD_STATUS_ERROR = 4U, /* card status non-masked error */
+ HAL_MEMCARD_CMD_TIMEOUT = 5U, /* Command timeout occurred */
+ HAL_MEMCARD_DATA_TIMEOUT = 6U, /* Data timeout occurred */
+ HAL_MEMCARD_CMD_CRC_ERROR = 7U, /* Command CRC error occurred */
+ HAL_MEMCARD_DATA_CRC_ERROR = 8U /* Data CRC error occurred */
+} HAL_MEMCARD_RETURN;
+
+/* memory access operation */
+typedef enum {
+ HAL_MEMCARD_READ = 0U, /* read */
+ HAL_MEMCARD_WRITE = 1U /* write */
+} HAL_MEMCARD_OPERATION;
+
+/* Type of data width on memorycard bus */
+typedef enum {
+ HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
+ HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
+ HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
+} HAL_MEMCARD_DATA_WIDTH; /* data (bus) width types */
+
+/* Presence of the memory card */
+typedef enum {
+ HAL_MEMCARD_CARD_IS_IN = 0U,
+ HAL_MEMCARD_CARD_IS_OUT = 1U
+} HAL_MEMCARD_PRESENCE_STATUS; /* presence status of the memory card */
+
+/* mode of data transfer */
+typedef enum {
+ HAL_MEMCARD_DMA = 0U,
+ HAL_MEMCARD_NOT_DMA = 1U
+} HAL_MEMCARD_DATA_TRANSFER_MODE;
+
+/* Memory card response types. */
+typedef enum hal_memcard_response_type {
+ HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
+ HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
+ HAL_MEMCARD_RESPONSE_R1b = 0x00200U,
+ HAL_MEMCARD_RESPONSE_R2 = 0x00300U,
+ HAL_MEMCARD_RESPONSE_R3 = 0x00400U,
+ HAL_MEMCARD_RESPONSE_R4 = 0x00500U,
+ HAL_MEMCARD_RESPONSE_R5 = 0x00600U,
+ HAL_MEMCARD_RESPONSE_R6 = 0x00700U,
+ HAL_MEMCARD_RESPONSE_R7 = 0x00800U,
+ HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
+} HAL_MEMCARD_RESPONSE_TYPE;
+
+/* Memory card command types. */
+typedef enum hal_memcard_command_type {
+ HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
+ HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
+ HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U,
+ HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U,
+ HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U,
+ HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
+} HAL_MEMCARD_COMMAND_TYPE;
+
+/* Type of memory card */
+typedef enum hal_memcard_command_card_type {
+ HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
+ HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
+ HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U,
+ HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
+} HAL_MEMCARD_COMMAND_CARD_TYPE;
+
+/* Memory card application command. */
+typedef enum hal_memcard_command_app_norm {
+ HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
+ HAL_MEMCARD_COMMAND_APP = 0x20000U,
+ HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
+} HAL_MEMCARD_COMMAND_APP_NORM;
+
+/* Memory card command codes. */
+typedef enum {
+/* class 0 and class 1 */
+ /* CMD0 */
+ CMD0_GO_IDLE_STATE =
+ 0U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
+ (uint32_t) HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD1 */
+ CMD1_SEND_OP_COND =
+ 1U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD2 */
+ CMD2_ALL_SEND_CID_MMC =
+ 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD2_ALL_SEND_CID_SD =
+ 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD3 */
+ CMD3_SET_RELATIVE_ADDR =
+ 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD3_SEND_RELATIVE_ADDR =
+ 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R6 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD4 */
+ CMD4_SET_DSR =
+ 4U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD5 */
+ CMD5_SLEEP_AWAKE =
+ 5U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD6 */
+ CMD6_SWITCH =
+ 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD6_SWITCH_FUNC =
+ 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ ACMD6_SET_BUS_WIDTH =
+ 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ /* CMD7 */
+ CMD7_SELECT_CARD =
+ 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD7(from Disconnected State to Programming State) */
+ CMD7_SELECT_CARD_PROG =
+ 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD7_DESELECT_CARD =
+ 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD8 */
+ CMD8_SEND_EXT_CSD =
+ 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD8_SEND_IF_COND =
+ 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R7 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD9 */
+ CMD9_SEND_CSD =
+ 9U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD10 */
+ CMD10_SEND_CID =
+ 10U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD11 */
+ CMD11_READ_DAT_UNTIL_STOP =
+ 11U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD12 */
+ CMD12_STOP_TRANSMISSION =
+ 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD12(R1b : write case) */
+ CMD12_STOP_TRANSMISSION_WRITE =
+ 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD13 */
+ CMD13_SEND_STATUS =
+ 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ ACMD13_SD_STATUS =
+ 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ /* CMD14 */
+ CMD14_BUSTEST_R =
+ 14U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD15 */
+ CMD15_GO_INACTIVE_STATE =
+ 15U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 2 */
+ /* CMD16 */
+ CMD16_SET_BLOCKLEN =
+ 16U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD17 */
+ CMD17_READ_SINGLE_BLOCK =
+ 17U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD18 */
+ CMD18_READ_MULTIPLE_BLOCK =
+ 18U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD19 */
+ CMD19_BUS_TEST_W =
+ 19U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 3 */
+ /* CMD20 */
+ CMD20_WRITE_DAT_UNTIL_STOP =
+ 20U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD21 */
+ CMD21 = 21U,
+ /* CMD22 */
+ CMD22 = 22U,
+ ACMD22_SEND_NUM_WR_BLOCKS =
+ 22U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+
+/* class 4 */
+ /* CMD23 */
+ CMD23_SET_BLOCK_COUNT =
+ 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ ACMD23_SET_WR_BLK_ERASE_COUNT =
+ 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ /* CMD24 */
+ CMD24_WRITE_BLOCK =
+ 24U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD25 */
+ CMD25_WRITE_MULTIPLE_BLOCK =
+ 25U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD26 */
+ CMD26_PROGRAM_CID =
+ 26U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD27 */
+ CMD27_PROGRAM_CSD =
+ 27U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 6 */
+ /* CMD28 */
+ CMD28_SET_WRITE_PROT =
+ 28U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD29 */
+ CMD29_CLR_WRITE_PROT =
+ 29U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD30 */
+ CMD30_SEND_WRITE_PROT =
+ 30U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD31 */
+ CMD30_SEND_WRITE_PROT_TYPE =
+ 31U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 5 */
+ /* CMD32 */
+ CMD32_ERASE_WR_BLK_START =
+ 32U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD33 */
+ CMD33_ERASE_WR_BLK_END =
+ 33U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD34 */
+ CMD34 = 34U,
+ /* CMD35 */
+ CMD35_ERASE_GROUP_START =
+ 35U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD36 */
+ CMD36_ERASE_GROUP_END =
+ 36U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD37 */
+ CMD37 = 37U,
+ /* CMD38 */
+ CMD38_ERASE =
+ 38U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+
+/* class 9 */
+ /* CMD39 */
+ CMD39_FASTIO =
+ 39U | (uint32_t)HAL_MEMCARD_RESPONSE_R4 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD40 */
+ CMD40_GO_IRQSTATE =
+ 40U | (uint32_t)HAL_MEMCARD_RESPONSE_R5 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD41 */
+ CMD41 = 41,
+ ACMD41_SD_SEND_OP_COND =
+ 41U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+
+/* class 7 */
+ /* CMD42 */
+ CMD42_LOCK_UNLOCK =
+ 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ ACMD42_SET_CLR_CARD_DETECT =
+ 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ CMD43 = 43U, /* CMD43 */
+ CMD44 = 44U, /* CMD44 */
+ CMD45 = 45U, /* CMD45 */
+ CMD46 = 46U, /* CMD46 */
+ CMD47 = 47U, /* CMD47 */
+ CMD48 = 48U, /* CMD48 */
+ CMD49 = 49U, /* CMD49 */
+ CMD50 = 50U, /* CMD50 */
+ CMD51 = 51U, /* CMD51 */
+ ACMD51_SEND_SCR =
+ 51U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ CMD52 = 52U, /* CMD52 */
+ CMD53 = 53U, /* CMD53 */
+ CMD54 = 54U, /* CMD54 */
+
+/* class 8 */
+ /* CMD55 */
+ CMD55_APP_CMD =
+ 55U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD56 */
+ CMD56_GEN_CMD =
+ 56U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD57 = 57U, /* CMD57 */
+ CMD58 = 58U, /* CMD58 */
+ CMD59 = 59U, /* CMD59 */
+ CMD60 = 60U, /* CMD60 */
+ CMD61 = 61U, /* CMD61 */
+ CMD62 = 62U, /* CMD62 */
+ CMD63 = 63U /* CMD63 */
+} HAL_MEMCARD_COMMAND;
+
+/*
+ * Configuration structure from HAL layer.
+ *
+ * If some field is not available it should be filled with 0xFF.
+ * The API version is 32-bit unsigned integer telling the version of the API.
+ * The integer is divided to four sections which each can be treated as a 8-bit
+ * unsigned number:
+ * Bits 31-24 make the most significant part of the version number. This number
+ * starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This
+ * number changes only, if the API itself changes so much that it is not
+ * compatible anymore with older releases.
+ * Bits 23-16 API minor version number. For example API version 2.1 would be
+ * 0x0201xxxx.
+ * Bits 15-8 are the number of the year when release is done. The 0 is year
+ * 2000, 1 is year 2001 and so on
+ * Bits 7- are the week number when release is done. First full week of the
+ * year is 1
+ *
+ * Example: let's assume that release 2.1 is done on week 10 year 2008
+ * the version will get the value 0x0201080A
+ */
+typedef struct {
+ /*
+ * Version of the chipset API implementation
+ *
+ * bits [31:24] API specification major version number.<br>
+ * bits [23:16] API specification minor version number.<br>
+ * bits [15:8] API implementation year. (2000 = 0, 2001 = 1, ...)
+ * bits [7:0] API implementation week.
+ * Example: API spec version 4.0, implementation w46 2008 => 0x0400082E
+ */
+ uint32_t api_version;
+
+ /* maximum block count which can be transferred at once */
+ uint32_t max_block_count;
+
+ /* maximum clock frequence in Hz supported by HW */
+ uint32_t max_clock_freq;
+
+ /* maximum data bus width supported by HW */
+ uint16_t max_data_width;
+
+ /* Is high-speed mode supported by HW (yes=1, no=0) */
+ uint8_t hs_mode_supported;
+
+ /* Is memory card removable (yes=1, no=0) */
+ uint8_t card_removable;
+
+} HAL_MEMCARD_HW_CONF;
+
+/* Configuration structure to HAL layer. */
+typedef struct {
+ /* how many times to try after fail, for instance sending command */
+ uint32_t retries_after_fail;
+} HAL_MEMCARD_INIT_CONF;
+
+#endif /* EMMC_HAL_H */
diff --git a/drivers/renesas/rcar/emmc/emmc_init.c b/drivers/renesas/common/emmc/emmc_init.c
similarity index 83%
rename from drivers/renesas/rcar/emmc/emmc_init.c
rename to drivers/renesas/common/emmc/emmc_init.c
index b27e165..354aa3c 100644
--- a/drivers/renesas/rcar/emmc/emmc_init.c
+++ b/drivers/renesas/common/emmc/emmc_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,12 +32,12 @@
return EMMC_SUCCESS;
}
-static __inline void emmc_set_retry_count(uint32_t retry)
+static inline void emmc_set_retry_count(uint32_t retry)
{
mmc_drv_obj.retries_after_fail = retry;
}
-static __inline void emmc_set_data_timeout(uint32_t data_timeout)
+static inline void emmc_set_data_timeout(uint32_t data_timeout)
{
mmc_drv_obj.data_timeout = data_timeout;
}
@@ -73,7 +73,8 @@
EMMC_ERROR_CODE result;
uint32_t dataL;
- /* MMC power off
+ /*
+ * MMC power off
* the power supply of eMMC device is always turning on.
* RST_n : Hi --> Low level.
*/
@@ -115,27 +116,25 @@
SETR_32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */
SETR_32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */
- SETR_32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */
+ SETR_32(SD_CLK_CTRL, 0x00000000U); /* Disable Automatic Control & Clock Output */
return EMMC_SUCCESS;
}
static EMMC_ERROR_CODE emmc_reset_controller(void)
{
- EMMC_ERROR_CODE retult;
+ EMMC_ERROR_CODE result;
/* initialize mmc driver */
emmc_drv_init();
/* initialize H/W */
- retult = emmc_dev_init();
- if (EMMC_SUCCESS != retult) {
- return retult;
+ result = emmc_dev_init();
+ if (result == EMMC_SUCCESS) {
+ mmc_drv_obj.initialize = TRUE;
}
- mmc_drv_obj.initialize = TRUE;
-
- return retult;
+ return result;
}
@@ -152,14 +151,12 @@
EMMC_ERROR_CODE rcar_emmc_init(void)
{
- EMMC_ERROR_CODE retult;
+ EMMC_ERROR_CODE result;
- retult = emmc_reset_controller();
- if (EMMC_SUCCESS != retult) {
- return retult;
+ result = emmc_reset_controller();
+ if (result == EMMC_SUCCESS) {
+ emmc_driver_config();
}
- emmc_driver_config();
-
- return EMMC_SUCCESS;
+ return result;
}
diff --git a/drivers/renesas/rcar/emmc/emmc_interrupt.c b/drivers/renesas/common/emmc/emmc_interrupt.c
similarity index 96%
rename from drivers/renesas/rcar/emmc/emmc_interrupt.c
rename to drivers/renesas/common/emmc/emmc_interrupt.c
index 2557280..092fdfb 100644
--- a/drivers/renesas/rcar/emmc/emmc_interrupt.c
+++ b/drivers/renesas/common/emmc/emmc_interrupt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -118,7 +118,7 @@
SETR_32(DM_CM_INFO2, 0x00000000U);
/* interrupt clear */
SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE));
- /* DM_CM_INFO2: DMA-ch0 error occured */
+ /* DM_CM_INFO2: DMA-ch0 error occurred */
if ((BIT16 & mmc_drv_obj.dm_event2) != 0) {
mmc_drv_obj.dma_error_flag = TRUE;
} else {
@@ -128,13 +128,13 @@
/* wait next interrupt */
mmc_drv_obj.state_machine_blocking = FALSE;
}
- /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */
+ /* DM_CM_INFO1: DMA-ch1 transfer complete or error occurred */
else if ((end_bit & mmc_drv_obj.dm_event1) != 0U) {
SETR_32(DM_CM_INFO1, 0x00000000U);
SETR_32(DM_CM_INFO2, 0x00000000U);
/* interrupt clear */
SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE));
- /* DM_CM_INFO2: DMA-ch1 error occured */
+ /* DM_CM_INFO2: DMA-ch1 error occurred */
if ((BIT17 & mmc_drv_obj.dm_event2) != 0) {
mmc_drv_obj.dma_error_flag = TRUE;
} else {
diff --git a/drivers/renesas/rcar/emmc/emmc_mount.c b/drivers/renesas/common/emmc/emmc_mount.c
similarity index 92%
rename from drivers/renesas/rcar/emmc/emmc_mount.c
rename to drivers/renesas/common/emmc/emmc_mount.c
index df8203e..e04afd4 100644
--- a/drivers/renesas/rcar/emmc/emmc_mount.c
+++ b/drivers/renesas/common/emmc/emmc_mount.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,10 +8,10 @@
#include <lib/mmio.h>
#include "emmc_config.h"
-#include "emmc_hal.h"
-#include "emmc_std.h"
-#include "emmc_registers.h"
#include "emmc_def.h"
+#include "emmc_hal.h"
+#include "emmc_registers.h"
+#include "emmc_std.h"
#include "micro_delay.h"
#include "rcar_def.h"
@@ -53,7 +53,7 @@
int32_t retry;
uint32_t freq = MMC_400KHZ; /* 390KHz */
EMMC_ERROR_CODE result;
- uint32_t resultCalc;
+ uint32_t result_calc;
/* state check */
if ((mmc_drv_obj.initialize != TRUE)
@@ -161,9 +161,12 @@
mmc_drv_obj.selected = TRUE;
- /* card speed check */
- resultCalc = emmc_calc_tran_speed(&freq); /* Card spec is calculated from TRAN_SPEED(CSD). */
- if (resultCalc == 0) {
+ /*
+ * card speed check
+ * Card spec is calculated from TRAN_SPEED(CSD)
+ */
+ result_calc = emmc_calc_tran_speed(&freq);
+ if (result_calc == 0) {
emmc_write_error_info(EMMC_FUNCNO_CARD_INIT,
EMMC_ERR_ILLEGAL_CARD);
return EMMC_ERR_ILLEGAL_CARD;
@@ -201,7 +204,8 @@
HAL_MEMCARD_NOT_DMA);
result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
if (result != EMMC_SUCCESS) {
- /* CMD12 is not send.
+ /*
+ * CMD12 is not send.
* If BUS initialization is failed, user must be execute Bus initialization again.
* Bus initialization is start CMD0(soft reset command).
*/
@@ -217,7 +221,7 @@
static EMMC_ERROR_CODE emmc_high_speed(void)
{
- uint32_t freq; /**< High speed mode clock frequency */
+ uint32_t freq; /* High speed mode clock frequency */
EMMC_ERROR_CODE result;
uint8_t cardType;
@@ -236,8 +240,8 @@
else
freq = MMC_20MHZ;
- /* Hi-Speed-mode selction */
- if ((MMC_52MHZ == freq) || (MMC_26MHZ == freq)) {
+ /* Hi-Speed-mode selection */
+ if ((freq == MMC_52MHZ) || (freq == MMC_26MHZ)) {
/* CMD6 */
emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING);
result =
@@ -322,7 +326,8 @@
return EMMC_ERR_STATE;
}
- mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2); /* 2 = 8bit, 1 = 4bit, 0 =1bit */
+ /* 2 = 8bit, 1 = 4bit, 0 =1bit */
+ mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2);
/* CMD6 */
emmc_make_nontrans_cmd(CMD6_SWITCH,
@@ -371,7 +376,6 @@
return EMMC_SUCCESS;
EXIT:
-
emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, result);
ERROR("BL2: emmc bus_width error end\n");
return result;
@@ -489,82 +493,83 @@
static uint32_t emmc_calc_tran_speed(uint32_t *freq)
{
- const uint32_t unit[8] = { 10000, 100000, 1000000, 10000000,
- 0, 0, 0, 0 }; /**< frequency unit (1/10) */
- const uint32_t mult[16] = { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45,
- 52, 55, 60, 70, 80 };
-
- uint32_t maxFreq;
- uint32_t result;
+ const uint32_t unit[8] = { 10000U, 100000U, 1000000U, 10000000U,
+ 0U, 0U, 0U, 0U }; /* frequency unit (1/10) */
+ const uint32_t mult[16] = { 0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, 35U,
+ 40U, 45U, 52U, 55U, 60U, 70U, 80U };
uint32_t tran_speed = EMMC_CSD_TRAN_SPEED();
+ uint32_t max_freq;
+ uint32_t result;
- /* tran_speed = 0x32
+ /*
+ * tran_speed = 0x32
* unit[tran_speed&0x7] = uint[0x2] = 1000000
* mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26
* 1000000 * 26 = 26000000 (26MHz)
*/
result = 1;
- maxFreq =
+ max_freq =
unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] *
mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >>
EMMC_TRANSPEED_MULT_SHIFT];
- if (maxFreq == 0) {
+ if (max_freq == 0) {
result = 0;
- } else if (MMC_FREQ_52MHZ <= maxFreq)
+ } else if (max_freq >= MMC_FREQ_52MHZ) {
*freq = MMC_52MHZ;
- else if (MMC_FREQ_26MHZ <= maxFreq)
+ } else if (max_freq >= MMC_FREQ_26MHZ) {
*freq = MMC_26MHZ;
- else if (MMC_FREQ_20MHZ <= maxFreq)
+ } else if (max_freq >= MMC_FREQ_20MHZ) {
*freq = MMC_20MHZ;
- else
+ } else {
*freq = MMC_400KHZ;
+ }
return result;
}
static uint32_t emmc_set_timeout_register_value(uint32_t freq)
{
- uint32_t timeoutCnt; /* SD_OPTION - Timeout Counter */
+ uint32_t timeout_cnt; /* SD_OPTION - Timeout Counter */
switch (freq) {
case 1U:
- timeoutCnt = 0xE0U;
+ timeout_cnt = 0xE0U;
break; /* SDCLK * 2^27 */
case 2U:
- timeoutCnt = 0xE0U;
+ timeout_cnt = 0xE0U;
break; /* SDCLK * 2^27 */
case 4U:
- timeoutCnt = 0xD0U;
+ timeout_cnt = 0xD0U;
break; /* SDCLK * 2^26 */
case 8U:
- timeoutCnt = 0xC0U;
+ timeout_cnt = 0xC0U;
break; /* SDCLK * 2^25 */
case 16U:
- timeoutCnt = 0xB0U;
+ timeout_cnt = 0xB0U;
break; /* SDCLK * 2^24 */
case 32U:
- timeoutCnt = 0xA0U;
+ timeout_cnt = 0xA0U;
break; /* SDCLK * 2^23 */
case 64U:
- timeoutCnt = 0x90U;
+ timeout_cnt = 0x90U;
break; /* SDCLK * 2^22 */
case 128U:
- timeoutCnt = 0x80U;
+ timeout_cnt = 0x80U;
break; /* SDCLK * 2^21 */
case 256U:
- timeoutCnt = 0x70U;
+ timeout_cnt = 0x70U;
break; /* SDCLK * 2^20 */
case 512U:
- timeoutCnt = 0x70U;
+ timeout_cnt = 0x70U;
break; /* SDCLK * 2^20 */
default:
- timeoutCnt = 0xE0U;
+ timeout_cnt = 0xE0U;
break; /* SDCLK * 2^27 */
}
- return timeoutCnt;
+ return timeout_cnt;
}
EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg)
diff --git a/drivers/renesas/rcar/emmc/emmc_read.c b/drivers/renesas/common/emmc/emmc_read.c
similarity index 91%
rename from drivers/renesas/rcar/emmc/emmc_read.c
rename to drivers/renesas/common/emmc/emmc_read.c
index 390d0ca..96e73ca 100644
--- a/drivers/renesas/rcar/emmc/emmc_read.c
+++ b/drivers/renesas/common/emmc/emmc_read.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,15 +7,15 @@
#include <arch_helpers.h>
#include "emmc_config.h"
-#include "emmc_hal.h"
-#include "emmc_std.h"
-#include "emmc_registers.h"
#include "emmc_def.h"
+#include "emmc_hal.h"
+#include "emmc_registers.h"
+#include "emmc_std.h"
-#define MIN_EMMC(a, b) (((a) < (b)) ? (a) : (b))
-#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffU
+#define MIN_EMMC(a, b) (((a) < (b)) ? (a) : (b))
+#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffU
-static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual,
+static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual,
uint32_t sector_number, uint32_t count,
HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
{
@@ -39,7 +39,8 @@
}
SETR_32(SD_SECCNT, count);
SETR_32(SD_STOP, 0x00000100);
- SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); /* SD_BUF Read/Write DMA Transfer enable */
+ /* SD_BUF Read/Write DMA Transfer enable */
+ SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE));
/* CMD18 */
emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number,
diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h
new file mode 100644
index 0000000..ae689ca
--- /dev/null
+++ b/drivers/renesas/common/emmc/emmc_registers.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_REGISTERS_H
+#define EMMC_REGISTERS_H
+
+/* MMC channel select */
+#define MMC_CH0 (0U) /* SDHI2/MMC0 */
+#define MMC_CH1 (1U) /* SDHI3/MMC1 */
+
+#if RCAR_LSI == RCAR_E3
+#define USE_MMC_CH (MMC_CH1) /* R-Car E3 */
+#else /* RCAR_LSI == RCAR_E3 */
+#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
+#endif /* RCAR_LSI == RCAR_E3 */
+
+#define BIT0 (0x00000001U)
+#define BIT1 (0x00000002U)
+#define BIT2 (0x00000004U)
+#define BIT3 (0x00000008U)
+#define BIT4 (0x00000010U)
+#define BIT5 (0x00000020U)
+#define BIT6 (0x00000040U)
+#define BIT7 (0x00000080U)
+#define BIT8 (0x00000100U)
+#define BIT9 (0x00000200U)
+#define BIT10 (0x00000400U)
+#define BIT11 (0x00000800U)
+#define BIT12 (0x00001000U)
+#define BIT13 (0x00002000U)
+#define BIT14 (0x00004000U)
+#define BIT15 (0x00008000U)
+#define BIT16 (0x00010000U)
+#define BIT17 (0x00020000U)
+#define BIT18 (0x00040000U)
+#define BIT19 (0x00080000U)
+#define BIT20 (0x00100000U)
+#define BIT21 (0x00200000U)
+#define BIT22 (0x00400000U)
+#define BIT23 (0x00800000U)
+#define BIT24 (0x01000000U)
+#define BIT25 (0x02000000U)
+#define BIT26 (0x04000000U)
+#define BIT27 (0x08000000U)
+#define BIT28 (0x10000000U)
+#define BIT29 (0x20000000U)
+#define BIT30 (0x40000000U)
+#define BIT31 (0x80000000U)
+
+/* Clock Pulse Generator (CPG) registers */
+#define CPG_BASE (0xE6150000U)
+/* Module stop status register 3 */
+#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
+/* System module stop control register 3 */
+#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU)
+/* SDHI2 clock frequency control register */
+#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
+/* SDHI3 clock frequency control register */
+#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
+/* CPG Write Protect Register */
+#define CPG_CPGWPR (CPG_BASE + 0x0900U)
+
+#if USE_MMC_CH == MMC_CH0
+#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
+#else /* USE_MMC_CH == MMC_CH0 */
+#define CPG_SDxCKCR (CPG_SD3CKCR) /* SDHI3/MMC1 */
+#endif /* USE_MMC_CH == MMC_CH0 */
+
+/* Boot Status register */
+#define MFISBTSTSR (0xE6260604U)
+
+#define MFISBTSTSR_BOOT_PARTITION (0x00000010U)
+
+/* eMMC registers */
+#define MMC0_SD_BASE (0xEE140000U)
+#define MMC1_SD_BASE (0xEE160000U)
+
+#if USE_MMC_CH == MMC_CH0
+#define MMC_SD_BASE (MMC0_SD_BASE)
+#else /* USE_MMC_CH == MMC_CH0 */
+#define MMC_SD_BASE (MMC1_SD_BASE)
+#endif /* USE_MMC_CH == MMC_CH0 */
+
+#define SD_CMD (MMC_SD_BASE + 0x0000U)
+#define SD_PORTSEL (MMC_SD_BASE + 0x0008U)
+#define SD_ARG (MMC_SD_BASE + 0x0010U)
+#define SD_ARG1 (MMC_SD_BASE + 0x0018U)
+#define SD_STOP (MMC_SD_BASE + 0x0020U)
+#define SD_SECCNT (MMC_SD_BASE + 0x0028U)
+#define SD_RSP10 (MMC_SD_BASE + 0x0030U)
+#define SD_RSP1 (MMC_SD_BASE + 0x0038U)
+#define SD_RSP32 (MMC_SD_BASE + 0x0040U)
+#define SD_RSP3 (MMC_SD_BASE + 0x0048U)
+#define SD_RSP54 (MMC_SD_BASE + 0x0050U)
+#define SD_RSP5 (MMC_SD_BASE + 0x0058U)
+#define SD_RSP76 (MMC_SD_BASE + 0x0060U)
+#define SD_RSP7 (MMC_SD_BASE + 0x0068U)
+#define SD_INFO1 (MMC_SD_BASE + 0x0070U)
+#define SD_INFO2 (MMC_SD_BASE + 0x0078U)
+#define SD_INFO1_MASK (MMC_SD_BASE + 0x0080U)
+#define SD_INFO2_MASK (MMC_SD_BASE + 0x0088U)
+#define SD_CLK_CTRL (MMC_SD_BASE + 0x0090U)
+#define SD_SIZE (MMC_SD_BASE + 0x0098U)
+#define SD_OPTION (MMC_SD_BASE + 0x00A0U)
+#define SD_ERR_STS1 (MMC_SD_BASE + 0x00B0U)
+#define SD_ERR_STS2 (MMC_SD_BASE + 0x00B8U)
+#define SD_BUF0 (MMC_SD_BASE + 0x00C0U)
+#define SDIO_MODE (MMC_SD_BASE + 0x00D0U)
+#define SDIO_INFO1 (MMC_SD_BASE + 0x00D8U)
+#define SDIO_INFO1_MASK (MMC_SD_BASE + 0x00E0U)
+#define CC_EXT_MODE (MMC_SD_BASE + 0x0360U)
+#define SOFT_RST (MMC_SD_BASE + 0x0380U)
+#define VERSION (MMC_SD_BASE + 0x0388U)
+#define HOST_MODE (MMC_SD_BASE + 0x0390U)
+#define DM_CM_DTRAN_MODE (MMC_SD_BASE + 0x0820U)
+#define DM_CM_DTRAN_CTRL (MMC_SD_BASE + 0x0828U)
+#define DM_CM_RST (MMC_SD_BASE + 0x0830U)
+#define DM_CM_INFO1 (MMC_SD_BASE + 0x0840U)
+#define DM_CM_INFO1_MASK (MMC_SD_BASE + 0x0848U)
+#define DM_CM_INFO2 (MMC_SD_BASE + 0x0850U)
+#define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U)
+#define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U)
+
+/* SD_INFO1 Registers */
+#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */
+#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */
+#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */
+#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */
+#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */
+#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */
+#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */
+#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */
+#define SD_INFO1_INFO2 0x00000004UL /* Access end */
+#define SD_INFO1_INFO0 0x00000001UL /* Response end */
+
+/* SD_INFO2 Registers */
+#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */
+#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */
+#define SD_INFO2_SCLKDIVEN 0x00002000UL
+#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */
+#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */
+#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */
+#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */
+#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */
+#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */
+#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */
+#define SD_INFO2_ERR2 0x00000004UL /* END Error */
+#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */
+#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */
+#define SD_INFO2_ALL_ERR 0x0000807FUL
+#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 write value should always be 1. HWM_0003 */
+
+/* SOFT_RST */
+#define SOFT_RST_SDRST 0x00000001UL
+
+/* SD_CLK_CTRL */
+#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL
+#define SD_CLK_CTRL_SCLKEN 0x00000100UL
+#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL
+#define SD_CLOCK_ENABLE 0x00000100UL
+#define SD_CLOCK_DISABLE 0x00000000UL
+#define SD_CLK_WRITE_MASK 0x000003FFUL
+#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL
+
+/* SD_OPTION */
+#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL
+
+/*
+ * MMC Clock Frequency
+ * 200MHz * 1/x = output clock
+ */
+#define MMC_CLK_OFF 0UL /* Clock output is disabled */
+#define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */
+#define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
+#define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz HS mode 26Mhz */
+#define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz HS mode 52Mhz */
+#define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */
+#define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */
+
+#define MMC_FREQ_52MHZ 52000000UL
+#define MMC_FREQ_26MHZ 26000000UL
+#define MMC_FREQ_20MHZ 20000000UL
+
+/* MMC Clock DIV */
+#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */
+#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
+#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */
+#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */
+#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */
+#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */
+#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */
+#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */
+#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */
+#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */
+#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */
+#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */
+
+/* DM_CM_DTRAN_MODE */
+#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */
+#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */
+#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL
+
+/* CC_EXT_MODE */
+#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */
+#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */
+
+/* DM_CM_INFO_MASK */
+#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL
+#define DM_CM_INFO_CH0_ENABLE 0x00010001UL
+#define DM_CM_INFO_CH1_ENABLE 0x00020001UL
+
+/* DM_DTRAN_ADDR */
+#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL
+
+/* DM_CM_DTRAN_CTRL */
+#define DM_CM_DTRAN_CTRL_START 0x00000001UL
+
+/* SYSC Registers */
+#if USE_MMC_CH == MMC_CH0
+#define CPG_MSTP_MMC (BIT12) /* SDHI2/MMC0 */
+#else /* USE_MMC_CH == MMC_CH0 */
+#define CPG_MSTP_MMC (BIT11) /* SDHI3/MMC1 */
+#endif /* USE_MMC_CH == MMC_CH0 */
+
+#endif /* EMMC_REGISTERS_H */
diff --git a/drivers/renesas/common/emmc/emmc_std.h b/drivers/renesas/common/emmc/emmc_std.h
new file mode 100644
index 0000000..087c6e9
--- /dev/null
+++ b/drivers/renesas/common/emmc/emmc_std.h
@@ -0,0 +1,475 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMMC_STD_H
+#define EMMC_STD_H
+
+#include "emmc_hal.h"
+
+#ifndef FALSE
+#define FALSE 0U
+#endif
+#ifndef TRUE
+#define TRUE 1U
+#endif
+
+/* 64bit registers */
+#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v))
+#define GETR_64(r) (*(volatile uint64_t *)(r))
+
+/* 32bit registers */
+#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v))
+#define GETR_32(r) (*(volatile uint32_t *)(r))
+
+/* 16bit registers */
+#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v))
+#define GETR_16(r) (*(volatile uint16_t *)(r))
+
+/* 8bit registers */
+#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v))
+#define GETR_8(r) (*(volatile uint8_t *)(r))
+
+/* CSD register Macros */
+#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y)))
+
+#define EMMC_CID_MID() (EMMC_GET_CID(127, 120))
+#define EMMC_CID_CBX() (EMMC_GET_CID(113, 112))
+#define EMMC_CID_OID() (EMMC_GET_CID(111, 104))
+#define EMMC_CID_PNM1() (EMMC_GET_CID(103, 88))
+#define EMMC_CID_PNM2() (EMMC_GET_CID(87, 56))
+#define EMMC_CID_PRV() (EMMC_GET_CID(55, 48))
+#define EMMC_CID_PSN() (EMMC_GET_CID(47, 16))
+#define EMMC_CID_MDT() (EMMC_GET_CID(15, 8))
+#define EMMC_CID_CRC() (EMMC_GET_CID(7, 1))
+
+/* CSD register Macros */
+#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y)))
+
+#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126))
+#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122))
+#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112))
+#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104))
+#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96))
+#define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84))
+#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80))
+#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79))
+#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78))
+#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77))
+#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76))
+#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62))
+#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59))
+#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56))
+#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53))
+#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50))
+#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47))
+#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42))
+#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37))
+#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32))
+#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31))
+#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29))
+#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26))
+#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22))
+#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21))
+#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16))
+#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15))
+#define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14))
+#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13))
+#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12))
+#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10))
+#define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8))
+#define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1))
+
+/* sector access */
+#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003
+#define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */
+#define EMMC_SECTOR_SIZE 512
+#define EMMC_BLOCK_LENGTH 512
+#define EMMC_BLOCK_LENGTH_DW 128
+#define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */
+
+/* eMMC specification clock */
+#define EMMC_CLOCK_SPEC_400K 400000UL /* initialize clock 400KHz */
+#define EMMC_CLOCK_SPEC_20M 20000000UL /* normal speed 20MHz */
+#define EMMC_CLOCK_SPEC_26M 26000000UL /* high speed 26MHz */
+#define EMMC_CLOCK_SPEC_52M 52000000UL /* high speed 52MHz */
+#define EMMC_CLOCK_SPEC_100M 100000000UL /* high speed 100MHz */
+
+/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */
+typedef enum {
+ EMMC_ERR = 0, /* unknown error */
+ EMMC_SUCCESS, /* OK */
+ EMMC_ERR_FROM_DMAC, /* DMAC allocation error */
+ EMMC_ERR_FROM_DMAC_TRANSFER, /* DMAC transfer error */
+ EMMC_ERR_CARD_STATUS_BIT, /* card status error */
+ EMMC_ERR_CMD_TIMEOUT, /* command timeout error */
+ EMMC_ERR_DATA_TIMEOUT, /* data timeout error */
+ EMMC_ERR_CMD_CRC, /* command CRC error */
+ EMMC_ERR_DATA_CRC, /* data CRC error */
+ EMMC_ERR_PARAM, /* parameter error */
+ EMMC_ERR_RESPONSE, /* response error */
+ EMMC_ERR_RESPONSE_BUSY, /* response busy error */
+ EMMC_ERR_TRANSFER, /* data transfer error */
+ EMMC_ERR_READ_SECTOR, /* read sector error */
+ EMMC_ERR_WRITE_SECTOR, /* write sector error */
+ EMMC_ERR_STATE, /* state error */
+ EMMC_ERR_TIMEOUT, /* timeout error */
+ EMMC_ERR_ILLEGAL_CARD, /* illegal card */
+ EMMC_ERR_CARD_BUSY, /* Busy state */
+ EMMC_ERR_CARD_STATE, /* card state error */
+ EMMC_ERR_SET_TRACE, /* trace information error */
+ EMMC_ERR_FROM_TIMER, /* Timer error */
+ EMMC_ERR_FORCE_TERMINATE, /* Force terminate */
+ EMMC_ERR_CARD_POWER, /* card power fail */
+ EMMC_ERR_ERASE_SECTOR, /* erase sector error */
+ EMMC_ERR_INFO2 /* exec cmd error info2 */
+} EMMC_ERROR_CODE;
+
+/* Function number */
+#define EMMC_FUNCNO_NONE 0U
+#define EMMC_FUNCNO_DRIVER_INIT 1U
+#define EMMC_FUNCNO_CARD_POWER_ON 2U
+#define EMMC_FUNCNO_MOUNT 3U
+#define EMMC_FUNCNO_CARD_INIT 4U
+#define EMMC_FUNCNO_HIGH_SPEED 5U
+#define EMMC_FUNCNO_BUS_WIDTH 6U
+#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U
+#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U
+#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U
+#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U
+#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U
+#define EMMC_FUNCNO_SET_CLOCK 12U
+#define EMMC_FUNCNO_EXEC_CMD 13U
+#define EMMC_FUNCNO_READ_SECTOR 14U
+#define EMMC_FUNCNO_WRITE_SECTOR 15U
+#define EMMC_FUNCNO_ERASE_SECTOR 16U
+#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U
+/*
+ * Response
+ * R1
+ * Type 'E' bit and bit14(must be 0). ignore bit22
+ */
+#define EMMC_R1_ERROR_MASK 0xFDBFE080U
+/* Ignore bit23 (Not check CRC error) */
+#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U)
+#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */
+#define EMMC_R1_READY 0x00000100U /* bit8 */
+#define EMMC_R1_STATE_SHIFT 9
+
+/* R4 */
+#define EMMC_R4_RCA_MASK 0xFFFF0000UL
+#define EMMC_R4_STATUS 0x00008000UL
+
+/* CSD */
+#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */
+#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0
+#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */
+#define EMMC_TRANSPEED_MULT_SHIFT 3
+
+/* OCR */
+#define EMMC_HOST_OCR_VALUE 0x40FF8080
+#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */
+#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */
+#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L
+#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L
+
+/* EXT_CSD */
+#define EMMC_EXT_CSD_S_CMD_SET 504
+#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241
+#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239
+#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238
+#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235
+#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234
+#define EMMC_EXT_CSD_TRIM_MULT 232
+#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231
+#define EMMC_EXT_CSD_SEC_ERASE_MULT 229
+#define EMMC_EXT_CSD_BOOT_INFO 228
+#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226
+#define EMMC_EXT_CSD_ACC_SIZE 225
+#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224
+#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223
+#define EMMC_EXT_CSD_PEL_WR_SEC_C 222
+#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221
+#define EMMC_EXT_CSD_S_C_VCC 220
+#define EMMC_EXT_CSD_S_C_VCCQ 219
+#define EMMC_EXT_CSD_S_A_TIMEOUT 217
+#define EMMC_EXT_CSD_SEC_COUNT 215
+#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210
+#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209
+#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208
+#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207
+#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206
+#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205
+#define EMMC_EXT_CSD_PWR_CL_26_360 203
+#define EMMC_EXT_CSD_PWR_CL_52_360 202
+#define EMMC_EXT_CSD_PWR_CL_26_195 201
+#define EMMC_EXT_CSD_PWR_CL_52_195 200
+#define EMMC_EXT_CSD_CARD_TYPE 196
+#define EMMC_EXT_CSD_CSD_STRUCTURE 194
+#define EMMC_EXT_CSD_EXT_CSD_REV 192
+#define EMMC_EXT_CSD_CMD_SET 191
+#define EMMC_EXT_CSD_CMD_SET_REV 189
+#define EMMC_EXT_CSD_POWER_CLASS 187
+#define EMMC_EXT_CSD_HS_TIMING 185
+#define EMMC_EXT_CSD_BUS_WIDTH 183
+#define EMMC_EXT_CSD_ERASED_MEM_CONT 181
+#define EMMC_EXT_CSD_PARTITION_CONFIG 179
+#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178
+#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177
+#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175
+#define EMMC_EXT_CSD_BOOT_WP 173
+#define EMMC_EXT_CSD_USER_WP 171
+#define EMMC_EXT_CSD_FW_CONFIG 169
+#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168
+#define EMMC_EXT_CSD_RST_n_FUNCTION 162
+#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160
+#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159
+#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156
+#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155
+#define EMMC_EXT_CSD_GP_SIZE_MULT 154
+#define EMMC_EXT_CSD_ENH_SIZE_MULT 142
+#define EMMC_EXT_CSD_ENH_START_ADDR 139
+#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134
+
+#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01
+#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02
+#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04
+#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08
+#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e
+
+/* SWITCH (CMD6) argument */
+#define EXTCSD_ACCESS_BYTE (BIT25 | BIT24)
+#define EXTCSD_SET_BITS BIT24
+
+#define HS_TIMING_ADD (185 << 16) /* H'b9 */
+#define HS_TIMING_1 (1 << 8)
+#define HS_TIMING_HS200 (2 << 8)
+#define HS_TIMING_HS400 (3 << 8)
+
+#define BUS_WIDTH_ADD (183 << 16) /* H'b7 */
+#define BUS_WIDTH_1 (0 << 8)
+#define BUS_WIDTH_4 (1 << 8)
+#define BUS_WIDTH_8 (2 << 8)
+#define BUS_WIDTH_4DDR (5 << 8)
+#define BUS_WIDTH_8DDR (6 << 8)
+
+#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE | HS_TIMING_ADD |\
+ HS_TIMING_1) /* H'03b90100 */
+#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE |\
+ HS_TIMING_ADD) /* H'03b90000 */
+
+#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_1) /* H'03b70000 */
+#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_4) /* H'03b70100 */
+#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_8) /* H'03b70200 */
+#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_4DDR) /* H'03b70500 */
+#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_8DDR) /* H'03b70600 */
+/* Partition config = 0x00 */
+#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL
+
+#define TIMING_HIGH_SPEED 1UL
+#define EMMC_BOOT_PARTITION_EN_MASK 0x38U
+#define EMMC_BOOT_PARTITION_EN_SHIFT 3U
+
+/* Bus width */
+#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT
+#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT
+#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT
+
+/* for st_mmc_base */
+#define EMMC_MAX_RESPONSE_LENGTH 17
+#define EMMC_MAX_CID_LENGTH 16
+#define EMMC_MAX_CSD_LENGTH 16
+#define EMMC_MAX_EXT_CSD_LENGTH 512U
+#define EMMC_RES_REG_ALIGNED 4U
+#define EMMC_BUF_REG_ALIGNED 8U
+
+/* TAAC mask */
+#define TAAC_TIME_UNIT_MASK (0x07)
+#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F)
+
+/* Partition id */
+typedef enum {
+ PARTITION_ID_USER = 0x0, /* User Area */
+ PARTITION_ID_BOOT_1 = 0x1, /* boot partition 1 */
+ PARTITION_ID_BOOT_2 = 0x2, /* boot partition 2 */
+ PARTITION_ID_RPMB = 0x3, /* Replay Protected Memory Block */
+ PARTITION_ID_GP_1 = 0x4, /* General Purpose partition 1 */
+ PARTITION_ID_GP_2 = 0x5, /* General Purpose partition 2 */
+ PARTITION_ID_GP_3 = 0x6, /* General Purpose partition 3 */
+ PARTITION_ID_GP_4 = 0x7, /* General Purpose partition 4 */
+ PARTITION_ID_MASK = 0x7 /* [2:0] */
+} EMMC_PARTITION_ID;
+
+/* card state in R1 response [12:9] */
+typedef enum {
+ EMMC_R1_STATE_IDLE = 0,
+ EMMC_R1_STATE_READY,
+ EMMC_R1_STATE_IDENT,
+ EMMC_R1_STATE_STBY,
+ EMMC_R1_STATE_TRAN,
+ EMMC_R1_STATE_DATA,
+ EMMC_R1_STATE_RCV,
+ EMMC_R1_STATE_PRG,
+ EMMC_R1_STATE_DIS,
+ EMMC_R1_STATE_BTST,
+ EMMC_R1_STATE_SLEP
+} EMMC_R1_STATE;
+
+typedef enum {
+ ESTATE_BEGIN = 0,
+ ESTATE_ISSUE_CMD,
+ ESTATE_NON_RESP_CMD,
+ ESTATE_RCV_RESP,
+ ESTATE_RCV_RESPONSE_BUSY,
+ ESTATE_CHECK_RESPONSE_COMPLETE,
+ ESTATE_DATA_TRANSFER,
+ ESTATE_DATA_TRANSFER_COMPLETE,
+ ESTATE_ACCESS_END,
+ ESTATE_TRANSFER_ERROR,
+ ESTATE_ERROR,
+ ESTATE_END
+} EMMC_INT_STATE;
+
+/* eMMC boot driver error information */
+typedef struct {
+ uint16_t num; /* error no */
+ uint16_t code; /* error code */
+
+ volatile uint32_t info1; /* SD_INFO1. (hw dependent) */
+ volatile uint32_t info2; /* SD_INFO2. (hw dependent) */
+ volatile uint32_t status1; /* SD_ERR_STS1. (hw dependent) */
+ volatile uint32_t status2; /* SD_ERR_STS2. (hw dependent) */
+ volatile uint32_t dm_info1; /* DM_CM_INFO1. (hw dependent) */
+ volatile uint32_t dm_info2; /* DM_CM_INFO2. (hw dependent) */
+} st_error_info;
+
+/* Command information */
+typedef struct {
+ HAL_MEMCARD_COMMAND cmd; /* Command information */
+ uint32_t arg; /* argument */
+ HAL_MEMCARD_OPERATION dir; /* direction */
+ uint32_t hw; /* SD_CMD register value. */
+} st_command_info;
+
+/* MMC driver base */
+typedef struct {
+ st_error_info error_info; /* error information */
+ st_command_info cmd_info; /* command information */
+
+ /* for data transfer */
+ uint32_t *buff_address_virtual; /* Dest or Src buff */
+ uint32_t *buff_address_physical; /* Dest or Src buff */
+ HAL_MEMCARD_DATA_WIDTH bus_width; /* bus width */
+
+ uint32_t trans_size; /* transfer size for this command */
+ uint32_t remain_size; /* remain size for this command */
+ uint32_t response_length; /* response length for this command */
+ uint32_t sector_size; /* sector_size */
+
+ /* clock */
+ uint32_t base_clock; /* MMC host controller clock */
+ /*
+ * Max freq (Card Spec)[Hz]. It changes dynamically by CSD and
+ * EXT_CSD.
+ */
+ uint32_t max_freq;
+ /* request freq [Hz] (400K, 26MHz, 52MHz, etc) */
+ uint32_t request_freq;
+ /* current MMC clock[Hz] (the closest frequency supported by HW) */
+ uint32_t current_freq;
+
+ /* state flag */
+ /* presence status of the memory card */
+ HAL_MEMCARD_PRESENCE_STATUS card_present;
+
+ uint32_t card_power_enable;
+ uint32_t clock_enable;
+ /* True : initialize complete. */
+ uint32_t initialize;
+ /* True : sector access, FALSE : byte access */
+ uint32_t access_mode;
+ /* True : mount complete. */
+ uint32_t mount;
+ /* True : selected card. */
+ uint32_t selected;
+ /* 0: DMA, 1:PIO */
+ HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;
+
+ /* loaded ISSW image No. ISSW have copy image. */
+ uint32_t image_num;
+ /* card state */
+ EMMC_R1_STATE current_state;
+ /* True : during command processing */
+ volatile uint32_t during_cmd_processing;
+ /* True : during transfer */
+ volatile uint32_t during_transfer;
+ /* True : during transfer (DMA) */
+ volatile uint32_t during_dma_transfer;
+ /* True : occurred DMAC error */
+ volatile uint32_t dma_error_flag;
+ /* force terminate flag */
+ volatile uint32_t force_terminate;
+ /* state machine blocking flag : True or False */
+ volatile uint32_t state_machine_blocking;
+ /* True : get partition access processing */
+ volatile uint32_t get_partition_access_flag;
+
+ EMMC_PARTITION_ID boot_partition_en; /* Boot partition */
+ EMMC_PARTITION_ID partition_access; /* Current access partition */
+
+ /* timeout */
+ uint32_t hs_timing;
+
+ /* read and write data timeout */
+ uint32_t data_timeout;
+
+ /* retry */
+ uint32_t retries_after_fail;
+
+ /* interrupt */
+ volatile uint32_t int_event1; /* interrupt SD_INFO1 Event */
+ volatile uint32_t int_event2; /* interrupt SD_INFO2 Event */
+ volatile uint32_t dm_event1; /* interrupt DM_CM_INFO1 Event */
+ volatile uint32_t dm_event2; /* interrupt DM_CM_INFO2 Event */
+
+ /* response */
+ uint32_t *response; /* buffer ptr for executing command. */
+ uint32_t r1_card_status; /* R1 response data */
+ uint32_t r3_ocr; /* R3 response data */
+ uint32_t r4_resp; /* R4 response data */
+ uint32_t r5_resp; /* R5 response data */
+
+ /* True : clock mode is low. (MMC clock = Max26MHz) */
+ uint32_t low_clock_mode_enable;
+
+ uint32_t reserved2;
+ uint32_t reserved3;
+ uint32_t reserved4;
+
+ /* CSD registers (4byte align) */
+ uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /* CSD */
+ __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
+ /* CID registers (4byte align) */
+ uint8_t cid_data[EMMC_MAX_CID_LENGTH] /* CID */
+ __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
+ /* EXT CSD registers (8byte align) */
+ uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /* EXT_CSD */
+ __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED)));
+ /* Response registers (4byte align) */
+ uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /* other response */
+ __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
+} st_mmc_base;
+
+typedef int (*func) (void);
+
+uint32_t emmc_get_csd_time(void);
+
+#define MMC_DEBUG
+#endif /* EMMC_STD_H */
diff --git a/drivers/renesas/rcar/emmc/emmc_utility.c b/drivers/renesas/common/emmc/emmc_utility.c
similarity index 96%
rename from drivers/renesas/rcar/emmc/emmc_utility.c
rename to drivers/renesas/common/emmc/emmc_utility.c
index 39d9ede..2e88abc 100644
--- a/drivers/renesas/rcar/emmc/emmc_utility.c
+++ b/drivers/renesas/common/emmc/emmc_utility.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,10 @@
#include <common/debug.h>
#include "emmc_config.h"
-#include "emmc_hal.h"
-#include "emmc_std.h"
-#include "emmc_registers.h"
#include "emmc_def.h"
+#include "emmc_hal.h"
+#include "emmc_registers.h"
+#include "emmc_std.h"
static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1] = {
0x00000000, /* CMD0 */
@@ -97,8 +97,8 @@
value =
(uint32_t) ((data[index_top] << 24) |
(data[index_top + 1] << 16) |
- (data[index_top + 2] << 8) | data[index_top +
- 3]);
+ (data[index_top + 2] << 8) |
+ data[index_top + 3]);
}
value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1));
@@ -150,7 +150,7 @@
mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
break;
case HAL_MEMCARD_RESPONSE_R1b:
- mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */
+ mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */
mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
break;
case HAL_MEMCARD_RESPONSE_R2:
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c b/drivers/renesas/common/iic_dvfs/iic_dvfs.c
similarity index 67%
rename from drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
rename to drivers/renesas/common/iic_dvfs/iic_dvfs.c
index 28b56c1..e1c9a5b 100644
--- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
+++ b/drivers/renesas/common/iic_dvfs/iic_dvfs.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,59 +7,59 @@
#include <common/debug.h>
#include <lib/mmio.h>
-#include "rcar_def.h"
#include "cpg_registers.h"
#include "iic_dvfs.h"
+#include "rcar_def.h"
#include "rcar_private.h"
#define DVFS_RETRY_MAX (2U)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0B)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0E)
-#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07U)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09U)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0BU)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0EU)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15U)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05)
-#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05U)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07U)
-#define CPG_BIT_SMSTPCR9_DVFS (0x04000000)
+#define CPG_BIT_SMSTPCR9_DVFS (0x04000000U)
-#define IIC_DVFS_REG_BASE (0xE60B0000)
-#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000)
-#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004)
-#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008)
-#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000C)
-#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010)
-#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014)
+#define IIC_DVFS_REG_BASE (0xE60B0000U)
+#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000U)
+#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004U)
+#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008U)
+#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000CU)
+#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010U)
+#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014U)
-#define IIC_DVFS_BIT_ICSR_BUSY (0x10)
-#define IIC_DVFS_BIT_ICSR_AL (0x08)
-#define IIC_DVFS_BIT_ICSR_TACK (0x04)
-#define IIC_DVFS_BIT_ICSR_WAIT (0x02)
-#define IIC_DVFS_BIT_ICSR_DTE (0x01)
+#define IIC_DVFS_BIT_ICSR_BUSY (0x10U)
+#define IIC_DVFS_BIT_ICSR_AL (0x08U)
+#define IIC_DVFS_BIT_ICSR_TACK (0x04U)
+#define IIC_DVFS_BIT_ICSR_WAIT (0x02U)
+#define IIC_DVFS_BIT_ICSR_DTE (0x01U)
-#define IIC_DVFS_BIT_ICCR_ENABLE (0x80)
-#define IIC_DVFS_SET_ICCR_START (0x94)
-#define IIC_DVFS_SET_ICCR_STOP (0x90)
-#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94)
-#define IIC_DVFS_SET_ICCR_CHANGE (0x81)
-#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0)
+#define IIC_DVFS_BIT_ICCR_ENABLE (0x80U)
+#define IIC_DVFS_SET_ICCR_START (0x94U)
+#define IIC_DVFS_SET_ICCR_STOP (0x90U)
+#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94U)
+#define IIC_DVFS_SET_ICCR_CHANGE (0x81U)
+#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0U)
-#define IIC_DVFS_BIT_ICIC_TACKE (0x04)
-#define IIC_DVFS_BIT_ICIC_WAITE (0x02)
-#define IIC_DVFS_BIT_ICIC_DTEE (0x01)
+#define IIC_DVFS_BIT_ICIC_TACKE (0x04U)
+#define IIC_DVFS_BIT_ICIC_WAITE (0x02U)
+#define IIC_DVFS_BIT_ICIC_DTEE (0x01U)
-#define DVFS_READ_MODE (0x01)
-#define DVFS_WRITE_MODE (0x00)
+#define DVFS_READ_MODE (0x01U)
+#define DVFS_WRITE_MODE (0x00U)
-#define IIC_DVFS_SET_DUMMY (0x52)
+#define IIC_DVFS_SET_DUMMY (0x52U)
#define IIC_DVFS_SET_BUSY_LOOP (500000000U)
-typedef enum {
+enum dvfs_state_t {
DVFS_START = 0,
DVFS_STOP,
DVFS_RETRANSMIT,
@@ -69,9 +69,9 @@
DVFS_SET_SLAVE,
DVFS_WRITE_ADDR,
DVFS_WRITE_DATA,
- DVFS_CHANGE_SEND_TO_RECIEVE,
+ DVFS_CHANGE_SEND_TO_RECEIVE,
DVFS_DONE,
-} DVFS_STATE_T;
+};
#define DVFS_PROCESS (1)
#define DVFS_COMPLETE (0)
@@ -79,26 +79,26 @@
#if IMAGE_BL31
#define IIC_DVFS_FUNC(__name, ...) \
-static int32_t __attribute__ ((section (".system_ram"))) \
+static int32_t __attribute__ ((section(".system_ram"))) \
dvfs_ ##__name(__VA_ARGS__)
#define RCAR_DVFS_API(__name, ...) \
-int32_t __attribute__ ((section (".system_ram"))) \
+int32_t __attribute__ ((section(".system_ram"))) \
rcar_iic_dvfs_ ##__name(__VA_ARGS__)
#else
-#define IIC_DVFS_FUNC(__name, ...) \
+#define IIC_DVFS_FUNC(__name, ...) \
static int32_t dvfs_ ##__name(__VA_ARGS__)
#define RCAR_DVFS_API(__name, ...) \
int32_t rcar_iic_dvfs_ ##__name(__VA_ARGS__)
#endif
-IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
+IIC_DVFS_FUNC(check_error, enum dvfs_state_t *state, uint32_t *err, uint8_t mode)
{
- uint8_t icsr_al = 0, icsr_tack = 0;
+ uint8_t icsr_al = 0U, icsr_tack = 0U;
uint8_t reg, stop;
- uint32_t i = 0;
+ uint32_t i = 0U;
stop = mode == DVFS_READ_MODE ? IIC_DVFS_SET_ICCR_STOP_READ :
IIC_DVFS_SET_ICCR_STOP;
@@ -107,43 +107,48 @@
icsr_al = (reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL;
icsr_tack = (reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK;
- if (icsr_al == 0 && icsr_tack == 0)
+ if (icsr_al == 0U && icsr_tack == 0U) {
return DVFS_PROCESS;
+ }
if (icsr_al) {
reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_AL;
mmio_write_8(IIC_DVFS_REG_ICSR, reg);
- if (*state == DVFS_SET_SLAVE)
+ if (*state == DVFS_SET_SLAVE) {
mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY);
+ }
do {
reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
IIC_DVFS_BIT_ICSR_WAIT;
- } while (reg == 0);
+ } while (reg == 0U);
mmio_write_8(IIC_DVFS_REG_ICCR, stop);
reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
mmio_write_8(IIC_DVFS_REG_ICSR, reg);
- i = 0;
+ i = 0U;
do {
reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
IIC_DVFS_BIT_ICSR_BUSY;
- if (reg == 0)
+ if (reg == 0U) {
break;
+ }
- if (i++ > IIC_DVFS_SET_BUSY_LOOP)
+ if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
panic();
+ }
- } while (1);
+ } while (true);
mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U);
(*err)++;
- if (*err > DVFS_RETRY_MAX)
+ if (*err > DVFS_RETRY_MAX) {
return DVFS_ERROR;
+ }
*state = DVFS_START;
@@ -161,24 +166,26 @@
reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_TACK;
mmio_write_8(IIC_DVFS_REG_ICSR, reg);
- i = 0;
- while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0) {
- if (i++ > IIC_DVFS_SET_BUSY_LOOP)
+ i = 0U;
+ while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
+ if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
panic();
+ }
}
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
(*err)++;
- if (*err > DVFS_RETRY_MAX)
+ if (*err > DVFS_RETRY_MAX) {
return DVFS_ERROR;
+ }
*state = DVFS_START;
return DVFS_PROCESS;
}
-IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
+IIC_DVFS_FUNC(start, enum dvfs_state_t *state)
{
uint8_t iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_E;
uint8_t icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_E;
@@ -190,8 +197,9 @@
mmio_write_8(IIC_DVFS_REG_ICCR, mode);
lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
- if (lsi_product == PRR_PRODUCT_E3)
+ if (lsi_product == PRR_PRODUCT_E3) {
goto start;
+ }
reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
switch (reg) {
@@ -228,19 +236,21 @@
return result;
}
-IIC_DVFS_FUNC(set_slave, DVFS_STATE_T * state, uint32_t *err, uint8_t slave)
+IIC_DVFS_FUNC(set_slave, enum dvfs_state_t *state, uint32_t *err, uint8_t slave)
{
uint8_t mode;
int32_t result;
uint8_t address;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
- if (mode != IIC_DVFS_BIT_ICSR_DTE)
+ if (mode != IIC_DVFS_BIT_ICSR_DTE) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
@@ -253,18 +263,20 @@
return result;
}
-IIC_DVFS_FUNC(write_addr, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_addr)
+IIC_DVFS_FUNC(write_addr, enum dvfs_state_t *state, uint32_t *err, uint8_t reg_addr)
{
uint8_t mode;
int32_t result;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
@@ -276,18 +288,21 @@
return result;
}
-IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data)
+IIC_DVFS_FUNC(write_data, enum dvfs_state_t *state, uint32_t *err,
+ uint8_t reg_data)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICDR, reg_data);
@@ -299,18 +314,20 @@
return result;
}
-IIC_DVFS_FUNC(stop, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(stop, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP);
@@ -326,32 +343,35 @@
{
uint32_t i;
- for (i = 0; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
- if (mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY)
+ for (i = 0U; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
+ if ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
continue;
+ }
goto done;
}
panic();
done:
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
return DVFS_COMPLETE;
}
-IIC_DVFS_FUNC(write_reg_addr_read, DVFS_STATE_T *state, uint32_t *err,
- uint8_t reg_addr)
+IIC_DVFS_FUNC(write_reg_addr_read, enum dvfs_state_t *state, uint32_t *err,
+ uint8_t reg_addr)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
@@ -363,18 +383,20 @@
return result;
}
-IIC_DVFS_FUNC(retransmit, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(retransmit, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_RETRANSMISSION);
@@ -389,20 +411,22 @@
return result;
}
-IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
- uint8_t slave)
+IIC_DVFS_FUNC(set_slave_read, enum dvfs_state_t *state, uint32_t *err,
+ uint8_t slave)
{
uint8_t address;
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
- if (mode != IIC_DVFS_BIT_ICSR_DTE)
+ if (mode != IIC_DVFS_BIT_ICSR_DTE) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
@@ -410,23 +434,25 @@
address = ((uint8_t) (slave << 1) + DVFS_READ_MODE);
mmio_write_8(IIC_DVFS_REG_ICDR, address);
- *state = DVFS_CHANGE_SEND_TO_RECIEVE;
+ *state = DVFS_CHANGE_SEND_TO_RECEIVE;
return result;
}
-IIC_DVFS_FUNC(change_send_to_recieve, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(change_send_to_receive, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_CHANGE);
@@ -438,18 +464,20 @@
return result;
}
-IIC_DVFS_FUNC(stop_read, DVFS_STATE_T *state, uint32_t *err)
+IIC_DVFS_FUNC(stop_read, enum dvfs_state_t *state, uint32_t *err)
{
int32_t result;
uint8_t mode;
result = dvfs_check_error(state, err, DVFS_READ_MODE);
- if (result == DVFS_ERROR)
+ if (result == DVFS_ERROR) {
return result;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
- if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+ if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
return result;
+ }
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP_READ);
@@ -464,13 +492,14 @@
return result;
}
-IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data)
+IIC_DVFS_FUNC(read, enum dvfs_state_t *state, uint8_t *reg_data)
{
uint8_t mode;
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
- if (mode != IIC_DVFS_BIT_ICSR_DTE)
+ if (mode != IIC_DVFS_BIT_ICSR_DTE) {
return DVFS_PROCESS;
+ }
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
@@ -483,12 +512,12 @@
RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data)
{
- DVFS_STATE_T state = DVFS_START;
+ enum dvfs_state_t state = DVFS_START;
int32_t result = DVFS_PROCESS;
- uint32_t err = 0;
+ uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
again:
switch (state) {
case DVFS_START:
@@ -514,20 +543,21 @@
break;
}
- if (result == DVFS_PROCESS)
+ if (result == DVFS_PROCESS) {
goto again;
+ }
return result;
}
RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data)
{
- DVFS_STATE_T state = DVFS_START;
+ enum dvfs_state_t state = DVFS_START;
int32_t result = DVFS_PROCESS;
- uint32_t err = 0;
+ uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
again:
switch (state) {
case DVFS_START:
@@ -545,8 +575,8 @@
case DVFS_SET_SLAVE_READ:
result = dvfs_set_slave_read(&state, &err, slave);
break;
- case DVFS_CHANGE_SEND_TO_RECIEVE:
- result = dvfs_change_send_to_recieve(&state, &err);
+ case DVFS_CHANGE_SEND_TO_RECEIVE:
+ result = dvfs_change_send_to_receive(&state, &err);
break;
case DVFS_STOP_READ:
result = dvfs_stop_read(&state, &err);
@@ -562,8 +592,9 @@
break;
}
- if (result == DVFS_PROCESS)
+ if (result == DVFS_PROCESS) {
goto again;
+ }
return result;
}
diff --git a/drivers/renesas/common/iic_dvfs/iic_dvfs.h b/drivers/renesas/common/iic_dvfs/iic_dvfs.h
new file mode 100644
index 0000000..244c06c
--- /dev/null
+++ b/drivers/renesas/common/iic_dvfs/iic_dvfs.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IIC_DVFS_H
+#define IIC_DVFS_H
+
+/* PMIC slave */
+#define PMIC (0x30U)
+#define BKUP_MODE_CNT (0x20U)
+#define DVFS_SET_VID (0x54U)
+#define REG_KEEP10 (0x79U)
+
+/* EEPROM slave */
+#define EEPROM (0x50U)
+#define BOARD_ID (0x70U)
+
+int32_t rcar_iic_dvfs_receive(uint8_t slave, uint8_t reg, uint8_t *data);
+int32_t rcar_iic_dvfs_send(uint8_t slave, uint8_t regr, uint8_t data);
+
+#endif /* IIC_DVFS_H */
diff --git a/drivers/renesas/rcar/io/io_common.h b/drivers/renesas/common/io/io_common.h
similarity index 100%
rename from drivers/renesas/rcar/io/io_common.h
rename to drivers/renesas/common/io/io_common.h
diff --git a/drivers/renesas/rcar/io/io_emmcdrv.c b/drivers/renesas/common/io/io_emmcdrv.c
similarity index 87%
rename from drivers/renesas/rcar/io/io_emmcdrv.c
rename to drivers/renesas/common/io/io_emmcdrv.c
index 84240d2..c2b5f7c 100644
--- a/drivers/renesas/rcar/io/io_emmcdrv.c
+++ b/drivers/renesas/common/io/io_emmcdrv.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,13 +10,13 @@
#include <drivers/io/io_driver.h>
#include <drivers/io/io_storage.h>
+#include "emmc_config.h"
+#include "emmc_def.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
#include "io_common.h"
#include "io_emmcdrv.h"
#include "io_private.h"
-#include "emmc_config.h"
-#include "emmc_hal.h"
-#include "emmc_std.h"
-#include "emmc_def.h"
static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)),
io_dev_info_t **dev_info);
@@ -41,8 +41,9 @@
static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode,
signed long long offset)
{
- if (mode != IO_SEEK_SET)
+ if (mode != IO_SEEK_SET) {
return IO_FAIL;
+ }
((file_state_t *) entity->info)->file_pos = offset;
@@ -64,12 +65,14 @@
current_file.partition, current_file.file_pos,
sector_add, length, sector_num);
- if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX)
+ if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX) {
emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE;
+ }
if (emmc_read_sector((uint32_t *) buffer, sector_add, sector_num,
- emmc_dma) != EMMC_SUCCESS)
+ emmc_dma) != EMMC_SUCCESS) {
result = IO_FAIL;
+ }
*length_read = length;
fp->file_pos += (signed long long)length;
@@ -92,8 +95,8 @@
if (emmcdrv_bootpartition == PARTITION_ID_USER) {
emmcdrv_bootpartition = mmc_drv_obj.boot_partition_en;
- if ((PARTITION_ID_BOOT_1 == emmcdrv_bootpartition) ||
- (PARTITION_ID_BOOT_2 == emmcdrv_bootpartition)) {
+ if ((emmcdrv_bootpartition == PARTITION_ID_BOOT_1) ||
+ (emmcdrv_bootpartition == PARTITION_ID_BOOT_2)) {
current_file.partition = emmcdrv_bootpartition;
NOTICE("BL2: eMMC boot from partition %d\n",
@@ -103,16 +106,18 @@
return IO_FAIL;
}
- if ((PARTITION_ID_USER == block_spec->partition) ||
- (PARTITION_ID_BOOT_1 == block_spec->partition) ||
- (PARTITION_ID_BOOT_2 == block_spec->partition))
+ if ((block_spec->partition == PARTITION_ID_USER) ||
+ (block_spec->partition == PARTITION_ID_BOOT_1) ||
+ (block_spec->partition == PARTITION_ID_BOOT_2)) {
current_file.partition = block_spec->partition;
- else
+ } else {
current_file.partition = emmcdrv_bootpartition;
+ }
done:
- if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS)
+ if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS) {
return IO_FAIL;
+ }
entity->info = (uintptr_t) ¤t_file;
@@ -166,8 +171,9 @@
int32_t rc;
rc = io_register_device(&emmcdrv_dev_info);
- if (rc == IO_SUCCESS)
+ if (rc == IO_SUCCESS) {
*dev_con = &emmcdrv_dev_connector;
+ }
return rc;
}
diff --git a/drivers/renesas/rcar/io/io_emmcdrv.h b/drivers/renesas/common/io/io_emmcdrv.h
similarity index 100%
rename from drivers/renesas/rcar/io/io_emmcdrv.h
rename to drivers/renesas/common/io/io_emmcdrv.h
diff --git a/drivers/renesas/rcar/io/io_memdrv.c b/drivers/renesas/common/io/io_memdrv.c
similarity index 91%
rename from drivers/renesas/rcar/io/io_memdrv.c
rename to drivers/renesas/common/io/io_memdrv.c
index 7e8c1d3..1f31c0f 100644
--- a/drivers/renesas/rcar/io/io_memdrv.c
+++ b/drivers/renesas/common/io/io_memdrv.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,8 +11,8 @@
#include <drivers/io/io_storage.h>
#include "io_common.h"
-#include "io_private.h"
#include "io_memdrv.h"
+#include "io_private.h"
#include "rcar_def.h"
extern void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len);
@@ -21,7 +21,8 @@
io_dev_info_t **dev_info);
static int32_t memdrv_dev_close(io_dev_info_t *dev_info);
-/* As we need to be able to keep state for seek, only one file can be open
+/*
+ * As we need to be able to keep state for seek, only one file can be open
* at a time. Make this a structure and point to the entity->info. When we
* can malloc memory we can change this to support more open files.
*/
@@ -43,12 +44,14 @@
{
const io_drv_spec_t *block_spec = (io_drv_spec_t *) spec;
- /* Since we need to track open state for seek() we only allow one open
+ /*
+ * Since we need to track open state for seek() we only allow one open
* spec at a time. When we have dynamic memory we can malloc and set
* entity->info.
*/
- if (current_file.in_use != 0U)
+ if (current_file.in_use != 0U) {
return IO_RESOURCES_EXHAUSTED;
+ }
/* File cursor offset for seek and incremental reads etc. */
current_file.base = block_spec->offset;
@@ -63,8 +66,9 @@
static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode,
signed long long offset)
{
- if (mode != IO_SEEK_SET)
+ if (mode != IO_SEEK_SET) {
return IO_FAIL;
+ }
((file_state_t *) entity->info)->file_pos = offset;
@@ -142,8 +146,9 @@
int32_t result;
result = io_register_device(&memdrv_dev_info);
- if (result == IO_SUCCESS)
+ if (result == IO_SUCCESS) {
*dev_con = &memdrv_dev_connector;
+ }
return result;
}
diff --git a/drivers/renesas/rcar/io/io_memdrv.h b/drivers/renesas/common/io/io_memdrv.h
similarity index 100%
rename from drivers/renesas/rcar/io/io_memdrv.h
rename to drivers/renesas/common/io/io_memdrv.h
diff --git a/drivers/renesas/rcar/io/io_private.h b/drivers/renesas/common/io/io_private.h
similarity index 100%
rename from drivers/renesas/rcar/io/io_private.h
rename to drivers/renesas/common/io/io_private.h
diff --git a/drivers/renesas/rcar/io/io_rcar.c b/drivers/renesas/common/io/io_rcar.c
similarity index 89%
rename from drivers/renesas/rcar/io/io_rcar.c
rename to drivers/renesas/common/io/io_rcar.c
index b82c510..c3e8319 100644
--- a/drivers/renesas/rcar/io/io_rcar.c
+++ b/drivers/renesas/common/io/io_rcar.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,8 +8,6 @@
#include <stdint.h>
#include <string.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -24,6 +22,7 @@
#include "io_rcar.h"
#include "io_common.h"
#include "io_private.h"
+#include <platform_def.h>
extern int32_t plat_get_drv_source(uint32_t id, uintptr_t *dev,
uintptr_t *image_spec);
@@ -39,7 +38,8 @@
} plat_rcar_name_offset_t;
typedef struct {
- /* Put position above the struct to allow {0} on static init.
+ /*
+ * Put position above the struct to allow {0} on static init.
* It is a workaround for a known bug in GCC
* http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
*/
@@ -59,7 +59,7 @@
#define RCAR_ATTR_SET_ISNOLOAD(a) (((a) & 0x1) << 16U)
#define RCAR_ATTR_SET_CERTOFF(a) (((a) & 0xF) << 8U)
#define RCAR_ATTR_SET_ALL(a, b, c) ((uint32_t)(RCAR_ATTR_SET_CALCADDR(a) |\
- RCAR_ATTR_SET_ISNOLOAD(b) | \
+ RCAR_ATTR_SET_ISNOLOAD(b) |\
RCAR_ATTR_SET_CERTOFF(c)))
#define RCAR_ATTR_GET_CALCADDR(a) ((a) & 0xFU)
@@ -136,9 +136,11 @@
{
#if TRUSTED_BOARD_BOOT
int32_t i;
+
for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
- if (name != cert_offset[i].name)
+ if (name != cert_offset[i].name) {
continue;
+ }
*cert = RCAR_CERT_SIZE;
*cert *= RCAR_ATTR_GET_CERTOFF(cert_offset[i].attr);
@@ -157,12 +159,14 @@
int32_t i;
for (i = 0; i < ARRAY_SIZE(name_offset); i++) {
- if (name != name_offset[i].name)
+ if (name != name_offset[i].name) {
continue;
+ }
addr = RCAR_ATTR_GET_CALCADDR(name_offset[i].attr);
- if (rcar_image_number + 2 < addr)
+ if (rcar_image_number + 2U < addr) {
continue;
+ }
*offset = rcar_image_header[addr];
*cert = RCAR_CERT_SIZE;
@@ -175,8 +179,9 @@
#if TRUSTED_BOARD_BOOT
for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
- if (name != cert_offset[i].name)
+ if (name != cert_offset[i].name) {
continue;
+ }
*no_load = RCAR_ATTR_GET_ISNOLOAD(cert_offset[i].attr);
*partition = 0U;
@@ -282,8 +287,9 @@
result = IO_FAIL;
}
done:
- if (result == IO_FAIL)
+ if (result == IO_FAIL) {
ERROR("BL2: Out of range : dst=0x%lx len=0x%lx\n", dst, len);
+ }
return result;
}
@@ -307,14 +313,15 @@
BL338_IMAGE_ID
};
- if (loaded != IO_NOT_SUPPORTED)
+ if (loaded != IO_NOT_SUPPORTED) {
return loaded;
+ }
for (i = 1; i < rcar_image_number; i++) {
rc = file_to_offset(img[i], &offset, &cert, &noload,
&partition);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: failed to get offset\n");
+ WARN("%s: failed to get offset\n", __func__);
loaded = IO_FAIL;
return loaded;
}
@@ -324,34 +331,34 @@
rc = io_open(rcar_handle, rcar_spec, &handle);
if (rc != IO_SUCCESS) {
- WARN("Failed to open FIP (%i)\n", rc);
+ WARN("%s: Failed to open FIP (%i)\n", __func__, rc);
loaded = IO_FAIL;
return loaded;
}
rc = io_seek(handle, IO_SEEK_SET, offset);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: failed to seek\n");
+ WARN("%s: failed to seek\n", __func__);
loaded = IO_FAIL;
return loaded;
}
rc = check_load_area(dst, len);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: check load area\n");
+ WARN("%s: check load area\n", __func__);
loaded = IO_FAIL;
return loaded;
}
rc = io_read(handle, dst, len, &cnt);
if (rc != IO_SUCCESS) {
- WARN("load_bl33x: failed to read\n");
+ WARN("%s: failed to read\n", __func__);
loaded = IO_FAIL;
return loaded;
}
#if TRUSTED_BOARD_BOOT
rc = auth_mod_verify_img(img[i], (void *)dst, len);
- if (rc) {
+ if (rc != 0) {
memset((void *)dst, 0x00, len);
loaded = IO_FAIL;
return loaded;
@@ -367,8 +374,7 @@
static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
{
- uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {
- 0};
+ uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {0UL};
uintptr_t handle;
ssize_t offset;
uint32_t i;
@@ -382,8 +388,9 @@
return IO_FAIL;
}
- if (RCAR_CERT_LOAD == rcar_cert_load)
+ if (rcar_cert_load == RCAR_CERT_LOAD) {
return IO_SUCCESS;
+ }
rc = io_open(rcar_handle, rcar_spec, &handle);
if (rc != IO_SUCCESS) {
@@ -391,16 +398,18 @@
return IO_FAIL;
}
- /* get start address list */
- /* [0] address num */
- /* [1] BL33-1 image address */
- /* [2] BL33-2 image address */
- /* [3] BL33-3 image address */
- /* [4] BL33-4 image address */
- /* [5] BL33-5 image address */
- /* [6] BL33-6 image address */
- /* [7] BL33-7 image address */
- /* [8] BL33-8 image address */
+ /*
+ * get start address list
+ * [0] address num
+ * [1] BL33-1 image address
+ * [2] BL33-2 image address
+ * [3] BL33-3 image address
+ * [4] BL33-4 image address
+ * [5] BL33-5 image address
+ * [6] BL33-6 image address
+ * [7] BL33-7 image address
+ * [8] BL33-8 image address
+ */
offset = name == EMMC_DEV_ID ? RCAR_EMMC_CERT_HEADER :
RCAR_FLASH_CERT_HEADER;
rc = io_seek(handle, IO_SEEK_SET, offset);
@@ -447,8 +456,9 @@
rcar_cert_load = RCAR_CERT_LOAD;
error:
- if (rc != IO_SUCCESS)
+ if (rc != IO_SUCCESS) {
rc = IO_FAIL;
+ }
io_close(handle);
@@ -464,13 +474,15 @@
uint32_t noload, cert, len;
int32_t rc;
- /* Only one file open at a time. We need to track state (ie, file
- * cursor position). Since the header lives at * offset zero, this entry
+ /*
+ * Only one file open at a time. We need to track state (ie, file
+ * cursor position). Since the header lives at offset zero, this entry
* should never be zero in an active file.
* Once the system supports dynamic memory allocation we will allow more
- * than one open file at a time. */
+ * than one open file at a time.
+ */
if (current_file.offset != 0U) {
- WARN("rcar_file_open : Only one open file at a time.\n");
+ WARN("%s: Only one open file at a time.\n", __func__);
return IO_RESOURCES_EXHAUSTED;
}
@@ -480,7 +492,7 @@
return IO_FAIL;
}
- if (noload) {
+ if (noload != 0U) {
current_file.offset = 1;
current_file.dst = 0;
current_file.size = 1;
@@ -494,12 +506,10 @@
rcar_read_certificate((uint64_t) cert, &len, &dst);
- /*----------------*
- * Baylibre: HACK *
- *----------------*/
- if (BL31_IMAGE_ID == spec->offset && len < RCAR_TRUSTED_SRAM_SIZE) {
- WARN("r-car ignoring the BL31 size from certificate,"
- "using RCAR_TRUSTED_SRAM_SIZE instead\n");
+ /* Baylibre: HACK */
+ if (spec->offset == BL31_IMAGE_ID && len < RCAR_TRUSTED_SRAM_SIZE) {
+ WARN("%s,%s\n", "r-car ignoring the BL31 size from certificate",
+ "using RCAR_TRUSTED_SRAM_SIZE instead");
len = RCAR_TRUSTED_SRAM_SIZE;
}
@@ -536,7 +546,7 @@
#else
static uint32_t load_bl33x_counter;
#endif
- if (current_file.no_load) {
+ if (current_file.no_load != 0U) {
*cnt = length;
return IO_SUCCESS;
}
@@ -551,14 +561,14 @@
rc = io_seek(handle, IO_SEEK_SET, offset);
if (rc != IO_SUCCESS) {
- WARN("rcar_file_read: failed to seek\n");
+ WARN("%s: failed to seek\n", __func__);
goto error;
}
if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33) {
rc = check_load_area(buffer, length);
if (rc != IO_SUCCESS) {
- WARN("rcar_file_read: load area err\n");
+ WARN("%s: load area err\n", __func__);
goto error;
}
}
@@ -573,8 +583,9 @@
io_close(handle);
load_bl33x_counter += 1;
- if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33X)
+ if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33X) {
return load_bl33x();
+ }
return IO_SUCCESS;
error:
@@ -584,8 +595,9 @@
static int32_t rcar_file_close(io_entity_t *entity)
{
- if (current_file.offset)
+ if (current_file.offset != 0U) {
memset(¤t_file, 0, sizeof(current_file));
+ }
entity->info = 0U;
@@ -634,8 +646,9 @@
int32_t result;
result = io_register_device(&rcar_dev_info);
- if (result == IO_SUCCESS)
+ if (result == IO_SUCCESS) {
*dev_con = &rcar_dev_connector;
+ }
return result;
}
diff --git a/drivers/renesas/rcar/io/io_rcar.h b/drivers/renesas/common/io/io_rcar.h
similarity index 100%
rename from drivers/renesas/rcar/io/io_rcar.h
rename to drivers/renesas/common/io/io_rcar.h
diff --git a/drivers/renesas/rcar/pfc/pfc_regs.h b/drivers/renesas/common/pfc_regs.h
similarity index 100%
rename from drivers/renesas/rcar/pfc/pfc_regs.h
rename to drivers/renesas/common/pfc_regs.h
diff --git a/drivers/renesas/rcar/pwrc/call_sram.S b/drivers/renesas/common/pwrc/call_sram.S
similarity index 100%
rename from drivers/renesas/rcar/pwrc/call_sram.S
rename to drivers/renesas/common/pwrc/call_sram.S
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/common/pwrc/pwrc.c
similarity index 75%
rename from drivers/renesas/rcar/pwrc/pwrc.c
rename to drivers/renesas/common/pwrc/pwrc.c
index 2ce6b61..c0f015f 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/common/pwrc/pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,10 +16,10 @@
#include <plat/common/platform.h>
#include "iic_dvfs.h"
-#include "rcar_def.h"
-#include "rcar_private.h"
#include "micro_delay.h"
#include "pwrc.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
/*
* Someday there will be a generic power controller api. At the moment each
@@ -27,105 +27,105 @@
*/
RCAR_INSTANTIATE_LOCK
-#define WUP_IRQ_SHIFT (0U)
-#define WUP_FIQ_SHIFT (8U)
-#define WUP_CSD_SHIFT (16U)
-#define BIT_SOFTRESET (1U<<15)
-#define BIT_CA53_SCU (1U<<21)
-#define BIT_CA57_SCU (1U<<12)
-#define REQ_RESUME (1U<<1)
-#define REQ_OFF (1U<<0)
-#define STATUS_PWRUP (1U<<4)
-#define STATUS_PWRDOWN (1U<<0)
-#define STATE_CA57_CPU (27U)
-#define STATE_CA53_CPU (22U)
-#define MODE_L2_DOWN (0x00000002U)
-#define CPU_PWR_OFF (0x00000003U)
-#define RCAR_PSTR_MASK (0x00000003U)
-#define ST_ALL_STANDBY (0x00003333U)
+#define WUP_IRQ_SHIFT (0U)
+#define WUP_FIQ_SHIFT (8U)
+#define WUP_CSD_SHIFT (16U)
+#define BIT_SOFTRESET (1U << 15)
+#define BIT_CA53_SCU (1U << 21)
+#define BIT_CA57_SCU (1U << 12)
+#define REQ_RESUME (1U << 1)
+#define REQ_OFF (1U << 0)
+#define STATUS_PWRUP (1U << 4)
+#define STATUS_PWRDOWN (1U << 0)
+#define STATE_CA57_CPU (27U)
+#define STATE_CA53_CPU (22U)
+#define MODE_L2_DOWN (0x00000002U)
+#define CPU_PWR_OFF (0x00000003U)
+#define RCAR_PSTR_MASK (0x00000003U)
+#define ST_ALL_STANDBY (0x00003333U)
/* Suspend to ram */
-#define DBSC4_REG_BASE (0xE6790000U)
-#define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
-#define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
-#define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
-#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
-#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
-#define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
-#define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
-#define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
-#define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
-#define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
-#define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
-#define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
-#define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
-#define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
-#define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
-#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
-#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
-#define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
-#define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
-#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
-#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
-#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
-#define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
-#define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
-#define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
-#define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
-#define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
-#define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
-#define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
-#define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
-#define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
-#define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
-#define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
-#define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
-#define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
-#define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
-#define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
-#define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
-#define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
-#define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
-#define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
-#define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
-#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
-#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
-#define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
-#define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
-#define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
-#define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
-#define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
-#define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
-#define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
-#define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
-#define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
-#define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-#define RST_MODEMR_BIT0 (0x00000001U)
+#define DBSC4_REG_BASE (0xE6790000U)
+#define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
+#define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
+#define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
+#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
+#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
+#define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
+#define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
+#define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
+#define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
+#define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
+#define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
+#define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
+#define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
+#define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
+#define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
+#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
+#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
+#define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
+#define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
+#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
+#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
+#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
+#define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
+#define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
+#define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
+#define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
+#define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
+#define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
+#define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
+#define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
+#define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
+#define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
+#define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
+#define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
+#define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
+#define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
+#define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
+#define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
+#define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
+#define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
+#define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
+#define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
+#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
+#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
+#define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
+#define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
+#define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
+#define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
+#define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
+#define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
+#define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
+#define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
+#define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
+#define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
+#define RST_BASE (0xE6160000U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
+#define RST_MODEMR_BIT0 (0x00000001U)
#define RCAR_CNTCR_OFF (0x00U)
#define RCAR_CNTCVL_OFF (0x08U)
@@ -136,17 +136,17 @@
#define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U)
#if PMIC_ROHM_BD9571
-#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
-#define PMIC_BKUP_MODE_CNT (0x20U)
-#define PMIC_QLLM_CNT (0x27U)
-#define PMIC_RETRY_MAX (100U)
-#endif
-#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
-#define RCAR_CA53CPU_NUM_MAX (4U)
-#define RCAR_CA57CPU_NUM_MAX (4U)
-#define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
-#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
-#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
+#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
+#define PMIC_BKUP_MODE_CNT (0x20U)
+#define PMIC_QLLM_CNT (0x27U)
+#define PMIC_RETRY_MAX (100U)
+#endif /* PMIC_ROHM_BD9571 */
+#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
+#define RCAR_CA53CPU_NUM_MAX (4U)
+#define RCAR_CA57CPU_NUM_MAX (4U)
+#define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
+#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
+#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
#ifndef __ASSEMBLER__
IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
@@ -320,11 +320,13 @@
c = rcar_pwrc_get_mpidr_cluster(mpidr);
dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
- if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
+ if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
goto done;
+ }
- if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
+ if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) {
goto done;
+ }
/* all of the CPUs in the cluster is in the CoreStandby mode */
mmio_write_32(dst, MODE_L2_DOWN);
@@ -343,7 +345,7 @@
rcar_pwrc_saved_cntfid =
mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
}
-#endif
+#endif /* RCAR_SYSTEM_SUSPEND */
void rcar_pwrc_restore_timer_state(void)
{
@@ -372,10 +374,10 @@
}
#endif /* PMIC_ROHM_BD9571 */
-#define RST_CA53_CPU0_BARH (0xE6160080U)
-#define RST_CA53_CPU0_BARL (0xE6160084U)
-#define RST_CA57_CPU0_BARH (0xE61600C0U)
-#define RST_CA57_CPU0_BARL (0xE61600C4U)
+#define RST_CA53_CPU0_BARH (0xE6160080U)
+#define RST_CA53_CPU0_BARL (0xE6160084U)
+#define RST_CA57_CPU0_BARH (0xE61600C0U)
+#define RST_CA57_CPU0_BARL (0xE61600C4U)
void rcar_pwrc_setup(void)
{
@@ -427,11 +429,13 @@
product = reg & PRR_PRODUCT_MASK;
cut = reg & PRR_CUT_MASK;
- if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
+ if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
goto self_refresh;
+ }
- if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
+ if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) {
goto self_refresh;
+ }
mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
@@ -509,7 +513,7 @@
}
static void __attribute__ ((section(".system_ram")))
- rcar_pwrc_set_self_refresh_e3(void)
+rcar_pwrc_set_self_refresh_e3(void)
{
uint32_t ddr_md;
uint32_t reg;
@@ -533,8 +537,10 @@
while (mmio_read_32(DBSC4_REG_DBWAIT))
;
- /* Set the auto-refresh enable register */
- /* Set the ARFEN bit to 0 in the DBRFEN */
+ /*
+ * Set the auto-refresh enable register
+ * Set the ARFEN bit to 0 in the DBRFEN
+ */
mmio_write_32(DBSC4_REG_DBRFEN, 0);
mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
@@ -638,7 +644,7 @@
}
void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
- rcar_pwrc_go_suspend_to_ram(void)
+rcar_pwrc_go_suspend_to_ram(void)
{
#if PMIC_ROHM_BD9571
int32_t rc = -1, qllm = -1;
@@ -713,7 +719,7 @@
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
if (error) {
- ERROR("Failed send KEEP10 init ret=%d \n", error);
+ ERROR("Failed send KEEP10 init ret=%d\n", error);
return;
}
#endif
@@ -835,7 +841,6 @@
uint64_t my_cpu;
int32_t rtn;
uint32_t my_cluster_type;
-
const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
RCAR_CLUSTER_CA53,
RCAR_CLUSTER_CA57
@@ -861,6 +866,6 @@
}
}
}
- return (rtn);
+ return rtn;
}
diff --git a/drivers/renesas/rcar/pwrc/pwrc.h b/drivers/renesas/common/pwrc/pwrc.h
similarity index 89%
rename from drivers/renesas/rcar/pwrc/pwrc.h
rename to drivers/renesas/common/pwrc/pwrc.h
index 2b81783..f73099b 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.h
+++ b/drivers/renesas/common/pwrc/pwrc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,12 +31,12 @@
#define WKUP_PPONR 0x2
#define WKUP_GICREQ 0x3
-#define RCAR_INVALID (0xffffffffU)
+#define RCAR_INVALID (0xffffffffU)
#define PSYSR_INVALID 0xffffffff
-#define RCAR_CLUSTER_A53A57 (0U)
-#define RCAR_CLUSTER_CA53 (1U)
-#define RCAR_CLUSTER_CA57 (2U)
+#define RCAR_CLUSTER_A53A57 (0U)
+#define RCAR_CLUSTER_CA53 (1U)
+#define RCAR_CLUSTER_CA57 (2U)
#ifndef __ASSEMBLER__
void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr);
diff --git a/drivers/renesas/rcar/qos/qos_reg.h b/drivers/renesas/common/qos_reg.h
similarity index 100%
rename from drivers/renesas/rcar/qos/qos_reg.h
rename to drivers/renesas/common/qos_reg.h
diff --git a/drivers/renesas/rcar/rom/rom_api.c b/drivers/renesas/common/rom/rom_api.c
similarity index 100%
rename from drivers/renesas/rcar/rom/rom_api.c
rename to drivers/renesas/common/rom/rom_api.c
diff --git a/drivers/renesas/rcar/rom/rom_api.h b/drivers/renesas/common/rom/rom_api.h
similarity index 100%
rename from drivers/renesas/rcar/rom/rom_api.h
rename to drivers/renesas/common/rom/rom_api.h
diff --git a/drivers/renesas/rcar/rpc/rpc_driver.c b/drivers/renesas/common/rpc/rpc_driver.c
similarity index 100%
rename from drivers/renesas/rcar/rpc/rpc_driver.c
rename to drivers/renesas/common/rpc/rpc_driver.c
diff --git a/drivers/renesas/rcar/rpc/rpc_registers.h b/drivers/renesas/common/rpc/rpc_registers.h
similarity index 100%
rename from drivers/renesas/rcar/rpc/rpc_registers.h
rename to drivers/renesas/common/rpc/rpc_registers.h
diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/common/scif/scif.S
similarity index 64%
rename from drivers/renesas/rcar/scif/scif.S
rename to drivers/renesas/common/scif/scif.S
index ae26cc4..beb8dd8 100644
--- a/drivers/renesas/rcar/scif/scif.S
+++ b/drivers/renesas/common/scif/scif.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,43 +9,43 @@
#include <console_macros.S>
#include <drivers/renesas/rcar/console/console.h>
-#define SCIF_INTERNAL_CLK 0
-#define SCIF_EXTARNAL_CLK 1
-#define SCIF_CLK SCIF_INTERNAL_CLK
+#define SCIF_INTERNAL_CLK 0
+#define SCIF_EXTARNAL_CLK 1
+#define SCIF_CLK SCIF_INTERNAL_CLK
/* product register */
-#define PRR (0xFFF00044)
-#define PRR_PRODUCT_MASK (0x00007F00)
-#define PRR_CUT_MASK (0x000000FF)
-#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
-#define PRR_PRODUCT_E3 (0x00005700)
-#define PRR_PRODUCT_D3 (0x00005800)
+#define PRR (0xFFF00044)
+#define PRR_PRODUCT_MASK (0x00007F00)
+#define PRR_CUT_MASK (0x000000FF)
+#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
+#define PRR_PRODUCT_E3 (0x00005700)
+#define PRR_PRODUCT_D3 (0x00005800)
/* module stop */
-#define CPG_BASE (0xE6150000)
-#define CPG_SMSTPCR2 (0x0138)
-#define CPG_SMSTPCR3 (0x013C)
+#define CPG_BASE (0xE6150000)
+#define CPG_SMSTPCR2 (0x0138)
+#define CPG_SMSTPCR3 (0x013C)
#define CPG_MSTPSR2 (0x0040)
-#define CPG_MSTPSR3 (0x0048)
-#define MSTP207 (1 << 7)
-#define MSTP310 (1 << 10)
-#define CPG_CPGWPR (0x0900)
+#define CPG_MSTPSR3 (0x0048)
+#define MSTP207 (1 << 7)
+#define MSTP310 (1 << 10)
+#define CPG_CPGWPR (0x0900)
/* scif */
-#define SCIF0_BASE (0xE6E60000)
-#define SCIF2_BASE (0xE6E88000)
-#define SCIF_SCSMR (0x00)
-#define SCIF_SCBRR (0x04)
-#define SCIF_SCSCR (0x08)
-#define SCIF_SCFTDR (0x0C)
-#define SCIF_SCFSR (0x10)
-#define SCIF_SCFRDR (0x14)
-#define SCIF_SCFCR (0x18)
-#define SCIF_SCFDR (0x1C)
-#define SCIF_SCSPTR (0x20)
-#define SCIF_SCLSR (0x24)
-#define SCIF_DL (0x30)
-#define SCIF_CKS (0x34)
+#define SCIF0_BASE (0xE6E60000)
+#define SCIF2_BASE (0xE6E88000)
+#define SCIF_SCSMR (0x00)
+#define SCIF_SCBRR (0x04)
+#define SCIF_SCSCR (0x08)
+#define SCIF_SCFTDR (0x0C)
+#define SCIF_SCFSR (0x10)
+#define SCIF_SCFRDR (0x14)
+#define SCIF_SCFCR (0x18)
+#define SCIF_SCFDR (0x1C)
+#define SCIF_SCSPTR (0x20)
+#define SCIF_SCLSR (0x24)
+#define SCIF_DL (0x30)
+#define SCIF_CKS (0x34)
#if RCAR_LSI == RCAR_V3M
#define SCIF_BASE SCIF0_BASE
@@ -60,70 +60,71 @@
#endif
/* mode pin */
-#define RST_MODEMR (0xE6160060)
-#define MODEMR_MD12 (0x00001000)
+#define RST_MODEMR (0xE6160060)
+#define MODEMR_MD12 (0x00001000)
-#define SCSMR_CA_MASK (1 << 7)
-#define SCSMR_CA_ASYNC (0x0000)
-#define SCSMR_CHR_MASK (1 << 6)
-#define SCSMR_CHR_8 (0x0000)
-#define SCSMR_PE_MASK (1 << 5)
-#define SCSMR_PE_DIS (0x0000)
-#define SCSMR_STOP_MASK (1 << 3)
-#define SCSMR_STOP_1 (0x0000)
-#define SCSMR_CKS_MASK (3 << 0)
-#define SCSMR_CKS_DIV1 (0x0000)
-#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
+#define SCSMR_CA_MASK (1 << 7)
+#define SCSMR_CA_ASYNC (0x0000)
+#define SCSMR_CHR_MASK (1 << 6)
+#define SCSMR_CHR_8 (0x0000)
+#define SCSMR_PE_MASK (1 << 5)
+#define SCSMR_PE_DIS (0x0000)
+#define SCSMR_STOP_MASK (1 << 3)
+#define SCSMR_STOP_1 (0x0000)
+#define SCSMR_CKS_MASK (3 << 0)
+#define SCSMR_CKS_DIV1 (0x0000)
+#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + \
SCSMR_CHR_8 + \
SCSMR_PE_DIS + \
SCSMR_STOP_1 + \
SCSMR_CKS_DIV1)
-#define SCBRR_115200BPS (17)
-#define SCBRR_115200BPSON (16)
-#define SCBRR_115200BPS_E3_SSCG (15)
-#define SCBRR_230400BPS (8)
+#define SCBRR_115200BPS (17)
+#define SCBRR_115200BPSON (16)
+#define SCBRR_115200BPS_E3_SSCG (15)
+#define SCBRR_230400BPS (8)
-#define SCSCR_TE_MASK (1 << 5)
-#define SCSCR_TE_DIS (0x0000)
-#define SCSCR_TE_EN (0x0020)
-#define SCSCR_RE_MASK (1 << 4)
-#define SCSCR_RE_DIS (0x0000)
-#define SCSCR_RE_EN (0x0010)
-#define SCSCR_CKE_MASK (3 << 0)
-#define SCSCR_CKE_INT (0x0000)
-#define SCSCR_CKE_BRG (0x0002)
+#define SCSCR_TE_MASK (1 << 5)
+#define SCSCR_TE_DIS (0x0000)
+#define SCSCR_TE_EN (0x0020)
+#define SCSCR_RE_MASK (1 << 4)
+#define SCSCR_RE_DIS (0x0000)
+#define SCSCR_RE_EN (0x0010)
+#define SCSCR_CKE_MASK (3 << 0)
+#define SCSCR_CKE_INT (0x0000)
+#define SCSCR_CKE_BRG (0x0002)
#if SCIF_CLK == SCIF_EXTARNAL_CLK
-#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
+#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
#else
-#define SCFSR_TEND_MASK (1 << 6)
-#define SCFSR_TEND_TRANS_END (0x0040)
-#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
+#define SCFSR_TEND_MASK (1 << 6)
+#define SCFSR_TEND_TRANS_END (0x0040)
+#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
#endif
-#define SCFSR_INIT_DATA (0x0000)
-#define SCFCR_TTRG_MASK (3 << 4)
-#define SCFCR_TTRG_8 (0x0000)
-#define SCFCR_TTRG_0 (0x0030)
-#define SCFCR_TFRST_MASK (1 << 2)
-#define SCFCR_TFRST_DIS (0x0000)
-#define SCFCR_TFRST_EN (0x0004)
-#define SCFCR_RFRS_MASK (1 << 1)
-#define SCFCR_RFRS_DIS (0x0000)
-#define SCFCR_RFRS_EN (0x0002)
-#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
-#define SCFDR_T_MASK (0x1f << 8)
-#define DL_INIT_DATA (8)
-#define CKS_CKS_DIV_MASK (1 << 15)
-#define CKS_CKS_DIV_CLK (0x0000)
-#define CKS_XIN_MASK (1 << 14)
-#define CKS_XIN_SCIF_CLK (0x0000)
-#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
+#define SCFSR_INIT_DATA (0x0000)
+#define SCFCR_TTRG_MASK (3 << 4)
+#define SCFCR_TTRG_8 (0x0000)
+#define SCFCR_TTRG_0 (0x0030)
+#define SCFCR_TFRST_MASK (1 << 2)
+#define SCFCR_TFRST_DIS (0x0000)
+#define SCFCR_TFRST_EN (0x0004)
+#define SCFCR_RFRS_MASK (1 << 1)
+#define SCFCR_RFRS_DIS (0x0000)
+#define SCFCR_RFRS_EN (0x0002)
+#define SCFCR_INIT_DATA (SCFCR_TTRG_8)
+#define SCFDR_T_MASK (0x1f << 8)
+#define DL_INIT_DATA (8)
+#define CKS_CKS_DIV_MASK (1 << 15)
+#define CKS_CKS_DIV_CLK (0x0000)
+#define CKS_XIN_MASK (1 << 14)
+#define CKS_XIN_SCIF_CLK (0x0000)
+#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
.globl console_rcar_register
.globl console_rcar_init
.globl console_rcar_putc
.globl console_rcar_flush
- /* -----------------------------------------------
+ /*
+ * -----------------------------------------------
* int console_rcar_register(
* uintptr_t base, uint32_t clk, uint32_t baud,
* console_t *console)
@@ -154,7 +155,7 @@
ret x7
endfunc console_rcar_register
- /* -----------------------------------------------
+ /*
* int console_rcar_init(unsigned long base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
@@ -166,7 +167,6 @@
* w2 - Baud rate
* Out: return 1 on success
* Clobber list : x1, x2
- * -----------------------------------------------
*/
func console_rcar_init
ldr x0, =CPG_BASE
@@ -188,8 +188,10 @@
ldrh w1, [x0, #SCIF_SCFCR]
orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN)
strh w1, [x0, #SCIF_SCFCR]
- /* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
- in SCLSR, then clear them to 0 */
+ /*
+ * Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
+ * in SCLSR, then clear them to 0
+ */
mov w1, #SCFSR_INIT_DATA
strh w1, [x0, #SCIF_SCFSR]
mov w1, #0
@@ -265,7 +267,7 @@
ret
endfunc console_rcar_init
- /* --------------------------------------------------------
+ /*
* int console_rcar_putc(int c, unsigned int base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
@@ -273,7 +275,6 @@
* x1 - pointer to console_t structure
* Out : return -1 on error else return character.
* Clobber list : x2
- * --------------------------------------------------------
*/
func console_rcar_putc
ldr x1, =SCIF_BASE
@@ -304,12 +305,11 @@
ret
endfunc console_rcar_putc
- /* ---------------------------------------------
+ /*
* void console_rcar_flush(void)
* Function to force a write of all buffered
* data that hasn't been output. It returns void
* Clobber list : x0, x1
- * ---------------------------------------------
*/
func console_rcar_flush
ldr x0, =SCIF_BASE
diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/common/watchdog/swdt.c
similarity index 96%
rename from drivers/renesas/rcar/watchdog/swdt.c
rename to drivers/renesas/common/watchdog/swdt.c
index 111e651..05987ab 100644
--- a/drivers/renesas/rcar/watchdog/swdt.c
+++ b/drivers/renesas/common/watchdog/swdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -162,6 +162,6 @@
gicv2_end_of_interrupt(ARM_IRQ_SEC_WDT);
rcar_swdt_release();
ERROR("\n");
- ERROR("System WDT overflow, occured address is %p\n", (void *)p);
+ ERROR("System WDT overflow, occurred address is %p\n", (void *)p);
panic();
}
diff --git a/drivers/renesas/rcar/common.c b/drivers/renesas/rcar/common.c
deleted file mode 100644
index 42bdce5..0000000
--- a/drivers/renesas/rcar/common.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-
-#include "rcar_private.h"
-
-void
-#if IMAGE_BL31
- __attribute__ ((section(".system_ram")))
-#endif
- cpg_write(uintptr_t regadr, uint32_t regval)
-{
- uint32_t value = (regval);
- mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
- mmio_write_32(regadr, value);
-}
-
-void
-#if IMAGE_BL31
- __attribute__ ((section(".system_ram")))
-#endif
- mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
-{
- uint32_t reg;
- reg = mmio_read_32(mstpcr);
- reg &= ~target_bit;
- cpg_write(mstpcr, reg);
- while ((mmio_read_32(mstpsr) & target_bit) != 0U) {
- }
-}
diff --git a/drivers/renesas/rcar/emmc/emmc_config.h b/drivers/renesas/rcar/emmc/emmc_config.h
deleted file mode 100644
index 686ccb9..0000000
--- a/drivers/renesas/rcar/emmc/emmc_config.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/**
- * @file emmc_config.h
- * @brief Configuration file
- *
- */
-
-#ifndef EMMC_CONFIG_H
-#define EMMC_CONFIG_H
-
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-
-/** @brief MMC driver config
- */
-#define EMMC_RCA 1UL /* RCA */
-#define EMMC_RW_DATA_TIMEOUT 0x40UL /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
-#define EMMC_RETRY_COUNT 0 /* how many times to try after fail. Don't change. */
-#define EMMC_CMD_MAX 60UL /* Don't change. */
-
-/** @brief etc
- */
-#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL
-
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-
-/* ********************************* CODE ********************************** */
-
-#endif /* EMMC_CONFIG_H */
-/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_hal.h b/drivers/renesas/rcar/emmc/emmc_hal.h
deleted file mode 100644
index f0b7e9d..0000000
--- a/drivers/renesas/rcar/emmc/emmc_hal.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/**
- * @file emmc_hal.h
- * @brief emmc boot driver is expecting this header file
- *
- */
-
-#ifndef EMMC_HAL_H
-#define EMMC_HAL_H
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-#include <stdint.h>
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-
-/** @brief memory card error/status types
- */
-#define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L
-#define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L
-#define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L
-#define HAL_MEMCARD_ERASE_SEQ_ERROR 0x10000000L
-#define HAL_MEMCARD_ERASE_PARAM 0x08000000L
-#define HAL_MEMCARD_WP_VIOLATION 0x04000000L
-#define HAL_MEMCARD_CARD_IS_LOCKED 0x02000000L
-#define HAL_MEMCARD_LOCK_UNLOCK_FAILED 0x01000000L
-#define HAL_MEMCARD_COM_CRC_ERROR 0x00800000L
-#define HAL_MEMCARD_ILEGAL_COMMAND 0x00400000L
-#define HAL_MEMCARD_CARD_ECC_FAILED 0x00200000L
-#define HAL_MEMCARD_CC_ERROR 0x00100000L
-#define HAL_MEMCARD_ERROR 0x00080000L
-#define HAL_MEMCARD_UNDERRUN 0x00040000L
-#define HAL_MEMCARD_OVERRUN 0x00020000L
-#define HAL_MEMCARD_CIDCSD_OVERWRITE 0x00010000L
-#define HAL_MEMCARD_WP_ERASE_SKIP 0x00008000L
-#define HAL_MEMCARD_CARD_ECC_DISABLED 0x00004000L
-#define HAL_MEMCARD_ERASE_RESET 0x00002000L
-#define HAL_MEMCARD_CARD_STATE 0x00001E00L
-#define HAL_MEMCARD_CARD_READY_FOR_DATA 0x00000100L
-#define HAL_MEMCARD_APP_CMD 0x00000020L
-#define HAL_MEMCARD_SWITCH_ERROR 0x00000080L
-#define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L
-#define HAL_MEMCARD_NO_ERRORS 0x00000000L
-
-/** @brief Memory card response types
- */
-#define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f
-
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/** @brief Type of the return value.
- */
-typedef enum {
- HAL_MEMCARD_FAIL = 0U,
- HAL_MEMCARD_OK = 1U,
- HAL_MEMCARD_DMA_ALLOC_FAIL = 2U, /**< DMA channel allocation failed */
- HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U, /**< DMA transfer failed */
- HAL_MEMCARD_CARD_STATUS_ERROR = 4U, /**< A non-masked error bit was set in the card status */
- HAL_MEMCARD_CMD_TIMEOUT = 5U, /**< Command timeout occurred */
- HAL_MEMCARD_DATA_TIMEOUT = 6U, /**< Data timeout occurred */
- HAL_MEMCARD_CMD_CRC_ERROR = 7U, /**< Command CRC error occurred */
- HAL_MEMCARD_DATA_CRC_ERROR = 8U /**< Data CRC error occurred */
-} HAL_MEMCARD_RETURN;
-
-/** @brief memory access operation
- */
-typedef enum {
- HAL_MEMCARD_READ = 0U, /**< read */
- HAL_MEMCARD_WRITE = 1U /**< write */
-} HAL_MEMCARD_OPERATION;
-
-/** @brief Type of data width on memorycard bus
- */
-typedef enum {
- HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
- HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
- HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
-} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */
-
-/** @brief Presence of the memory card
- */
-typedef enum {
- HAL_MEMCARD_CARD_IS_IN = 0U,
- HAL_MEMCARD_CARD_IS_OUT = 1U
-} HAL_MEMCARD_PRESENCE_STATUS; /* presence status of the memory card */
-
-/** @brief mode of data transfer
- */
-typedef enum {
- HAL_MEMCARD_DMA = 0U,
- HAL_MEMCARD_NOT_DMA = 1U
-} HAL_MEMCARD_DATA_TRANSFER_MODE;
-
-/** @brief Memory card response types.
- */
-typedef enum hal_memcard_response_type {
- HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
- HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
- HAL_MEMCARD_RESPONSE_R1b = 0x00200U,
- HAL_MEMCARD_RESPONSE_R2 = 0x00300U,
- HAL_MEMCARD_RESPONSE_R3 = 0x00400U,
- HAL_MEMCARD_RESPONSE_R4 = 0x00500U,
- HAL_MEMCARD_RESPONSE_R5 = 0x00600U,
- HAL_MEMCARD_RESPONSE_R6 = 0x00700U,
- HAL_MEMCARD_RESPONSE_R7 = 0x00800U,
- HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
-} HAL_MEMCARD_RESPONSE_TYPE;
-
-/** @brief Memory card command types.
- */
-typedef enum hal_memcard_command_type {
- HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
- HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
- HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U,
- HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U,
- HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U,
- HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
-} HAL_MEMCARD_COMMAND_TYPE;
-
-/** @brief Type of memory card
- */
-typedef enum hal_memcard_command_card_type {
- HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
- HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U,
- HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
-} HAL_MEMCARD_COMMAND_CARD_TYPE;
-
-/** @brief Memory card application command.
- */
-typedef enum hal_memcard_command_app_norm {
- HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
- HAL_MEMCARD_COMMAND_APP = 0x20000U,
- HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
-} HAL_MEMCARD_COMMAND_APP_NORM;
-
-/** @brief Memory card command codes.
- */
-typedef enum {
-/* class 0 and class 1 */
- CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */
- CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */
- CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */
- CMD2_ALL_SEND_CID_SD =
- 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */
- CMD3_SEND_RELATIVE_ADDR =
- 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */
- CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */
- CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */
- CMD6_SWITCH_FUNC =
- 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- ACMD6_SET_BUS_WIDTH =
- 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */
- CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */
- CMD7_DESELECT_CARD =
- 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,
- CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */
- CMD8_SEND_IF_COND =
- 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */
- CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */
- CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */
- CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */
- CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12(R1b : write case) */
- CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */
- ACMD13_SD_STATUS =
- 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */
- CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */
-
-/* class 2 */
- CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */
- CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */
- CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */
- CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */
-
-/* class 3 */
- CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */
- CMD21 = 21, /* CMD21 */
- CMD22 = 22, /* CMD22 */
- ACMD22_SEND_NUM_WR_BLOCKS =
- 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
-
-/* class 4 */
- CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD23 */
- ACMD23_SET_WR_BLK_ERASE_COUNT =
- 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD24_WRITE_BLOCK = 24 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD24 */
- CMD25_WRITE_MULTIPLE_BLOCK = 25 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD25 */
- CMD26_PROGRAM_CID = 26 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD26 */
- CMD27_PROGRAM_CSD = 27 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD27 */
-
-/* class 6 */
- CMD28_SET_WRITE_PROT = 28 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD28 */
- CMD29_CLR_WRITE_PROT = 29 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD29 */
- CMD30_SEND_WRITE_PROT = 30 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD30 */
- CMD30_SEND_WRITE_PROT_TYPE = 31 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD31 */
-
-/* class 5 */
- CMD32_ERASE_WR_BLK_START = 32 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD32 */
- CMD33_ERASE_WR_BLK_END = 33 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD33 */
- CMD34 = 34, /* CMD34 */
- CMD35_ERASE_GROUP_START = 35 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD35 */
- CMD36_ERASE_GROUP_END = 36 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD36 */
- CMD37 = 37, /* CMD37 */
- CMD38_ERASE = 38 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD38 */
-
-/* class 9 */
- CMD39_FASTIO = 39 | HAL_MEMCARD_RESPONSE_R4 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD39 */
- CMD40_GO_IRQSTATE = 40 | HAL_MEMCARD_RESPONSE_R5 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD40 */
- CMD41 = 41, /* CMD41 */
- ACMD41_SD_SEND_OP_COND =
- 41 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
-
-/* class 7 */
- CMD42_LOCK_UNLOCK = 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD42 */
- ACMD42_SET_CLR_CARD_DETECT =
- 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD43 = 43, /* CMD43 */
- CMD44 = 44, /* CMD44 */
- CMD45 = 45, /* CMD45 */
- CMD46 = 46, /* CMD46 */
- CMD47 = 47, /* CMD47 */
- CMD48 = 48, /* CMD48 */
- CMD49 = 49, /* CMD49 */
- CMD50 = 50, /* CMD50 */
- CMD51 = 51, /* CMD51 */
- ACMD51_SEND_SCR =
- 51 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD52 = 52, /* CMD52 */
- CMD53 = 53, /* CMD53 */
- CMD54 = 54, /* CMD54 */
-
-/* class 8 */
- CMD55_APP_CMD = 55 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD55 */
- CMD56_GEN_CMD = 56 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD56 */
- CMD57 = 57, /* CMD57 */
- CMD58 = 58, /* CMD58 */
- CMD59 = 59, /* CMD59 */
- CMD60 = 60, /* CMD60 */
- CMD61 = 61, /* CMD61 */
- CMD62 = 62, /* CMD62 */
- CMD63 = 63 /* CMD63 */
-} HAL_MEMCARD_COMMAND;
-
-/** @brief Configuration structure from HAL layer.
- *
- * If some field is not available it should be filled with 0xFF.
- * The API version is 32-bit unsigned integer telling the version of the API. The integer is divided to four sections which each can be treated as a 8-bit unsigned number:
- * Bits 31-24 make the most significant part of the version number. This number starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This number changes only, if the API itself changes so much that it is not compatible anymore with older releases.
- * Bits 23-16 API minor version number. For example API version 2.1 would be 0x0201xxxx.
- * Bits 15-8 are the number of the year when release is done. The 0 is year 2000, 1 is year 2001 and so on
- * Bits 7- are the week number when release is done. First full week of the year is 1
- *
- * @note Example: let's assume that release 2.1 is done on week 10 year 2008 the version will get the value 0x0201080A
- */
-typedef struct {
- /**
- * Version of the chipset API implementation
- *
- * bits [31:24] API specification major version number.<br>
- * bits [23:16] API specification minor version number.<br>
- * bits [15:8] API implemention year. (2000 = 0, 2001 = 1, ...)<br>
- * bits [7:0] API implemention week.<br>
- * Example: API specification version 4.0, implementation w46 2008 => 0x0400082E
- */
- uint32_t api_version;
-
- /** maximum block count which can be transferred at once */
- uint32_t max_block_count;
-
- /** maximum clock frequence in Hz supported by HW */
- uint32_t max_clock_freq;
-
- /** maximum data bus width supported by HW */
- uint16_t max_data_width;
-
- /** Is high-speed mode supported by HW (yes=1, no=0) */
- uint8_t hs_mode_supported;
-
- /** Is memory card removable (yes=1, no=0) */
- uint8_t card_removable;
-
-} HAL_MEMCARD_HW_CONF;
-
-/** @brief Configuration structure to HAL layer.
- */
-typedef struct {
- /** how many times to try after fail, for instance sending command */
- uint32_t retries_after_fail;
-} HAL_MEMCARD_INIT_CONF;
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-
-/* ********************************* CODE ********************************** */
-
-#endif /* EMMC_HAL_H */
-
-/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_registers.h b/drivers/renesas/rcar/emmc/emmc_registers.h
deleted file mode 100644
index 55ff33d..0000000
--- a/drivers/renesas/rcar/emmc/emmc_registers.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/**
- * @file emmc_registers.h
- * @brief emmc boot driver is expecting this header file. HS-MMC module header file.
- *
- */
-
-#ifndef EMMC_REGISTERS_H
-#define EMMC_REGISTERS_H
-
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-
-/* MMC channel select */
-#define MMC_CH0 (0U) /* SDHI2/MMC0 */
-#define MMC_CH1 (1U) /* SDHI3/MMC1 */
-
-#if RCAR_LSI == RCAR_E3
-#define USE_MMC_CH (MMC_CH1) /* R-Car E3 */
-#else /* RCAR_LSI == RCAR_E3 */
-#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
-#endif /* RCAR_LSI == RCAR_E3 */
-
-#define BIT0 (0x00000001U)
-#define BIT1 (0x00000002U)
-#define BIT2 (0x00000004U)
-#define BIT3 (0x00000008U)
-#define BIT4 (0x00000010U)
-#define BIT5 (0x00000020U)
-#define BIT6 (0x00000040U)
-#define BIT7 (0x00000080U)
-#define BIT8 (0x00000100U)
-#define BIT9 (0x00000200U)
-#define BIT10 (0x00000400U)
-#define BIT11 (0x00000800U)
-#define BIT12 (0x00001000U)
-#define BIT13 (0x00002000U)
-#define BIT14 (0x00004000U)
-#define BIT15 (0x00008000U)
-#define BIT16 (0x00010000U)
-#define BIT17 (0x00020000U)
-#define BIT18 (0x00040000U)
-#define BIT19 (0x00080000U)
-#define BIT20 (0x00100000U)
-#define BIT21 (0x00200000U)
-#define BIT22 (0x00400000U)
-#define BIT23 (0x00800000U)
-#define BIT24 (0x01000000U)
-#define BIT25 (0x02000000U)
-#define BIT26 (0x04000000U)
-#define BIT27 (0x08000000U)
-#define BIT28 (0x10000000U)
-#define BIT29 (0x20000000U)
-#define BIT30 (0x40000000U)
-#define BIT31 (0x80000000U)
-
-/** @brief Clock Pulse Generator (CPG) registers
- */
-#define CPG_BASE (0xE6150000U)
-
-#define CPG_MSTPSR3 (CPG_BASE+0x0048U) /* Module stop status register 3 */
-
-#define CPG_SMSTPCR3 (CPG_BASE+0x013CU) /* System module stop control register 3 */
-
-#define CPG_SD2CKCR (CPG_BASE+0x0268U) /* SDHI2 clock frequency control register */
-#define CPG_SD3CKCR (CPG_BASE+0x026CU) /* SDHI3 clock frequency control register */
-
-#define CPG_CPGWPR (CPG_BASE+0x0900U) /* CPG Write Protect Register */
-
-#if USE_MMC_CH == MMC_CH0
-#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
-#else /* USE_MMC_CH == MMC_CH0 */
-#define CPG_SDxCKCR (CPG_SD3CKCR) /* SDHI3/MMC1 */
-#endif /* USE_MMC_CH == MMC_CH0 */
-
-/** Boot Status register
- */
-#define MFISBTSTSR (0xE6260604U)
-
-#define MFISBTSTSR_BOOT_PARTITION (0x00000010U)
-
-/** brief eMMC registers
- */
-#define MMC0_SD_BASE (0xEE140000U)
-#define MMC1_SD_BASE (0xEE160000U)
-
-#if USE_MMC_CH == MMC_CH0
-#define MMC_SD_BASE (MMC0_SD_BASE)
-#else /* USE_MMC_CH == MMC_CH0 */
-#define MMC_SD_BASE (MMC1_SD_BASE)
-#endif /* USE_MMC_CH == MMC_CH0 */
-
-#define SD_CMD (MMC_SD_BASE + 0x0000U)
-#define SD_PORTSEL (MMC_SD_BASE + 0x0008U)
-#define SD_ARG (MMC_SD_BASE + 0x0010U)
-#define SD_ARG1 (MMC_SD_BASE + 0x0018U)
-#define SD_STOP (MMC_SD_BASE + 0x0020U)
-#define SD_SECCNT (MMC_SD_BASE + 0x0028U)
-#define SD_RSP10 (MMC_SD_BASE + 0x0030U)
-#define SD_RSP1 (MMC_SD_BASE + 0x0038U)
-#define SD_RSP32 (MMC_SD_BASE + 0x0040U)
-#define SD_RSP3 (MMC_SD_BASE + 0x0048U)
-#define SD_RSP54 (MMC_SD_BASE + 0x0050U)
-#define SD_RSP5 (MMC_SD_BASE + 0x0058U)
-#define SD_RSP76 (MMC_SD_BASE + 0x0060U)
-#define SD_RSP7 (MMC_SD_BASE + 0x0068U)
-#define SD_INFO1 (MMC_SD_BASE + 0x0070U)
-#define SD_INFO2 (MMC_SD_BASE + 0x0078U)
-#define SD_INFO1_MASK (MMC_SD_BASE + 0x0080U)
-#define SD_INFO2_MASK (MMC_SD_BASE + 0x0088U)
-#define SD_CLK_CTRL (MMC_SD_BASE + 0x0090U)
-#define SD_SIZE (MMC_SD_BASE + 0x0098U)
-#define SD_OPTION (MMC_SD_BASE + 0x00A0U)
-#define SD_ERR_STS1 (MMC_SD_BASE + 0x00B0U)
-#define SD_ERR_STS2 (MMC_SD_BASE + 0x00B8U)
-#define SD_BUF0 (MMC_SD_BASE + 0x00C0U)
-#define SDIO_MODE (MMC_SD_BASE + 0x00D0U)
-#define SDIO_INFO1 (MMC_SD_BASE + 0x00D8U)
-#define SDIO_INFO1_MASK (MMC_SD_BASE + 0x00E0U)
-#define CC_EXT_MODE (MMC_SD_BASE + 0x0360U)
-#define SOFT_RST (MMC_SD_BASE + 0x0380U)
-#define VERSION (MMC_SD_BASE + 0x0388U)
-#define HOST_MODE (MMC_SD_BASE + 0x0390U)
-#define DM_CM_DTRAN_MODE (MMC_SD_BASE + 0x0820U)
-#define DM_CM_DTRAN_CTRL (MMC_SD_BASE + 0x0828U)
-#define DM_CM_RST (MMC_SD_BASE + 0x0830U)
-#define DM_CM_INFO1 (MMC_SD_BASE + 0x0840U)
-#define DM_CM_INFO1_MASK (MMC_SD_BASE + 0x0848U)
-#define DM_CM_INFO2 (MMC_SD_BASE + 0x0850U)
-#define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U)
-#define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U)
-
-/** @brief SD_INFO1 Registers
- */
-#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */
-#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */
-#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */
-#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */
-#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */
-#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */
-#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */
-#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */
-#define SD_INFO1_INFO2 0x00000004UL /* Access end */
-#define SD_INFO1_INFO0 0x00000001UL /* Response end */
-
-/** @brief SD_INFO2 Registers
- */
-#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */
-#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */
-#define SD_INFO2_SCLKDIVEN 0x00002000UL
-#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */
-#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */
-#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */
-#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */
-#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */
-#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */
-#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */
-#define SD_INFO2_ERR2 0x00000004UL /* END Error */
-#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */
-#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */
-#define SD_INFO2_ALL_ERR 0x0000807FUL
-#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 The write value should always be 1. HWM_0003 */
-
-/** @brief SOFT_RST
- */
-#define SOFT_RST_SDRST 0x00000001UL
-
-/** @brief SD_CLK_CTRL
- */
-#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL
-#define SD_CLK_CTRL_SCLKEN 0x00000100UL
-#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL
-#define SD_CLOCK_ENABLE 0x00000100UL
-#define SD_CLOCK_DISABLE 0x00000000UL
-#define SD_CLK_WRITE_MASK 0x000003FFUL
-#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL
-
-/** @brief SD_OPTION
- */
-#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL
-
-/** @brief MMC Clock Frequency
- * 200MHz * 1/x = output clock
- */
-#define MMC_CLK_OFF 0UL /* Clock output is disabled */
-#define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */
-#define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
-#define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz */
-#define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz */
-#define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */
-#define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */
-
-#define MMC_FREQ_52MHZ 52000000UL
-#define MMC_FREQ_26MHZ 26000000UL
-#define MMC_FREQ_20MHZ 20000000UL
-
-/** @brief MMC Clock DIV
- */
-#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */
-#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
-#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */
-#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */
-#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */
-#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */
-#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */
-#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */
-#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */
-#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */
-#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */
-#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */
-
-/** @brief DM_CM_DTRAN_MODE
- */
-#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */
-#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */
-#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL
-
-/** @brief CC_EXT_MODE
- */
-#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */
-#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */
-
-/** @brief DM_CM_INFO_MASK
- */
-#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL
-#define DM_CM_INFO_CH0_ENABLE 0x00010001UL
-#define DM_CM_INFO_CH1_ENABLE 0x00020001UL
-
-/** @brief DM_DTRAN_ADDR
- */
-#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL
-
-/** @brief DM_CM_DTRAN_CTRL
- */
-#define DM_CM_DTRAN_CTRL_START 0x00000001UL
-
-/** @brief SYSC Registers
- */
-#if USE_MMC_CH == MMC_CH0
-#define CPG_MSTP_MMC (BIT12) /* SDHI2/MMC0 */
-#else /* USE_MMC_CH == MMC_CH0 */
-#define CPG_MSTP_MMC (BIT11) /* SDHI3/MMC1 */
-#endif /* USE_MMC_CH == MMC_CH0 */
-
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-
-/* ********************************* CODE ********************************** */
-
-#endif /* EMMC_REGISTERS_H */
-/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_std.h b/drivers/renesas/rcar/emmc/emmc_std.h
deleted file mode 100644
index 99cb6b9..0000000
--- a/drivers/renesas/rcar/emmc/emmc_std.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/**
- * @file emmc_std.h
- * @brief eMMC boot is expecting this header file
- *
- */
-
-#ifndef EMMC_STD_H
-#define EMMC_STD_H
-
-#include "emmc_hal.h"
-
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-#ifndef FALSE
-#define FALSE 0U
-#endif
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-/** @brief 64bit registers
- **/
-#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v))
-#define GETR_64(r) (*(volatile uint64_t *)(r))
-
-/** @brief 32bit registers
- **/
-#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v))
-#define GETR_32(r) (*(volatile uint32_t *)(r))
-
-/** @brief 16bit registers
- */
-#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v))
-#define GETR_16(r) (*(volatile uint16_t *)(r))
-
-/** @brief 8bit registers
- */
-#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v))
-#define GETR_8(r) (*(volatile uint8_t *)(r))
-
-/** @brief CSD register Macros
- */
-#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y)))
-
-#define EMMC_CID_MID() (EMMC_GET_CID(127, 120))
-#define EMMC_CID_CBX() (EMMC_GET_CID(113, 112))
-#define EMMC_CID_OID() (EMMC_GET_CID(111, 104))
-#define EMMC_CID_PNM1() (EMMC_GET_CID(103, 88))
-#define EMMC_CID_PNM2() (EMMC_GET_CID(87, 56))
-#define EMMC_CID_PRV() (EMMC_GET_CID(55, 48))
-#define EMMC_CID_PSN() (EMMC_GET_CID(47, 16))
-#define EMMC_CID_MDT() (EMMC_GET_CID(15, 8))
-#define EMMC_CID_CRC() (EMMC_GET_CID(7, 1))
-
-/** @brief CSD register Macros
- */
-#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y)))
-
-#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126))
-#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122))
-#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112))
-#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104))
-#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96))
-#define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84))
-#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80))
-#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79))
-#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78))
-#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77))
-#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76))
-#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62))
-#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59))
-#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56))
-#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53))
-#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50))
-#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47))
-#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42))
-#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37))
-#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32))
-#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31))
-#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29))
-#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26))
-#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22))
-#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21))
-#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16))
-#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15))
-#define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14))
-#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13))
-#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12))
-#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10))
-#define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8))
-#define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1))
-
-/** @brief for sector access
- */
-#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003
-#define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */
-#define EMMC_SECTOR_SIZE 512
-#define EMMC_BLOCK_LENGTH 512
-#define EMMC_BLOCK_LENGTH_DW 128
-#define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */
-
-/** @brief eMMC specification clock
- */
-#define EMMC_CLOCK_SPEC_400K 400000UL /**< initialize clock 400KHz */
-#define EMMC_CLOCK_SPEC_20M 20000000UL /**< normal speed 20MHz */
-#define EMMC_CLOCK_SPEC_26M 26000000UL /**< high speed 26MHz */
-#define EMMC_CLOCK_SPEC_52M 52000000UL /**< high speed 52MHz */
-#define EMMC_CLOCK_SPEC_100M 100000000UL /**< high speed 100MHz */
-
-/** @brief EMMC driver error code. (extended HAL_MEMCARD_RETURN)
- */
-typedef enum {
- EMMC_ERR = 0, /**< unknown error */
- EMMC_SUCCESS, /**< OK */
- EMMC_ERR_FROM_DMAC, /**< DMAC allocation error */
- EMMC_ERR_FROM_DMAC_TRANSFER, /**< DMAC transfer error */
- EMMC_ERR_CARD_STATUS_BIT, /**< card status error. Non-masked error bit was set in the card status */
- EMMC_ERR_CMD_TIMEOUT, /**< command timeout error */
- EMMC_ERR_DATA_TIMEOUT, /**< data timeout error */
- EMMC_ERR_CMD_CRC, /**< command CRC error */
- EMMC_ERR_DATA_CRC, /**< data CRC error */
- EMMC_ERR_PARAM, /**< parameter error */
- EMMC_ERR_RESPONSE, /**< response error */
- EMMC_ERR_RESPONSE_BUSY, /**< response busy error */
- EMMC_ERR_TRANSFER, /**< data transfer error */
- EMMC_ERR_READ_SECTOR, /**< read sector error */
- EMMC_ERR_WRITE_SECTOR, /**< write sector error */
- EMMC_ERR_STATE, /**< state error */
- EMMC_ERR_TIMEOUT, /**< timeout error */
- EMMC_ERR_ILLEGAL_CARD, /**< illegal card */
- EMMC_ERR_CARD_BUSY, /**< Busy state */
- EMMC_ERR_CARD_STATE, /**< card state error */
- EMMC_ERR_SET_TRACE, /**< trace information error */
- EMMC_ERR_FROM_TIMER, /**< Timer error */
- EMMC_ERR_FORCE_TERMINATE, /**< Force terminate */
- EMMC_ERR_CARD_POWER, /**< card power fail */
- EMMC_ERR_ERASE_SECTOR, /**< erase sector error */
- EMMC_ERR_INFO2 /**< exec cmd error info2 */
-} EMMC_ERROR_CODE;
-
-/** @brief Function number */
-#define EMMC_FUNCNO_NONE 0U
-#define EMMC_FUNCNO_DRIVER_INIT 1U
-#define EMMC_FUNCNO_CARD_POWER_ON 2U
-#define EMMC_FUNCNO_MOUNT 3U
-#define EMMC_FUNCNO_CARD_INIT 4U
-#define EMMC_FUNCNO_HIGH_SPEED 5U
-#define EMMC_FUNCNO_BUS_WIDTH 6U
-#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U
-#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U
-#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U
-#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U
-#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U
-#define EMMC_FUNCNO_SET_CLOCK 12U
-#define EMMC_FUNCNO_EXEC_CMD 13U
-#define EMMC_FUNCNO_READ_SECTOR 14U
-#define EMMC_FUNCNO_WRITE_SECTOR 15U
-#define EMMC_FUNCNO_ERASE_SECTOR 16U
-#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U
-/** @brief Response
- */
-/** R1 */
-#define EMMC_R1_ERROR_MASK 0xFDBFE080U /* Type 'E' bit and bit14(must be 0). ignore bit22 */
-#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */
-#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */
-#define EMMC_R1_READY 0x00000100U /* bit8 */
-#define EMMC_R1_STATE_SHIFT 9
-
-/** R4 */
-#define EMMC_R4_RCA_MASK 0xFFFF0000UL
-#define EMMC_R4_STATUS 0x00008000UL
-
-/** CSD */
-#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */
-#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0
-#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */
-#define EMMC_TRANSPEED_MULT_SHIFT 3
-
-/** OCR */
-#define EMMC_HOST_OCR_VALUE 0x40FF8080
-#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */
-#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */
-#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L
-#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L
-
-/** EXT_CSD */
-#define EMMC_EXT_CSD_S_CMD_SET 504
-#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241
-#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239
-#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238
-#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235
-#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234
-#define EMMC_EXT_CSD_TRIM_MULT 232
-#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231
-#define EMMC_EXT_CSD_SEC_ERASE_MULT 229
-#define EMMC_EXT_CSD_BOOT_INFO 228
-#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226
-#define EMMC_EXT_CSD_ACC_SIZE 225
-#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224
-#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223
-#define EMMC_EXT_CSD_PEL_WR_SEC_C 222
-#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221
-#define EMMC_EXT_CSD_S_C_VCC 220
-#define EMMC_EXT_CSD_S_C_VCCQ 219
-#define EMMC_EXT_CSD_S_A_TIMEOUT 217
-#define EMMC_EXT_CSD_SEC_COUNT 215
-#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210
-#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209
-#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208
-#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207
-#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206
-#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205
-#define EMMC_EXT_CSD_PWR_CL_26_360 203
-#define EMMC_EXT_CSD_PWR_CL_52_360 202
-#define EMMC_EXT_CSD_PWR_CL_26_195 201
-#define EMMC_EXT_CSD_PWR_CL_52_195 200
-#define EMMC_EXT_CSD_CARD_TYPE 196
-#define EMMC_EXT_CSD_CSD_STRUCTURE 194
-#define EMMC_EXT_CSD_EXT_CSD_REV 192
-#define EMMC_EXT_CSD_CMD_SET 191
-#define EMMC_EXT_CSD_CMD_SET_REV 189
-#define EMMC_EXT_CSD_POWER_CLASS 187
-#define EMMC_EXT_CSD_HS_TIMING 185
-#define EMMC_EXT_CSD_BUS_WIDTH 183
-#define EMMC_EXT_CSD_ERASED_MEM_CONT 181
-#define EMMC_EXT_CSD_PARTITION_CONFIG 179
-#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178
-#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177
-#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175
-#define EMMC_EXT_CSD_BOOT_WP 173
-#define EMMC_EXT_CSD_USER_WP 171
-#define EMMC_EXT_CSD_FW_CONFIG 169
-#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168
-#define EMMC_EXT_CSD_RST_n_FUNCTION 162
-#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160
-#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159
-#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156
-#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155
-#define EMMC_EXT_CSD_GP_SIZE_MULT 154
-#define EMMC_EXT_CSD_ENH_SIZE_MULT 142
-#define EMMC_EXT_CSD_ENH_START_ADDR 139
-#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134
-
-#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01
-#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02
-#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04
-#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08
-#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e
-
-/** SWITCH (CMD6) argument */
-#define EXTCSD_ACCESS_BYTE (BIT25|BIT24)
-#define EXTCSD_SET_BITS BIT24
-
-#define HS_TIMING_ADD (185<<16) /* H'b9 */
-#define HS_TIMING_1 (1<<8)
-#define HS_TIMING_HS200 (2<<8)
-#define HS_TIMING_HS400 (3<<8)
-
-#define BUS_WIDTH_ADD (183<<16) /* H'b7 */
-#define BUS_WIDTH_1 (0<<8)
-#define BUS_WIDTH_4 (1<<8)
-#define BUS_WIDTH_8 (2<<8)
-#define BUS_WIDTH_4DDR (5<<8)
-#define BUS_WIDTH_8DDR (6<<8)
-
-#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */
-#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD) /**< H'03b90000 */
-
-#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */
-#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4) /**< H'03b70100 */
-#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8) /**< H'03b70200 */
-#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4DDR) /**< H'03b70500 */
-#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8DDR) /**< H'03b70600 */
-#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL /**< Partition config = 0x00 */
-
-#define TIMING_HIGH_SPEED 1UL
-#define EMMC_BOOT_PARTITION_EN_MASK 0x38U
-#define EMMC_BOOT_PARTITION_EN_SHIFT 3U
-
-/** Bus width */
-#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT
-#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT
-#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT
-
-/** for st_mmc_base */
-#define EMMC_MAX_RESPONSE_LENGTH 17
-#define EMMC_MAX_CID_LENGTH 16
-#define EMMC_MAX_CSD_LENGTH 16
-#define EMMC_MAX_EXT_CSD_LENGTH 512U
-#define EMMC_RES_REG_ALIGNED 4U
-#define EMMC_BUF_REG_ALIGNED 8U
-
-/** @brief for TAAC mask
- */
-#define TAAC_TIME_UNIT_MASK (0x07)
-#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F)
-
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/** @brief Partition id
- */
-typedef enum {
- PARTITION_ID_USER = 0x0, /**< User Area */
- PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */
- PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */
- PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */
- PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */
- PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */
- PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */
- PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */
- PARTITION_ID_MASK = 0x7 /**< [2:0] */
-} EMMC_PARTITION_ID;
-
-/** @brief card state in R1 response [12:9]
- */
-typedef enum {
- EMMC_R1_STATE_IDLE = 0,
- EMMC_R1_STATE_READY,
- EMMC_R1_STATE_IDENT,
- EMMC_R1_STATE_STBY,
- EMMC_R1_STATE_TRAN,
- EMMC_R1_STATE_DATA,
- EMMC_R1_STATE_RCV,
- EMMC_R1_STATE_PRG,
- EMMC_R1_STATE_DIS,
- EMMC_R1_STATE_BTST,
- EMMC_R1_STATE_SLEP
-} EMMC_R1_STATE;
-
-typedef enum {
- ESTATE_BEGIN = 0,
- ESTATE_ISSUE_CMD,
- ESTATE_NON_RESP_CMD,
- ESTATE_RCV_RESP,
- ESTATE_RCV_RESPONSE_BUSY,
- ESTATE_CHECK_RESPONSE_COMPLETE,
- ESTATE_DATA_TRANSFER,
- ESTATE_DATA_TRANSFER_COMPLETE,
- ESTATE_ACCESS_END,
- ESTATE_TRANSFER_ERROR,
- ESTATE_ERROR,
- ESTATE_END
-} EMMC_INT_STATE;
-
-/** @brief eMMC boot driver error information
- */
-typedef struct {
- uint16_t num; /**< error no */
- uint16_t code; /**< error code */
- volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */
- volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */
- volatile uint32_t status1;/**< SD_ERR_STS1 register value. (hardware dependence) */
- volatile uint32_t status2;/**< SD_ERR_STS2 register value. (hardware dependence) */
- volatile uint32_t dm_info1;/**< DM_CM_INFO1 register value. (hardware dependence) */
- volatile uint32_t dm_info2;/**< DM_CM_INFO2 register value. (hardware dependence) */
-} st_error_info;
-
-/** @brief Command information
- */
-typedef struct {
- HAL_MEMCARD_COMMAND cmd; /**< Command information */
- uint32_t arg; /**< argument */
- HAL_MEMCARD_OPERATION dir; /**< direction */
- uint32_t hw; /**< H/W dependence. SD_CMD register value. */
-} st_command_info;
-
-/** @brief MMC driver base
- */
-typedef struct {
- st_error_info error_info; /**< error information */
- st_command_info cmd_info; /**< command information */
-
- /* for data transfer */
- uint32_t *buff_address_virtual; /**< Dest or Src buff */
- uint32_t *buff_address_physical; /**< Dest or Src buff */
- HAL_MEMCARD_DATA_WIDTH bus_width;
- /**< bus width */
- uint32_t trans_size; /**< transfer size for this command */
- uint32_t remain_size; /**< remain size for this command */
- uint32_t response_length; /**< response length for this command */
- uint32_t sector_size; /**< sector_size */
-
- /* clock */
- uint32_t base_clock; /**< MMC host controller clock */
- uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
- uint32_t request_freq; /**< request freq [Hz] (400K, 26MHz, 52MHz, etc) */
- uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */
-
- /* state flag */
- HAL_MEMCARD_PRESENCE_STATUS card_present;
- /**< presence status of the memory card */
- uint32_t card_power_enable; /**< True : Power ON */
- uint32_t clock_enable; /**< True : Clock ON */
- uint32_t initialize; /**< True : initialize complete. */
- uint32_t access_mode; /**< True : sector access, FALSE : byte access */
- uint32_t mount; /**< True : mount complete. */
- uint32_t selected; /**< True : selected card. */
- HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;
- /**< 0: DMA, 1:PIO */
- uint32_t image_num; /**< loaded ISSW image No. ISSW have copy image. */
- EMMC_R1_STATE current_state; /**< card state */
- volatile uint32_t during_cmd_processing; /**< True : during command processing */
- volatile uint32_t during_transfer; /**< True : during transfer */
- volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/
- volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */
- volatile uint32_t force_terminate; /**< force terminate flag */
- volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
- volatile uint32_t get_partition_access_flag;
- /**< True : get partition access processing */
-
- EMMC_PARTITION_ID boot_partition_en; /**< Boot partition */
- EMMC_PARTITION_ID partition_access; /**< Current access partition */
-
- /* timeout */
- uint32_t hs_timing; /**< high speed */
-
- /* timeout */
- uint32_t data_timeout; /**< read and write data timeout.*/
-
- /* retry */
- uint32_t retries_after_fail; /**< how many times to try after fail, for instance sending command */
-
- /* interrupt */
- volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
- volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */
- volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */
- volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */
-
- /* response */
- uint32_t *response; /**< pointer to buffer for executing command. */
- uint32_t r1_card_status; /**< R1 response data */
- uint32_t r3_ocr; /**< R3 response data */
- uint32_t r4_resp; /**< R4 response data */
- uint32_t r5_resp; /**< R5 response data */
-
- uint32_t low_clock_mode_enable;
- /**< True : clock mode is low. (MMC clock = Max26MHz) */
- uint32_t reserved2;
- uint32_t reserved3;
- uint32_t reserved4;
-
- /* CSD registers (4byte align) */
- uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /**< CSD */
- __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
- /* CID registers (4byte align) */
- uint8_t cid_data[EMMC_MAX_CID_LENGTH] /**< CID */
- __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
- /* EXT CSD registers (8byte align) */
- uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /**< EXT_CSD */
- __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED)));
- /* Response registers (4byte align) */
- uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /**< other response */
- __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
-} st_mmc_base;
-
-typedef int (*func) (void);
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-uint32_t emmc_get_csd_time(void);
-
-#define MMC_DEBUG
-/* ********************************* CODE ********************************** */
-
-/* ******************************** END ************************************ */
-#endif /* EMMC_STD_H */
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h
deleted file mode 100644
index 2dec58f..0000000
--- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef IIC_DVFS_H
-#define IIC_DVFS_H
-
-/* PMIC slave */
-#define PMIC (0x30)
-#define BKUP_MODE_CNT (0x20)
-#define DVFS_SET_VID (0x54)
-#define REG_KEEP10 (0x79)
-
-/* EEPROM slave */
-#define EEPROM (0x50)
-#define BOARD_ID (0x70)
-
-int32_t rcar_iic_dvfs_receive(uint8_t slave, uint8_t reg, uint8_t *data);
-int32_t rcar_iic_dvfs_send(uint8_t slave, uint8_t regr, uint8_t data);
-
-#endif /* IIC_DVFS_H */
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts
index 2218b2a..699dc23 100644
--- a/fdts/morello-fvp.dts
+++ b/fdts/morello-fvp.dts
@@ -80,8 +80,14 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
};
+ virtio_net@1c180000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x1c180000 0x0 0x200>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
virtio_rng@1c190000 {
- compatible = "virtio,mmio","virtio-rng";
+ compatible = "virtio,mmio";
reg = <0x0 0x1c190000 0x0 0x200>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/fdts/tc0.dts b/fdts/tc0.dts
index 15c14ca..5438474 100644
--- a/fdts/tc0.dts
+++ b/fdts/tc0.dts
@@ -106,7 +106,18 @@
memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x80000000>;
+ reg = <0x0 0x80000000 0x0 0x7d000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ optee@0xfce00000 {
+ reg = <0x00000000 0xfce00000 0 0x00200000>;
+ no-map;
+ };
};
psci {
@@ -370,4 +381,17 @@
};
};
};
+
+ ffa {
+ compatible = "arm,ffa";
+ conduit = "smc";
+ mem_share_buffer = "tx";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "ffa";
+ };
+ };
};
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index db8938f..c30073b 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -102,6 +102,11 @@
/* CSSELR definitions */
#define LEVEL_SHIFT U(1)
+/* ID_DFR1_EL1 definitions */
+#define ID_DFR1_MTPMU_SHIFT U(0)
+#define ID_DFR1_MTPMU_MASK U(0xf)
+#define ID_DFR1_MTPMU_SUPPORTED U(1)
+
/* ID_MMFR4 definitions */
#define ID_MMFR4_CNP_SHIFT U(12)
#define ID_MMFR4_CNP_LENGTH U(4)
@@ -126,6 +131,9 @@
#define ID_PFR1_GENTIMER_MASK U(0xf)
#define ID_PFR1_GIC_SHIFT U(28)
#define ID_PFR1_GIC_MASK U(0xf)
+#define ID_PFR1_SEC_SHIFT U(4)
+#define ID_PFR1_SEC_MASK U(0xf)
+#define ID_PFR1_ELx_ENABLED U(1)
/* SCTLR definitions */
#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
@@ -164,6 +172,7 @@
#define SDCR_SCCD_BIT (U(1) << 23)
#define SDCR_SPME_BIT (U(1) << 17)
#define SDCR_RESET_VAL U(0x0)
+#define SDCR_MTPME_BIT (U(1) << 28)
/* HSCTLR definitions */
#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
@@ -244,6 +253,7 @@
#define VTTBR_BADDR_SHIFT U(0)
/* HDCR definitions */
+#define HDCR_MTPME_BIT (U(1) << 28)
#define HDCR_HLP_BIT (U(1) << 26)
#define HDCR_HPME_BIT (U(1) << 7)
#define HDCR_RESET_VAL U(0x0)
@@ -503,6 +513,7 @@
#define CTR p15, 0, c0, c0, 1
#define CNTFRQ p15, 0, c14, c0, 0
#define ID_MMFR4 p15, 0, c0, c2, 6
+#define ID_DFR1 p15, 0, c0, c3, 5
#define ID_PFR0 p15, 0, c0, c1, 0
#define ID_PFR1 p15, 0, c0, c1, 1
#define MAIR0 p15, 0, c10, c2, 0
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index 94cf7ea..82efb18 100644
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -166,7 +166,7 @@
#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
static inline void _op ## _type(void) \
{ \
- __asm__ (#_op " " #_type); \
+ __asm__ (#_op " " #_type : : : "memory"); \
}
/* Define function for system instruction with register parameter */
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index 4fd746d..580dd95 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -242,6 +242,10 @@
cps #MODE32_mon
isb
+#if DISABLE_MTPMU
+ bl mtpmu_disable
+#endif
+
.if \_warm_boot_mailbox
/* -------------------------------------------------------------
* This code will be executed for both warm and cold resets.
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 33e1134..09e598a 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -188,6 +188,11 @@
#define ID_AA64DFR0_PMS_SHIFT U(32)
#define ID_AA64DFR0_PMS_MASK ULL(0xf)
+/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
+#define ID_AA64DFR0_MTPMU_SHIFT U(48)
+#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
+#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
+
/* ID_AA64ISAR1_EL1 definitions */
#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
#define ID_AA64ISAR1_GPI_SHIFT U(28)
@@ -243,6 +248,13 @@
#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
+#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
+#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
+#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
+#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
+
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@@ -266,9 +278,17 @@
#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
-#define MTE_UNIMPLEMENTED ULL(0)
-#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
-#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
+/* Memory Tagging Extension is not implemented */
+#define MTE_UNIMPLEMENTED U(0)
+/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
+#define MTE_IMPLEMENTED_EL0 U(1)
+/* FEAT_MTE2: Full MTE is implemented */
+#define MTE_IMPLEMENTED_ELX U(2)
+/*
+ * FEAT_MTE3: MTE is implemented with support for
+ * asymmetric Tag Check Fault handling
+ */
+#define MTE_IMPLEMENTED_ASY U(3)
#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
@@ -286,6 +306,7 @@
#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
(UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
+
#define SCTLR_AARCH32_EL1_RES1 \
((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
(U(1) << 4) | (U(1) << 3))
@@ -300,9 +321,12 @@
#define SCTLR_SA_BIT (ULL(1) << 3)
#define SCTLR_SA0_BIT (ULL(1) << 4)
#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
+#define SCTLR_nAA_BIT (ULL(1) << 6)
#define SCTLR_ITD_BIT (ULL(1) << 7)
#define SCTLR_SED_BIT (ULL(1) << 8)
#define SCTLR_UMA_BIT (ULL(1) << 9)
+#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
+#define SCTLR_EOS_BIT (ULL(1) << 11)
#define SCTLR_I_BIT (ULL(1) << 12)
#define SCTLR_EnDB_BIT (ULL(1) << 13)
#define SCTLR_DZE_BIT (ULL(1) << 14)
@@ -310,21 +334,65 @@
#define SCTLR_NTWI_BIT (ULL(1) << 16)
#define SCTLR_NTWE_BIT (ULL(1) << 18)
#define SCTLR_WXN_BIT (ULL(1) << 19)
-#define SCTLR_UWXN_BIT (ULL(1) << 20)
+#define SCTLR_TSCXT_BIT (ULL(1) << 20)
#define SCTLR_IESB_BIT (ULL(1) << 21)
+#define SCTLR_EIS_BIT (ULL(1) << 22)
+#define SCTLR_SPAN_BIT (ULL(1) << 23)
#define SCTLR_E0E_BIT (ULL(1) << 24)
#define SCTLR_EE_BIT (ULL(1) << 25)
#define SCTLR_UCI_BIT (ULL(1) << 26)
#define SCTLR_EnDA_BIT (ULL(1) << 27)
+#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
+#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
#define SCTLR_EnIB_BIT (ULL(1) << 30)
#define SCTLR_EnIA_BIT (ULL(1) << 31)
#define SCTLR_BT0_BIT (ULL(1) << 35)
#define SCTLR_BT1_BIT (ULL(1) << 36)
#define SCTLR_BT_BIT (ULL(1) << 36)
+#define SCTLR_ITFSB_BIT (ULL(1) << 37)
+#define SCTLR_TCF0_SHIFT U(38)
+#define SCTLR_TCF0_MASK ULL(3)
+
+/* Tag Check Faults in EL0 have no effect on the PE */
+#define SCTLR_TCF0_NO_EFFECT U(0)
+/* Tag Check Faults in EL0 cause a synchronous exception */
+#define SCTLR_TCF0_SYNC U(1)
+/* Tag Check Faults in EL0 are asynchronously accumulated */
+#define SCTLR_TCF0_ASYNC U(2)
+/*
+ * Tag Check Faults in EL0 cause a synchronous exception on reads,
+ * and are asynchronously accumulated on writes
+ */
+#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
+
+#define SCTLR_TCF_SHIFT U(40)
+#define SCTLR_TCF_MASK ULL(3)
+
+/* Tag Check Faults in EL1 have no effect on the PE */
+#define SCTLR_TCF_NO_EFFECT U(0)
+/* Tag Check Faults in EL1 cause a synchronous exception */
+#define SCTLR_TCF_SYNC U(1)
+/* Tag Check Faults in EL1 are asynchronously accumulated */
+#define SCTLR_TCF_ASYNC U(2)
+/*
+ * Tag Check Faults in EL1 cause a synchronous exception on reads,
+ * and are asynchronously accumulated on writes
+ */
+#define SCTLR_TCF_SYNCR_ASYNCW U(3)
+
+#define SCTLR_ATA0_BIT (ULL(1) << 42)
+#define SCTLR_ATA_BIT (ULL(1) << 43)
#define SCTLR_DSSBS_BIT (ULL(1) << 44)
+#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
+#define SCTLR_TWEDEL_SHIFT U(46)
+#define SCTLR_TWEDEL_MASK ULL(0xf)
+#define SCTLR_EnASR_BIT (ULL(1) << 54)
+#define SCTLR_EnAS0_BIT (ULL(1) << 55)
+#define SCTLR_EnALS_BIT (ULL(1) << 56)
+#define SCTLR_EPAN_BIT (ULL(1) << 57)
#define SCTLR_RESET_VAL SCTLR_EL3_RES1
-/* CPACR_El1 definitions */
+/* CPACR_EL1 definitions */
#define CPACR_EL1_FPEN(x) ((x) << 20)
#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
@@ -358,6 +426,7 @@
#define SCR_RESET_VAL SCR_RES1_BITS
/* MDCR_EL3 definitions */
+#define MDCR_MTPME_BIT (ULL(1) << 28)
#define MDCR_SCCD_BIT (ULL(1) << 23)
#define MDCR_SPME_BIT (ULL(1) << 17)
#define MDCR_SDD_BIT (ULL(1) << 16)
@@ -373,6 +442,7 @@
#define MDCR_EL3_RESET_VAL ULL(0x0)
/* MDCR_EL2 definitions */
+#define MDCR_EL2_MTPME (U(1) << 28)
#define MDCR_EL2_HLP (U(1) << 26)
#define MDCR_EL2_HCCD (U(1) << 23)
#define MDCR_EL2_TTRF (U(1) << 19)
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 1f2f4a9..5d1bc94 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -80,7 +80,7 @@
#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
static inline void _op ## _type(void) \
{ \
- __asm__ (#_op " " #_type); \
+ __asm__ (#_op " " #_type : : : "memory"); \
}
/* Define function for system instruction with register parameter */
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 6f4143c..f759983 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -277,6 +277,10 @@
isb
.endif /* _init_sctlr */
+#if DISABLE_MTPMU
+ bl mtpmu_disable
+#endif
+
.if \_warm_boot_mailbox
/* -------------------------------------------------------------
* This code will be executed for both warm and cold resets.
diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h
index 9c0035f..222820b 100644
--- a/include/drivers/allwinner/axp.h
+++ b/include/drivers/allwinner/axp.h
@@ -9,6 +9,10 @@
#include <stdint.h>
+#define AXP20X_MODE_REG 0x3e
+#define AXP20X_MODE_I2C 0x00
+#define AXP20X_MODE_RSB 0x7c
+
#define NA 0xff
enum {
diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h
index 46ba466..30ca910 100644
--- a/include/drivers/cadence/cdns_uart.h
+++ b/include/drivers/cadence/cdns_uart.h
@@ -21,6 +21,7 @@
#define R_UART_SR 0x2C
#define UART_SR_INTR_REMPTY_BIT 1
#define UART_SR_INTR_TFUL_BIT 4
+#define UART_SR_INTR_TEMPTY_BIT 3
#define R_UART_TX 0x30
#define R_UART_RX 0x30
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h
index b522e8e..a61825f 100644
--- a/include/lib/cpus/aarch64/cortex_a76.h
+++ b/include/lib/cpus/aarch64/cortex_a76.h
@@ -20,7 +20,6 @@
#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
-#define CORTEX_A76_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index ed84c0f..0a42a5d 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -17,7 +17,6 @@
******************************************************************************/
#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
-#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
* CPU Power Control register specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 0d4712b..caa5120 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,17 +15,18 @@
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
-#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
-#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
+#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
@@ -33,12 +34,12 @@
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
******************************************************************************/
-#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
-#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
-#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
-#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
+#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
+#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
+#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
+#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
-#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
-#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
+#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
+#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
#endif /* CORTEX_A78_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index 9998b93..b50befa 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -64,12 +64,4 @@
#define CPUPOR_EL3 S3_6_C15_C8_2
#define CPUPMR_EL3 S3_6_C15_C8_3
-/******************************************************************************
- * CPU Configuration register definitions.
- *****************************************************************************/
-#define CPUCFR_EL1 S3_0_C15_C0_0
-
-/* SCU bit of CPU Configuration Register, EL1 */
-#define SCU_SHIFT U(2)
-
#endif /* NEOVERSE_N1_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
new file mode 100644
index 0000000..7cbd8c1
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_N2_H
+#define NEOVERSE_N2_H
+
+/* Neoverse N2 ID register for revision r0p0 */
+#define NEOVERSE_N2_MIDR U(0x410FD490)
+
+/*******************************************************************************
+ * CPU Power control register
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
+#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+
+#endif /* NEOVERSE_N2_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n_common.h b/include/lib/cpus/aarch64/neoverse_n_common.h
new file mode 100644
index 0000000..7cb91cd
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_n_common.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_N_COMMON_H
+#define NEOVERSE_N_COMMON_H
+
+/******************************************************************************
+ * Neoverse Nx CPU Configuration register definitions
+ *****************************************************************************/
+#define CPUCFR_EL1 S3_0_C15_C0_0
+
+/* SCU bit of CPU Configuration Register, EL1 */
+#define SCU_SHIFT U(2)
+
+#endif /* NEOVERSE_N_COMMON_H */
diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h
index 7cac77e..efdedf0 100644
--- a/include/lib/cpus/errata_report.h
+++ b/include/lib/cpus/errata_report.h
@@ -30,4 +30,7 @@
#define ERRATA_APPLIES 1
#define ERRATA_MISSING 2
+/* Macro to get CPU revision code for checking errata version compatibility. */
+#define CPU_REV(r, p) ((r << 4) | p)
+
#endif /* ERRATA_REPORT_H */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index c018643..00746c6 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -497,9 +497,9 @@
# elif defined(SPD_spmd)
# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
-# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
-# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
- + (UL(1) << 21))
+# define BL32_BASE PLAT_ARM_SPMC_BASE
+# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \
+ PLAT_ARM_SPMC_SIZE)
# elif ARM_BL31_IN_DRAM
# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
PLAT_ARM_MAX_BL31_SIZE)
diff --git a/include/plat/arm/common/arm_reclaim_init.ld.S b/include/plat/arm/common/arm_reclaim_init.ld.S
index e4d4f12..717f65e 100644
--- a/include/plat/arm/common/arm_reclaim_init.ld.S
+++ b/include/plat/arm/common/arm_reclaim_init.ld.S
@@ -14,54 +14,30 @@
__INIT_CODE_START__ = .;
*(*text.init*);
__INIT_CODE_END__ = .;
+ INIT_CODE_END_ALIGNED = ALIGN(PAGE_SIZE);
} >RAM
#ifdef BL31_PROGBITS_LIMIT
ASSERT(__INIT_CODE_END__ <= BL31_PROGBITS_LIMIT,
"BL31 init has exceeded progbits limit.")
#endif
-
- ASSERT(__INIT_CODE_END__ <= __STACKS_END__,
- "Init code ends past the end of the stacks")
-
}
-#undef MIN
#define ABS ABSOLUTE
-#define COUNT PLATFORM_CORE_COUNT
-#define ALIGN_MASK ~(CACHE_WRITEBACK_GRANULE - 1)
-#define PRIMARY_STACK \
- __STACKS_START__ = .; \
- *(tzfw_normal_stacks) \
- OFFSET = ABS(SIZEOF(.init) - (. - __STACKS_START__)); \
- /* Offset sign */ \
- SIGN = ABS(OFFSET) & (1 << 63); \
- /* Offset mask */ \
- MASK = ABS(SIGN >> 63) - 1; \
- . += ABS(OFFSET) & ABS(MASK); \
- . = ALIGN(PAGE_SIZE); \
- __STACKS_END__ = .; \
- /* Total stack size */ \
- SIZE = ABS(. - __STACKS_START__); \
- /* Maximum primary CPU stack */ \
- STACK = ABS(__STACKS_START__ + SIZE / COUNT) & ALIGN_MASK; \
- /* Primary CPU stack */ \
- __PRIMARY_STACK__ = MIN(STACK, ABS(__INIT_CODE_START__));
-
-#if (COUNT > 1)
-#define SECONDARY_STACK \
- /* Size of the secondary CPUs' stack */ \
- REST = ABS(__STACKS_END__ - __PRIMARY_STACK__); \
- /* Secondary per-CPU stack size */ \
- __STACK_SIZE__ = ABS(REST / (COUNT - 1));
-#else
-#define SECONDARY_STACK
-#endif
-
-#define STACK_SECTION \
- stacks (NOLOAD) : { \
- PRIMARY_STACK \
- SECONDARY_STACK \
+#define STACK_SECTION \
+ stacks (NOLOAD) : { \
+ __STACKS_START__ = .; \
+ *(tzfw_normal_stacks) \
+ __STACKS_END__ = .; \
+ /* Allow room for the init section where necessary. */ \
+ OFFSET = ABS(SIZEOF(.init) - (. - __STACKS_START__)); \
+ /* Offset sign */ \
+ SIGN = ABS(OFFSET) & (1 << 63); \
+ /* Offset mask */ \
+ MASK = ABS(SIGN >> 63) - 1; \
+ . += ABS(OFFSET) & ABS(MASK); \
+ . = ALIGN(PAGE_SIZE); \
}
+
#endif /* ARM_RECLAIM_INIT_LD_S */
diff --git a/include/plat/arm/common/fconf_arm_sp_getter.h b/include/plat/arm/common/fconf_arm_sp_getter.h
index c6315be..aa628df 100644
--- a/include/plat/arm/common/fconf_arm_sp_getter.h
+++ b/include/plat/arm/common/fconf_arm_sp_getter.h
@@ -13,7 +13,7 @@
/* arm_sp getter */
#define arm__sp_getter(prop) arm_sp.prop
-#define ARM_SP_MAX_SIZE U(0x80000)
+#define ARM_SP_MAX_SIZE U(0xb0000)
#define ARM_SP_OWNER_NAME_LEN U(8)
struct arm_sp_t {
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index 0528916..b6f6c9d 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -486,15 +486,20 @@
* arguments (which is usually the limits of the relocable BL image).
* x0 - the start of the fixup region
* x1 - the limit of the fixup region
- * These addresses have to be page (4KB aligned).
+ * These addresses have to be 4KB page aligned.
* ---------------------------------------------------------------------------
*/
+
+/* Relocation codes */
+#define R_AARCH64_NONE 0
+#define R_AARCH64_RELATIVE 1027
+
func fixup_gdt_reloc
mov x6, x0
mov x7, x1
- /* Test if the limits are 4K aligned */
#if ENABLE_ASSERTIONS
+ /* Test if the limits are 4KB aligned */
orr x0, x0, x1
tst x0, #(PAGE_SIZE_MASK)
ASM_ASSERT(eq)
@@ -505,7 +510,8 @@
* fixup region.
*/
and x2, x30, #~(PAGE_SIZE_MASK)
- sub x0, x2, x6 /* Diff(S) = Current Address - Compiled Address */
+ subs x0, x2, x6 /* Diff(S) = Current Address - Compiled Address */
+ b.eq 3f /* Diff(S) = 0. No relocation needed */
adrp x1, __GOT_START__
add x1, x1, :lo12:__GOT_START__
@@ -518,31 +524,32 @@
* The new_addr is the address currently the binary is executing from
* and old_addr is the address at compile time.
*/
-1:
- ldr x3, [x1]
+1: ldr x3, [x1]
+
/* Skip adding offset if address is < lower limit */
cmp x3, x6
b.lo 2f
+
/* Skip adding offset if address is >= upper limit */
cmp x3, x7
- b.ge 2f
+ b.hs 2f
add x3, x3, x0
str x3, [x1]
-2:
- add x1, x1, #8
+
+2: add x1, x1, #8
cmp x1, x2
b.lo 1b
/* Starting dynamic relocations. Use adrp/adr to get RELA_START and END */
- adrp x1, __RELA_START__
+3: adrp x1, __RELA_START__
add x1, x1, :lo12:__RELA_START__
adrp x2, __RELA_END__
add x2, x2, :lo12:__RELA_END__
+
/*
* According to ELF-64 specification, the RELA data structure is as
* follows:
- * typedef struct
- * {
+ * typedef struct {
* Elf64_Addr r_offset;
* Elf64_Xword r_info;
* Elf64_Sxword r_addend;
@@ -550,16 +557,19 @@
*
* r_offset is address of reference
* r_info is symbol index and type of relocation (in this case
- * 0x403 which corresponds to R_AARCH64_RELATIVE).
+ * code 1027 which corresponds to R_AARCH64_RELATIVE).
* r_addend is constant part of expression.
*
* Size of Elf64_Rela structure is 24 bytes.
*/
-1:
- /* Assert that the relocation type is R_AARCH64_RELATIVE */
+
+ /* Skip R_AARCH64_NONE entry with code 0 */
+1: ldr x3, [x1, #8]
+ cbz x3, 2f
+
#if ENABLE_ASSERTIONS
- ldr x3, [x1, #8]
- cmp x3, #0x403
+ /* Assert that the relocation type is R_AARCH64_RELATIVE */
+ cmp x3, #R_AARCH64_RELATIVE
ASM_ASSERT(eq)
#endif
ldr x3, [x1] /* r_offset */
@@ -569,9 +579,10 @@
/* Skip adding offset if r_addend is < lower limit */
cmp x4, x6
b.lo 2f
+
/* Skip adding offset if r_addend entry is >= upper limit */
cmp x4, x7
- b.ge 2f
+ b.hs 2f
add x4, x0, x4 /* Diff(S) + r_addend */
str x4, [x3]
@@ -579,6 +590,5 @@
2: add x1, x1, #24
cmp x1, x2
b.lo 1b
-
ret
endfunc fixup_gdt_reloc
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 98a1183..4f7f4bb 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -382,35 +382,6 @@
endfunc check_errata_1791580
/* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1800710.
- * This applies to revision <= r4p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1800710_wa
- /* Compare x0 against revision <= r4p0 */
- mov x17, x30
- bl check_errata_1800710
- cbz x0, 1f
-
- /* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A76_CPUECTLR_EL1
- orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_53
- msr CORTEX_A76_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1800710_wa
-
-func check_errata_1800710
- /* Applies to everything <= r4p0 */
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1800710
-
- /* --------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1262606,
* #1275112, and #1868343. #1262606 and #1275112
* apply to revisions <= r3p0 and #1868343 applies to
@@ -459,6 +430,61 @@
b cpu_rev_var_ls
endfunc check_errata_1868343
+/* --------------------------------------------------
+ * Errata Workaround for A76 Erratum 1946160.
+ * This applies to revisions r3p0 - r4p1 of A76.
+ * It also exists in r0p0 - r2p0 but there is no fix
+ * in those revisions.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a76_1946160_wa
+ /* Compare x0 against revisions r3p0 - r4p1 */
+ mov x17, x30
+ bl check_errata_1946160
+ cbz x0, 1f
+
+ mov x0, #3
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3900002
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #4
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800082
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #5
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800200
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF003E0
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ isb
+1:
+ ret x17
+endfunc errata_a76_1946160_wa
+
+func check_errata_1946160
+ /* Applies to revisions r3p0 - r4p1. */
+ mov x1, #0x30
+ mov x2, #0x41
+ b cpu_rev_var_range
+endfunc check_errata_1946160
+
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
@@ -538,9 +564,9 @@
bl errata_a76_1791580_wa
#endif
-#if ERRATA_A76_1800710
+#if ERRATA_A76_1946160
mov x0, x18
- bl errata_a76_1800710_wa
+ bl errata_a76_1946160_wa
#endif
#if WORKAROUND_CVE_2018_3639
@@ -624,9 +650,9 @@
report_errata ERRATA_A76_1275112, cortex_a76, 1275112
report_errata ERRATA_A76_1286807, cortex_a76, 1286807
report_errata ERRATA_A76_1791580, cortex_a76, 1791580
- report_errata ERRATA_A76_1800710, cortex_a76, 1800710
report_errata ERRATA_A76_1165522, cortex_a76, 1165522
report_errata ERRATA_A76_1868343, cortex_a76, 1868343
+ report_errata ERRATA_A76_1946160, cortex_a76, 1946160
report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953
report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 04a610e..e3a6f5f 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -86,35 +86,6 @@
endfunc check_errata_1508412_0
/* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1800714.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1800714_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1800714
- cbz x0, 1f
-
- /* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A77_CPUECTLR_EL1
- orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
- msr CORTEX_A77_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1800714_wa
-
-func check_errata_1800714
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1800714
-
- /* --------------------------------------------------
* Errata Workaround for Cortex A77 Errata #1925769.
* This applies to revision <= r1p1 of Cortex A77.
* Inputs:
@@ -158,11 +129,6 @@
bl errata_a77_1508412_wa
#endif
-#if ERRATA_A77_1800714
- mov x0, x18
- bl errata_a77_1800714_wa
-#endif
-
#if ERRATA_A77_1925769
mov x0, x18
bl errata_a77_1925769_wa
@@ -202,7 +168,6 @@
* checking functions of each errata.
*/
report_errata ERRATA_A77_1508412, cortex_a77, 1508412
- report_errata ERRATA_A77_1800714, cortex_a77, 1800714
report_errata ERRATA_A77_1925769, cortex_a77, 1925769
ldp x8, x30, [sp], #16
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 9914f12..f61726b 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,7 +31,7 @@
bl check_errata_1688305
cbz x0, 1f
mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, CORTEX_A78_ACTLR2_EL1_BIT_1
+ orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
msr CORTEX_A78_ACTLR2_EL1, x1
isb
1:
@@ -44,6 +44,88 @@
b cpu_rev_var_ls
endfunc check_errata_1688305
+ /* --------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata #1941498.
+ * This applies to revisions r0p0, r1p0, and r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78_1941498_wa
+ /* Compare x0 against revision <= r1p1 */
+ mov x17, x30
+ bl check_errata_1941498
+ cbz x0, 1f
+
+ /* Set bit 8 in ECTLR_EL1 */
+ mrs x1, CORTEX_A78_CPUECTLR_EL1
+ orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
+ msr CORTEX_A78_CPUECTLR_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_a78_1941498_wa
+
+func check_errata_1941498
+ /* Check for revision <= r1p1, might need to be updated later. */
+ mov x1, #0x11
+ b cpu_rev_var_ls
+endfunc check_errata_1941498
+
+ /* --------------------------------------------------
+ * Errata Workaround for A78 Erratum 1951500.
+ * This applies to revisions r1p0 and r1p1 of A78.
+ * The issue also exists in r0p0 but there is no fix
+ * in that revision.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78_1951500_wa
+ /* Compare x0 against revisions r1p0 - r1p1 */
+ mov x17, x30
+ bl check_errata_1951500
+ cbz x0, 1f
+
+ msr S3_6_c15_c8_0, xzr
+ ldr x0, =0x10E3900002
+ msr S3_6_c15_c8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_c15_c8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_c15_c8_1, x0
+
+ mov x0, #1
+ msr S3_6_c15_c8_0, x0
+ ldr x0, =0x10E3800082
+ msr S3_6_c15_c8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_c15_c8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_c15_c8_1, x0
+
+ mov x0, #2
+ msr S3_6_c15_c8_0, x0
+ ldr x0, =0x10E3800200
+ msr S3_6_c15_c8_2, x0
+ ldr x0, =0x10FFF003E0
+ msr S3_6_c15_c8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_c15_c8_1, x0
+
+ isb
+1:
+ ret x17
+endfunc errata_a78_1951500_wa
+
+func check_errata_1951500
+ /* Applies to revisions r1p0 and r1p1. */
+ mov x1, #CPU_REV(1, 0)
+ mov x2, #CPU_REV(1, 1)
+ b cpu_rev_var_range
+endfunc check_errata_1951500
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A78
* -------------------------------------------------
@@ -58,6 +140,16 @@
bl errata_a78_1688305_wa
#endif
+#if ERRATA_A78_1941498
+ mov x0, x18
+ bl errata_a78_1941498_wa
+#endif
+
+#if ERRATA_A78_1951500
+ mov x0, x18
+ bl errata_a78_1951500_wa
+#endif
+
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@@ -113,6 +205,8 @@
* checking functions of each errata.
*/
report_errata ERRATA_A78_1688305, cortex_a78, 1688305
+ report_errata ERRATA_A78_1941498, cortex_a78, 1941498
+ report_errata ERRATA_A78_1951500, cortex_a78, 1951500
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 03ee472..9c97cf6 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,15 +1,15 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
-#include <neoverse_n1.h>
#include <cpuamu.h>
#include <cpu_macros.S>
#include <context.h>
+#include <neoverse_n1.h>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
@@ -22,19 +22,6 @@
#endif
.global neoverse_n1_errata_ic_trap_handler
- .global is_scu_present_in_dsu
-
-/*
- * Check DSU is configured with SCU and L3 unit
- * 1-> SCU present
- * 0-> SCU not present
- */
-func is_scu_present_in_dsu
- mrs x0, CPUCFR_EL1
- ubfx x0, x0, #SCU_SHIFT, #1
- eor x0, x0, #1
- ret
-endfunc is_scu_present_in_dsu
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Erratum 1043202.
@@ -420,6 +407,63 @@
b cpu_rev_var_ls
endfunc check_errata_1868343
+ /* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1946160.
+ * This applies to revisions r3p0, r3p1, r4p0, and
+ * r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
+ * and r2p0 but there is no fix in these revisions.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1946160_wa
+ /*
+ * Compare x0 against r3p0 - r4p1
+ */
+ mov x17, x30
+ bl check_errata_1946160
+ cbz x0, 1f
+
+ mov x0, #3
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3900002
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #4
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800082
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #5
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800200
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF003E0
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ isb
+1:
+ ret x17
+endfunc errata_n1_1946160_wa
+
+func check_errata_1946160
+ /* Applies to r3p0 - r4p1. */
+ mov x1, #0x30
+ mov x2, #0x41
+ b cpu_rev_var_range
+endfunc check_errata_1946160
+
func neoverse_n1_reset_func
mov x19, x30
@@ -499,6 +543,11 @@
bl errata_n1_1868343_wa
#endif
+#if ERRATA_N1_1946160
+ mov x0, x18
+ bl errata_n1_1946160_wa
+#endif
+
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@@ -515,7 +564,7 @@
msr CPUAMCNTENSET_EL0, x0
#endif
-#if NEOVERSE_N1_EXTERNAL_LLC
+#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some system may have External LLC, core needs to be made aware */
mrs x0, NEOVERSE_N1_CPUECTLR_EL1
orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
@@ -573,6 +622,7 @@
report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
+ report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
ldp x8, x30, [sp], #16
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
new file mode 100644
index 0000000..8d646cb
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <neoverse_n2.h>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Neoverse N2.
+ * -------------------------------------------------
+ */
+func neoverse_n2_reset_func
+ /* Check if the PE implements SSBS */
+ mrs x0, id_aa64pfr1_el1
+ tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
+ b.eq 1f
+
+ /* Disable speculative loads */
+ msr SSBS, xzr
+1:
+ /* Force all cacheable atomic instructions to be near */
+ mrs x0, NEOVERSE_N2_CPUACTLR2_EL1
+ orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
+ msr NEOVERSE_N2_CPUACTLR2_EL1, x0
+
+#if ENABLE_AMU
+ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
+ mrs x0, cptr_el3
+ orr x0, x0, #TAM_BIT
+ msr cptr_el3, x0
+
+ /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
+ mrs x0, cptr_el2
+ orr x0, x0, #TAM_BIT
+ msr cptr_el2, x0
+
+ /* No need to enable the counters as this would be done at el3 exit */
+#endif
+
+#if NEOVERSE_Nx_EXTERNAL_LLC
+ /* Some systems may have External LLC, core needs to be made aware */
+ mrs x0, NEOVERSE_N2_CPUECTLR_EL1
+ orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
+ msr NEOVERSE_N2_CPUECTLR_EL1, x0
+#endif
+
+ isb
+ ret
+endfunc neoverse_n2_reset_func
+
+func neoverse_n2_core_pwr_dwn
+ /* ---------------------------------------------
+ * Enable CPU power down bit in power control register
+ * No need to do cache maintenance here.
+ * ---------------------------------------------
+ */
+ mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
+ orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
+ msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc neoverse_n2_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Neoverse N2 cores. Must follow AAPCS.
+ */
+func neoverse_n2_errata_report
+ /* No errata reported for Neoverse N2 cores */
+ ret
+endfunc neoverse_n2_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides Neoverse N2 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ASCII and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_n2_regs, "aS"
+neoverse_n2_regs: /* The ASCII list of register names to be reported */
+ .asciz "cpupwrctlr_el1", ""
+
+func neoverse_n2_cpu_reg_dump
+ adr x6, neoverse_n2_regs
+ mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1
+ ret
+endfunc neoverse_n2_cpu_reg_dump
+
+declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \
+ neoverse_n2_reset_func, \
+ neoverse_n2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_n_common.S b/lib/cpus/aarch64/neoverse_n_common.S
new file mode 100644
index 0000000..b816342
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_n_common.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <neoverse_n_common.h>
+
+ .global is_scu_present_in_dsu
+
+/*
+ * Check if the SCU L3 Unit is present on the DSU
+ * 1-> SCU present
+ * 0-> SCU not present
+ *
+ * This function is implemented as weak on dsu_helpers.S and must be
+ * overwritten for Neoverse Nx cores.
+ */
+
+func is_scu_present_in_dsu
+ mrs x0, CPUCFR_EL1
+ ubfx x0, x0, #SCU_SHIFT, #1
+ eor x0, x0, #1
+ ret
+endfunc is_scu_present_in_dsu
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 1210538..64a4b4d 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -25,9 +25,9 @@
WORKAROUND_CVE_2018_3639 ?=1
DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
-# Flag to indicate internal or external Last level cache
+# Flags to indicate internal or external Last level cache
# By default internal
-NEOVERSE_N1_EXTERNAL_LLC ?=0
+NEOVERSE_Nx_EXTERNAL_LLC ?=0
# Process A57_ENABLE_NONCACHEABLE_LOAD_FWD flag
$(eval $(call assert_boolean,A57_ENABLE_NONCACHEABLE_LOAD_FWD))
@@ -56,8 +56,8 @@
$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
-$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC))
-$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC))
+$(eval $(call assert_boolean,NEOVERSE_Nx_EXTERNAL_LLC))
+$(eval $(call add_define,NEOVERSE_Nx_EXTERNAL_LLC))
ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
ifeq (${WORKAROUND_CVE_2018_3639},0)
@@ -270,10 +270,6 @@
# only to revision <= r4p0 of the Cortex A76 cpu.
ERRATA_A76_1791580 ?=0
-# Flag to apply erratum 1800710 workaround during reset. This erratum applies
-# only to revision <= r4p0 of the Cortex A76 cpu.
-ERRATA_A76_1800710 ?=0
-
# Flag to apply erratum 1165522 workaround during reset. This erratum applies
# to all revisions of Cortex A76 cpu.
ERRATA_A76_1165522 ?=0
@@ -282,14 +278,14 @@
# only to revision <= r4p0 of the Cortex A76 cpu.
ERRATA_A76_1868343 ?=0
+# Flag to apply erratum 1946160 workaround during reset. This erratum applies
+# only to revisions r3p0 - r4p1 of the Cortex A76 cpu.
+ERRATA_A76_1946160 ?=0
+
# Flag to apply erratum 1508412 workaround during reset. This erratum applies
# only to revision <= r1p0 of the Cortex A77 cpu.
ERRATA_A77_1508412 ?=0
-# Flag to apply erratum 1800714 workaround during reset. This erratum applies
-# only to revision <= r1p1 of the Cortex A77 cpu.
-ERRATA_A77_1800714 ?=0
-
# Flag to apply erratum 1925769 workaround during reset. This erratum applies
# only to revision <= r1p1 of the Cortex A77 cpu.
ERRATA_A77_1925769 ?=0
@@ -298,6 +294,15 @@
# to revisions r0p0 - r1p0 of the A78 cpu.
ERRATA_A78_1688305 ?=0
+# Flag to apply erratum 1941498 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0, and r1p1 of the A78 cpu.
+ERRATA_A78_1941498 ?=0
+
+# Flag to apply erratum 1951500 workaround during reset. This erratum applies
+# to revisions r1p0 and r1p1 of the A78 cpu. The issue is present in r0p0 as
+# well but there is no workaround for that revision.
+ERRATA_A78_1951500 ?=0
+
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_N1_1043202 ?=0
@@ -350,6 +355,11 @@
# to revision <= r4p0 of the Neoverse N1 cpu.
ERRATA_N1_1868343 ?=0
+# Flag to apply erratum 1946160 workaround during reset. This erratum applies
+# to revisions r3p0, r3p1, r4p0, and r4p1 of the Neoverse N1 cpu. The issue
+# exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround.
+ERRATA_N1_1946160 ?=0
+
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
ERRATA_DSU_798953 ?=0
@@ -555,10 +565,6 @@
$(eval $(call assert_boolean,ERRATA_A76_1791580))
$(eval $(call add_define,ERRATA_A76_1791580))
-# Process ERRATA_A76_1800710 flag
-$(eval $(call assert_boolean,ERRATA_A76_1800710))
-$(eval $(call add_define,ERRATA_A76_1800710))
-
# Process ERRATA_A76_1165522 flag
$(eval $(call assert_boolean,ERRATA_A76_1165522))
$(eval $(call add_define,ERRATA_A76_1165522))
@@ -567,14 +573,14 @@
$(eval $(call assert_boolean,ERRATA_A76_1868343))
$(eval $(call add_define,ERRATA_A76_1868343))
+# Process ERRATA_A76_1946160 flag
+$(eval $(call assert_boolean,ERRATA_A76_1946160))
+$(eval $(call add_define,ERRATA_A76_1946160))
+
# Process ERRATA_A77_1508412 flag
$(eval $(call assert_boolean,ERRATA_A77_1508412))
$(eval $(call add_define,ERRATA_A77_1508412))
-# Process ERRATA_A77_1800714 flag
-$(eval $(call assert_boolean,ERRATA_A77_1800714))
-$(eval $(call add_define,ERRATA_A77_1800714))
-
# Process ERRATA_A77_1925769 flag
$(eval $(call assert_boolean,ERRATA_A77_1925769))
$(eval $(call add_define,ERRATA_A77_1925769))
@@ -583,6 +589,14 @@
$(eval $(call assert_boolean,ERRATA_A78_1688305))
$(eval $(call add_define,ERRATA_A78_1688305))
+# Process ERRATA_A78_1941498 flag
+$(eval $(call assert_boolean,ERRATA_A78_1941498))
+$(eval $(call add_define,ERRATA_A78_1941498))
+
+# Process ERRATA_A78_1951500 flag
+$(eval $(call assert_boolean,ERRATA_A78_1951500))
+$(eval $(call add_define,ERRATA_A78_1951500))
+
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_N1_1043202))
@@ -635,6 +649,10 @@
$(eval $(call assert_boolean,ERRATA_N1_1868343))
$(eval $(call add_define,ERRATA_N1_1868343))
+# Process ERRATA_N1_1946160 flag
+$(eval $(call assert_boolean,ERRATA_N1_1946160))
+$(eval $(call add_define,ERRATA_N1_1946160))
+
# Process ERRATA_DSU_798953 flag
$(eval $(call assert_boolean,ERRATA_DSU_798953))
$(eval $(call add_define,ERRATA_DSU_798953))
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 1cb527d..773082a 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -65,9 +65,13 @@
mrs x9, cptr_el2
stp x17, x9, [x0, #CTX_CNTVOFF_EL2]
- mrs x10, dbgvcr32_el2
mrs x11, elr_el2
+#if CTX_INCLUDE_AARCH32_REGS
+ mrs x10, dbgvcr32_el2
stp x10, x11, [x0, #CTX_DBGVCR32_EL2]
+#else
+ str x11, [x0, #CTX_ELR_EL2]
+#endif
mrs x14, esr_el2
mrs x15, far_el2
@@ -90,8 +94,12 @@
stp x13, x14, [x0, #CTX_ICH_VMCR_EL2]
mrs x15, mdcr_el2
+#if ENABLE_SPE_FOR_LOWER_ELS
mrs x16, PMSCR_EL2
stp x15, x16, [x0, #CTX_MDCR_EL2]
+#else
+ str x15, [x0, #CTX_MDCR_EL2]
+#endif
mrs x17, sctlr_el2
mrs x9, spsr_el2
@@ -185,8 +193,10 @@
mrs x9, contextidr_el2
stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2]
+#if CTX_INCLUDE_AARCH32_REGS
mrs x10, sder32_el2
str x10, [x0, #CTX_SDER32_EL2]
+#endif
mrs x11, ttbr1_el2
str x11, [x0, #CTX_TTBR1_EL2]
@@ -194,8 +204,10 @@
mrs x12, vdisr_el2
str x12, [x0, #CTX_VDISR_EL2]
+#if CTX_INCLUDE_NEVE_REGS
mrs x13, vncr_el2
str x13, [x0, #CTX_VNCR_EL2]
+#endif
mrs x14, vsesr_el2
str x14, [x0, #CTX_VSESR_EL2]
@@ -255,8 +267,12 @@
msr cntvoff_el2, x17
msr cptr_el2, x9
+#if CTX_INCLUDE_AARCH32_REGS
ldp x10, x11, [x0, #CTX_DBGVCR32_EL2]
msr dbgvcr32_el2, x10
+#else
+ ldr x11, [x0, #CTX_ELR_EL2]
+#endif
msr elr_el2, x11
ldp x14, x15, [x0, #CTX_ESR_EL2]
@@ -279,9 +295,13 @@
msr ICH_VMCR_EL2, x13
msr mair_el2, x14
+#if ENABLE_SPE_FOR_LOWER_ELS
ldp x15, x16, [x0, #CTX_MDCR_EL2]
- msr mdcr_el2, x15
msr PMSCR_EL2, x16
+#else
+ ldr x15, [x0, #CTX_MDCR_EL2]
+#endif
+ msr mdcr_el2, x15
ldp x17, x9, [x0, #CTX_SCTLR_EL2]
msr sctlr_el2, x17
@@ -374,8 +394,10 @@
msr cnthv_tval_el2, x9
msr contextidr_el2, x10
+#if CTX_INCLUDE_AARCH32_REGS
ldr x11, [x0, #CTX_SDER32_EL2]
msr sder32_el2, x11
+#endif
ldr x12, [x0, #CTX_TTBR1_EL2]
msr ttbr1_el2, x12
@@ -383,8 +405,10 @@
ldr x13, [x0, #CTX_VDISR_EL2]
msr vdisr_el2, x13
+#if CTX_INCLUDE_NEVE_REGS
ldr x14, [x0, #CTX_VNCR_EL2]
msr vncr_el2, x14
+#endif
ldr x15, [x0, #CTX_VSESR_EL2]
msr vsesr_el2, x15
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index b460731..72d463b 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -144,30 +144,33 @@
scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
#endif /* !CTX_INCLUDE_PAUTH_REGS */
+#if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
+ /* Get Memory Tagging Extension support level */
+ unsigned int mte = get_armv8_5_mte_support();
+#endif
/*
* Enable MTE support. Support is enabled unilaterally for the normal
* world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
* set.
*/
#if CTX_INCLUDE_MTE_REGS
- assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX);
+ assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
scr_el3 |= SCR_ATA_BIT;
#else
- unsigned int mte = get_armv8_5_mte_support();
- if (mte == MTE_IMPLEMENTED_EL0) {
- /*
- * Can enable MTE across both worlds as no MTE registers are
- * used
- */
- scr_el3 |= SCR_ATA_BIT;
- } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) {
- /*
- * Can only enable MTE in Non-Secure world without register
- * saving
- */
+ /*
+ * When MTE is only implemented at EL0, it can be enabled
+ * across both worlds as no MTE registers are used.
+ */
+ if ((mte == MTE_IMPLEMENTED_EL0) ||
+ /*
+ * When MTE is implemented at all ELs, it can be only enabled
+ * in Non-Secure world without register saving.
+ */
+ (((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)) &&
+ (security_state == NON_SECURE))) {
scr_el3 |= SCR_ATA_BIT;
}
-#endif
+#endif /* CTX_INCLUDE_MTE_REGS */
#ifdef IMAGE_BL31
/*
diff --git a/lib/extensions/mtpmu/aarch32/mtpmu.S b/lib/extensions/mtpmu/aarch32/mtpmu.S
new file mode 100644
index 0000000..834cee3
--- /dev/null
+++ b/lib/extensions/mtpmu/aarch32/mtpmu.S
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+ .global mtpmu_disable
+
+/* -------------------------------------------------------------
+ * The functions in this file are called at entrypoint, before
+ * the CPU has decided whether this is a cold or a warm boot.
+ * Therefore there are no stack yet to rely on for a C function
+ * call.
+ * -------------------------------------------------------------
+ */
+
+/*
+ * bool mtpmu_supported(void)
+ *
+ * Return a boolean indicating whether FEAT_MTPMU is supported or not.
+ *
+ * Trash registers: r0.
+ */
+func mtpmu_supported
+ ldcopr r0, ID_DFR1
+ and r0, r0, #(ID_DFR1_MTPMU_MASK >> ID_DFR1_MTPMU_SHIFT)
+ cmp r0, #ID_DFR1_MTPMU_SUPPORTED
+ mov r0, #0
+ addeq r0, r0, #1
+ bx lr
+endfunc mtpmu_supported
+
+/*
+ * bool el_implemented(unsigned int el)
+ *
+ * Return a boolean indicating if the specified EL (2 or 3) is implemented.
+ *
+ * Trash registers: r0
+ */
+func el_implemented
+ cmp r0, #3
+ ldcopr r0, ID_PFR1
+ lsreq r0, r0, #ID_PFR1_SEC_SHIFT
+ lsrne r0, r0, #ID_PFR1_VIRTEXT_SHIFT
+ /*
+ * ID_PFR1_VIRTEXT_MASK is the same as ID_PFR1_SEC_MASK
+ * so use any one of them
+ */
+ and r0, r0, #ID_PFR1_VIRTEXT_MASK
+ cmp r0, #ID_PFR1_ELx_ENABLED
+ mov r0, #0
+ addeq r0, r0, #1
+ bx lr
+endfunc el_implemented
+
+/*
+ * void mtpmu_disable(void)
+ *
+ * Disable mtpmu feature if supported.
+ *
+ * Trash register: r0, r1, r2
+ */
+func mtpmu_disable
+ mov r2, lr
+ bl mtpmu_supported
+ cmp r0, #0
+ bxeq r2 /* FEAT_MTPMU not supported */
+
+ /* FEAT_MTMPU Supported */
+ mov r0, #3
+ bl el_implemented
+ cmp r0, #0
+ beq 1f
+
+ /* EL3 implemented */
+ ldcopr r0, SDCR
+ ldr r1, =SDCR_MTPME_BIT
+ bic r0, r0, r1
+ stcopr r0, SDCR
+
+ /*
+ * If EL3 is implemented, HDCR.MTPME is implemented as Res0 and
+ * FEAT_MTPMU is controlled only from EL3, so no need to perform
+ * any operations for EL2.
+ */
+ isb
+ bx r2
+1:
+ /* EL3 not implemented */
+ mov r0, #2
+ bl el_implemented
+ cmp r0, #0
+ bxeq r2 /* No EL2 or EL3 implemented */
+
+ /* EL2 implemented */
+ ldcopr r0, HDCR
+ ldr r1, =HDCR_MTPME_BIT
+ orr r0, r0, r1
+ stcopr r0, HDCR
+ isb
+ bx r2
+endfunc mtpmu_disable
diff --git a/lib/extensions/mtpmu/aarch64/mtpmu.S b/lib/extensions/mtpmu/aarch64/mtpmu.S
new file mode 100644
index 0000000..0a1d57b
--- /dev/null
+++ b/lib/extensions/mtpmu/aarch64/mtpmu.S
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+ .global mtpmu_disable
+
+/* -------------------------------------------------------------
+ * The functions in this file are called at entrypoint, before
+ * the CPU has decided whether this is a cold or a warm boot.
+ * Therefore there are no stack yet to rely on for a C function
+ * call.
+ * -------------------------------------------------------------
+ */
+
+/*
+ * bool mtpmu_supported(void)
+ *
+ * Return a boolean indicating whether FEAT_MTPMU is supported or not.
+ *
+ * Trash registers: x0, x1
+ */
+func mtpmu_supported
+ mrs x0, id_aa64dfr0_el1
+ mov_imm x1, ID_AA64DFR0_MTPMU_MASK
+ and x0, x1, x0, LSR #ID_AA64DFR0_MTPMU_SHIFT
+ cmp x0, ID_AA64DFR0_MTPMU_SUPPORTED
+ cset x0, eq
+ ret
+endfunc mtpmu_supported
+
+/*
+ * bool el_implemented(unsigned int el_shift)
+ *
+ * Return a boolean indicating if the specified EL is implemented.
+ * The EL is represented as the bitmask shift on id_aa64pfr0_el1 register.
+ *
+ * Trash registers: x0, x1
+ */
+func el_implemented
+ mrs x1, id_aa64pfr0_el1
+ lsr x1, x1, x0
+ cmp x1, #ID_AA64PFR0_ELX_MASK
+ cset x0, eq
+ ret
+endfunc el_implemented
+
+/*
+ * void mtpmu_disable(void)
+ *
+ * Disable mtpmu feature if supported.
+ *
+ * Trash register: x0, x1, x30
+ */
+func mtpmu_disable
+ mov x10, x30
+ bl mtpmu_supported
+ cbz x0, exit_disable
+
+ /* FEAT_MTMPU Supported */
+ mov_imm x0, ID_AA64PFR0_EL3_SHIFT
+ bl el_implemented
+ cbz x0, 1f
+
+ /* EL3 implemented */
+ mrs x0, mdcr_el3
+ mov_imm x1, MDCR_MTPME_BIT
+ bic x0, x0, x1
+ msr mdcr_el3, x0
+
+ /*
+ * If EL3 is implemented, MDCR_EL2.MTPME is implemented as Res0 and
+ * FEAT_MTPMU is controlled only from EL3, so no need to perform
+ * any operations for EL2.
+ */
+ isb
+exit_disable:
+ ret x10
+1:
+ /* EL3 not implemented */
+ mov_imm x0, ID_AA64PFR0_EL2_SHIFT
+ bl el_implemented
+ cbz x0, exit_disable
+
+ /* EL2 implemented */
+ mrs x0, mdcr_el2
+ mov_imm x1, MDCR_EL2_MTPME
+ bic x0, x0, x1
+ msr mdcr_el2, x0
+ isb
+ ret x10
+endfunc mtpmu_disable
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index e2dcfa8..72bd6bd 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -42,6 +42,11 @@
define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \
define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64))
+/* Internally PSCI uses a uint16_t for various cpu indexes so
+ * define a limit to number of CPUs that can be initialised.
+ */
+#define PSCI_MAX_CPUS_INDEX 0xFFFFU
+
/*
* Helper functions to get/set the fields of PSCI per-cpu data.
*/
@@ -134,7 +139,7 @@
unsigned char level;
/* For indexing the psci_lock array*/
- unsigned char lock_index;
+ uint16_t lock_index;
} non_cpu_pd_node_t;
typedef struct cpu_pwr_domain_node {
@@ -239,7 +244,7 @@
#endif /* HW_ASSISTED_COHERENCY */
static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node,
- unsigned char idx)
+ uint16_t idx)
{
non_cpu_pd_node[idx].lock_index = idx;
}
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index d1ec998..9c37d63 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c
@@ -17,6 +17,12 @@
#include "psci_private.h"
+/*
+ * Check that PLATFORM_CORE_COUNT fits into the number of cores
+ * that can be represented by PSCI_MAX_CPUS_INDEX.
+ */
+CASSERT(PLATFORM_CORE_COUNT <= (PSCI_MAX_CPUS_INDEX + 1U), assert_psci_cores_overflow);
+
/*******************************************************************************
* Per cpu non-secure contexts used to program the architectural state prior
* return to the normal world.
@@ -34,11 +40,13 @@
* Function which initializes the 'psci_non_cpu_pd_nodes' or the
* 'psci_cpu_pd_nodes' corresponding to the power level.
******************************************************************************/
-static void __init psci_init_pwr_domain_node(unsigned char node_idx,
+static void __init psci_init_pwr_domain_node(uint16_t node_idx,
unsigned int parent_idx,
unsigned char level)
{
if (level > PSCI_CPU_PWR_LVL) {
+ assert(node_idx < PSCI_NUM_NON_CPU_PWR_DOMAINS);
+
psci_non_cpu_pd_nodes[node_idx].level = level;
psci_lock_init(psci_non_cpu_pd_nodes, node_idx);
psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx;
@@ -47,6 +55,8 @@
} else {
psci_cpu_data_t *svc_cpu_data;
+ assert(node_idx < PLATFORM_CORE_COUNT);
+
psci_cpu_pd_nodes[node_idx].parent_node = parent_idx;
/* Initialize with an invalid mpidr */
@@ -144,7 +154,7 @@
for (j = node_index;
j < (node_index + num_children); j++)
- psci_init_pwr_domain_node((unsigned char)j,
+ psci_init_pwr_domain_node((uint16_t)j,
parent_node_index - 1U,
(unsigned char)level);
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index bc4982d..5217a85 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -19,6 +19,9 @@
# The Target build architecture. Supported values are: aarch64, aarch32.
ARCH := aarch64
+# ARM Architecture feature modifiers: none by default
+ARM_ARCH_FEATURE := none
+
# ARM Architecture major and minor versions: 8.0 by default.
ARM_ARCH_MAJOR := 8
ARM_ARCH_MINOR := 0
@@ -62,6 +65,11 @@
# world. It is not needed to use it in the Non-secure world.
CTX_INCLUDE_PAUTH_REGS := 0
+# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
+# This must be set to 1 if architecture implements Nested Virtualization
+# Extension and platform wants to use this feature in the Secure world
+CTX_INCLUDE_NEVE_REGS := 0
+
# Debug build
DEBUG := 0
@@ -74,6 +82,10 @@
# Disable the generation of the binary image (ELF only).
DISABLE_BIN_GENERATION := 0
+# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards
+# compatibility.
+DISABLE_MTPMU := 0
+
# Enable capability to disable authentication dynamically. Only meant for
# development platforms.
DYN_DISABLE_AUTH := 0
diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk
index 9c92d3f..853ad11 100644
--- a/make_helpers/tbbr/tbbr_tools.mk
+++ b/make_helpers/tbbr/tbbr_tools.mk
@@ -54,8 +54,11 @@
# packed in the FIP). Developers can use their own keys by specifying the proper
# build option in the command line when building the Trusted Firmware
$(if ${KEY_ALG},$(eval $(call CERT_ADD_CMD_OPT,${KEY_ALG},--key-alg)))
+$(if ${KEY_ALG},$(eval $(call CERT_ADD_CMD_OPT,${KEY_ALG},--key-alg,FWU_)))
$(if ${KEY_SIZE},$(eval $(call CERT_ADD_CMD_OPT,${KEY_SIZE},--key-size)))
+$(if ${KEY_SIZE},$(eval $(call CERT_ADD_CMD_OPT,${KEY_SIZE},--key-size,FWU_)))
$(if ${HASH_ALG},$(eval $(call CERT_ADD_CMD_OPT,${HASH_ALG},--hash-alg)))
+$(if ${HASH_ALG},$(eval $(call CERT_ADD_CMD_OPT,${HASH_ALG},--hash-alg,FWU_)))
$(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key)))
$(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key,FWU_)))
$(if ${PROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${PROT_KEY},--prot-key)))
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk
index 997aaa6..901d888 100644
--- a/plat/allwinner/common/allwinner-common.mk
+++ b/plat/allwinner/common/allwinner-common.mk
@@ -48,6 +48,10 @@
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+ERRATA_A53_1530924 := 1
+
+# The traditional U-Boot load address is 160MB into DRAM.
+PRELOADED_BL33_BASE ?= 0x4a000000
# The reset vector can be changed for each CPU.
PROGRAMMABLE_RESET_ADDRESS := 1
diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
index 975cc48..93720ff 100644
--- a/plat/allwinner/common/include/platform_def.h
+++ b/plat/allwinner/common/include/platform_def.h
@@ -25,9 +25,6 @@
#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
-/* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */
-#define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20))
-
/* How much memory to reserve as secure for BL32, if configured */
#define SUNXI_DRAM_SEC_SIZE (32U << 20)
diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c
index e836a34..9c8eaa4 100644
--- a/plat/allwinner/common/sunxi_bl31_setup.c
+++ b/plat/allwinner/common/sunxi_bl31_setup.c
@@ -57,7 +57,7 @@
for (i = 0; i < 2048 / sizeof(uint64_t); i++) {
uint32_t *dtb_base;
- if (u_boot_base[i] != PLAT_SUNXI_NS_IMAGE_OFFSET)
+ if (u_boot_base[i] != PRELOADED_BL33_BASE)
continue;
/* Does the suspected U-Boot size look anyhow reasonable? */
@@ -96,7 +96,7 @@
* Tell BL31 where the non-trusted software image
* is located and the entry state information
*/
- bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+ bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
index 0ca18ad..5b536a0 100644
--- a/plat/allwinner/common/sunxi_common.c
+++ b/plat/allwinner/common/sunxi_common.c
@@ -27,7 +27,7 @@
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
MT_RW_DATA | MT_SECURE),
- MAP_REGION(PLAT_SUNXI_NS_IMAGE_OFFSET,
+ MAP_REGION(PRELOADED_BL33_BASE,
SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE,
SUNXI_DRAM_MAP_SIZE,
MT_RO_DATA | MT_NS),
@@ -39,15 +39,6 @@
return SUNXI_OSC24M_CLK_IN_HZ;
}
-uintptr_t plat_get_ns_image_entrypoint(void)
-{
-#ifdef PRELOADED_BL33_BASE
- return PRELOADED_BL33_BASE;
-#else
- return PLAT_SUNXI_NS_IMAGE_OFFSET;
-#endif
-}
-
void sunxi_configure_mmu_el3(int flags)
{
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
@@ -125,11 +116,9 @@
device_bit = BIT(6);
break;
case SUNXI_SOC_H6:
- if (use_rsb)
- return -ENODEV;
- pin_func = 0x33;
+ pin_func = use_rsb ? 0x22 : 0x33;
device_bit = BIT(16);
- reset_offset = 0x19c;
+ reset_offset = use_rsb ? 0x1bc : 0x19c;
break;
case SUNXI_SOC_A64:
pin_func = use_rsb ? 0x22 : 0x33;
@@ -157,7 +146,7 @@
if (socid != SUNXI_SOC_H6)
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit);
else
- mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0));
+ mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0));
/* assert, then de-assert reset of I2C/RSB controller */
mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
diff --git a/plat/allwinner/common/sunxi_security.c b/plat/allwinner/common/sunxi_security.c
index 92c83b0..98b91c3 100644
--- a/plat/allwinner/common/sunxi_security.c
+++ b/plat/allwinner/common/sunxi_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,16 +7,11 @@
#include <common/debug.h>
#include <lib/mmio.h>
+#include <sunxi_ccu.h>
#include <sunxi_mmap.h>
#include <sunxi_private.h>
+#include <sunxi_spc.h>
-#ifdef SUNXI_SPC_BASE
-#define SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x4)
-#define SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x8)
-#define SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0xc)
-#endif
-
-#define R_PRCM_SEC_SWITCH_REG 0x1d0
#define DMA_SEC_REG 0x20
/*
@@ -27,20 +22,18 @@
*/
void sunxi_security_setup(void)
{
-#ifdef SUNXI_SPC_BASE
int i;
INFO("Configuring SPC Controller\n");
/* SPC setup: set all devices to non-secure */
- for (i = 0; i < 6; i++)
- mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff);
-#endif
+ for (i = 0; i < SUNXI_SPC_NUM_PORTS; i++)
+ mmio_write_32(SUNXI_SPC_DECPORT_SET_REG(i), 0xffffffff);
/* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */
mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7);
/* Set R_PRCM bus clocks to non-secure */
- mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x1);
+ mmio_write_32(SUNXI_R_PRCM_SEC_SWITCH_REG, 0x1);
/* Set all DMA channels (16 max.) to non-secure */
mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff);
diff --git a/plat/allwinner/sun50i_a64/include/sunxi_ccu.h b/plat/allwinner/sun50i_a64/include/sunxi_ccu.h
new file mode 100644
index 0000000..2a24886
--- /dev/null
+++ b/plat/allwinner/sun50i_a64/include/sunxi_ccu.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CCU_H
+#define SUNXI_CCU_H
+
+#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x02f0)
+
+#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x01d0)
+
+#endif /* SUNXI_CCU_H */
diff --git a/plat/allwinner/sun50i_a64/include/sunxi_mmap.h b/plat/allwinner/sun50i_a64/include/sunxi_mmap.h
index 9d2542f..6c847d3 100644
--- a/plat/allwinner/sun50i_a64/include/sunxi_mmap.h
+++ b/plat/allwinner/sun50i_a64/include/sunxi_mmap.h
@@ -36,7 +36,6 @@
#define SUNXI_MSGBOX_BASE 0x01c17000
#define SUNXI_SPINLOCK_BASE 0x01c18000
#define SUNXI_CCU_BASE 0x01c20000
-#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x2f0)
#define SUNXI_PIO_BASE 0x01c20800
#define SUNXI_TIMER_BASE 0x01c20c00
#define SUNXI_WDOG_BASE 0x01c20ca0
diff --git a/plat/allwinner/sun50i_a64/include/sunxi_spc.h b/plat/allwinner/sun50i_a64/include/sunxi_spc.h
new file mode 100644
index 0000000..5ba7e18
--- /dev/null
+++ b/plat/allwinner/sun50i_a64/include/sunxi_spc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_SPC_H
+#define SUNXI_SPC_H
+
+#define SUNXI_SPC_NUM_PORTS 6
+
+#define SUNXI_SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + 0x0004 + 0x0c * (p))
+#define SUNXI_SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + 0x0008 + 0x0c * (p))
+#define SUNXI_SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + 0x000c + 0x0c * (p))
+
+#endif /* SUNXI_SPC_H */
diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
index 5b7d76a..80a69c3 100644
--- a/plat/allwinner/sun50i_a64/sunxi_power.c
+++ b/plat/allwinner/sun50i_a64/sunxi_power.c
@@ -92,24 +92,16 @@
if (ret)
return ret;
- /* Start with 400 KHz to issue the I2C->RSB switch command. */
- ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 400000);
- if (ret)
- return ret;
-
- /*
- * Initiate an I2C transaction to write 0x7c into register 0x3e,
- * switching the PMIC to RSB mode.
- */
- ret = rsb_set_device_mode(0x7c3e00);
- if (ret)
- return ret;
-
- /* Now in RSB mode, switch to the recommended 3 MHz. */
+ /* Switch to the recommended 3 MHz bus clock. */
ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
if (ret)
return ret;
+ /* Initiate an I2C transaction to switch the PMIC to RSB mode. */
+ ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
+ if (ret)
+ return ret;
+
/* Associate the 8-bit runtime address with the 12-bit bus address. */
ret = rsb_assign_runtime_address(AXP803_HW_ADDR,
AXP803_RT_ADDR);
@@ -156,6 +148,11 @@
pmic = AXP803_RSB;
axp_setup_regulators(fdt);
+ /* Switch the PMIC back to I2C mode. */
+ ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
+ if (ret)
+ return ret;
+
break;
default:
return -ENODEV;
diff --git a/plat/allwinner/sun50i_h6/include/sunxi_ccu.h b/plat/allwinner/sun50i_h6/include/sunxi_ccu.h
new file mode 100644
index 0000000..85fbb90
--- /dev/null
+++ b/plat/allwinner/sun50i_h6/include/sunxi_ccu.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CCU_H
+#define SUNXI_CCU_H
+
+#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x0f00)
+
+#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x0290)
+
+#endif /* SUNXI_CCU_H */
diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
index 702db77..2d7b098 100644
--- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
+++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
@@ -30,8 +30,8 @@
#define SUNXI_DMA_BASE 0x03002000
#define SUNXI_MSGBOX_BASE 0x03003000
#define SUNXI_CCU_BASE 0x03001000
-#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0xf00)
#define SUNXI_PIO_BASE 0x0300b000
+#define SUNXI_SPC_BASE 0x03008000
#define SUNXI_TIMER_BASE 0x03009000
#define SUNXI_WDOG_BASE 0x030090a0
#define SUNXI_THS_BASE 0x05070400
@@ -55,6 +55,7 @@
#define SUNXI_R_TWD_BASE 0x07020800
#define SUNXI_R_CPUCFG_BASE 0x07000400
#define SUNXI_R_I2C_BASE 0x07081400
+#define SUNXI_R_RSB_BASE 0x07083000
#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_PIO_BASE 0x07022000
diff --git a/plat/allwinner/sun50i_h6/include/sunxi_spc.h b/plat/allwinner/sun50i_h6/include/sunxi_spc.h
new file mode 100644
index 0000000..0f5965b
--- /dev/null
+++ b/plat/allwinner/sun50i_h6/include/sunxi_spc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_SPC_H
+#define SUNXI_SPC_H
+
+#define SUNXI_SPC_NUM_PORTS 14
+
+#define SUNXI_SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + 0x0000 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + 0x0004 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + 0x0008 + 0x10 * (p))
+
+#endif /* SUNXI_SPC_H */
diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk
index 4ecc57c..1c98919 100644
--- a/plat/allwinner/sun50i_h6/platform.mk
+++ b/plat/allwinner/sun50i_h6/platform.mk
@@ -8,4 +8,4 @@
include plat/allwinner/common/allwinner-common.mk
BL31_SOURCES += drivers/allwinner/axp/axp805.c \
- drivers/mentor/i2c/mi2cv.c
+ drivers/allwinner/sunxi_rsb.c
diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c
index 443015b..a7865a5 100644
--- a/plat/allwinner/sun50i_h6/sunxi_power.c
+++ b/plat/allwinner/sun50i_h6/sunxi_power.c
@@ -6,20 +6,17 @@
*/
#include <errno.h>
-#include <string.h>
-#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/allwinner/axp.h>
-#include <drivers/delay_timer.h>
-#include <drivers/mentor/mi2cv.h>
-#include <lib/mmio.h>
+#include <drivers/allwinner/sunxi_rsb.h>
#include <sunxi_def.h>
#include <sunxi_mmap.h>
#include <sunxi_private.h>
-#define AXP805_ADDR 0x36
+#define AXP805_HW_ADDR 0x745
+#define AXP805_RT_ADDR 0x3a
static enum pmic_type {
UNKNOWN,
@@ -28,67 +25,67 @@
int axp_read(uint8_t reg)
{
- uint8_t val;
- int ret;
-
- ret = i2c_write(AXP805_ADDR, 0, 0, ®, 1);
- if (ret == 0)
- ret = i2c_read(AXP805_ADDR, 0, 0, &val, 1);
- if (ret) {
- ERROR("PMIC: Cannot read AXP805 register %02x\n", reg);
- return ret;
- }
-
- return val;
+ return rsb_read(AXP805_RT_ADDR, reg);
}
int axp_write(uint8_t reg, uint8_t val)
{
- int ret;
-
- ret = i2c_write(AXP805_ADDR, reg, 1, &val, 1);
- if (ret)
- ERROR("PMIC: Cannot write AXP805 register %02x\n", reg);
-
- return ret;
+ return rsb_write(AXP805_RT_ADDR, reg, val);
}
-static int axp805_probe(void)
+static int rsb_init(void)
{
int ret;
- /* Switch the AXP805 to master/single-PMIC mode. */
- ret = axp_write(0xff, 0x0);
+ ret = rsb_init_controller();
if (ret)
return ret;
- ret = axp_check_id();
+ /* Switch to the recommended 3 MHz bus clock. */
+ ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
if (ret)
return ret;
- return 0;
+ /* Initiate an I2C transaction to switch the PMIC to RSB mode. */
+ ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
+ if (ret)
+ return ret;
+
+ /* Associate the 8-bit runtime address with the 12-bit bus address. */
+ ret = rsb_assign_runtime_address(AXP805_HW_ADDR, AXP805_RT_ADDR);
+ if (ret)
+ return ret;
+
+ return axp_check_id();
}
int sunxi_pmic_setup(uint16_t socid, const void *fdt)
{
int ret;
- INFO("PMIC: Probing AXP805 on I2C\n");
+ INFO("PMIC: Probing AXP805 on RSB\n");
- ret = sunxi_init_platform_r_twi(SUNXI_SOC_H6, false);
+ ret = sunxi_init_platform_r_twi(socid, true);
if (ret)
return ret;
- /* initialise mi2cv driver */
- i2c_init((void *)SUNXI_R_I2C_BASE);
+ ret = rsb_init();
+ if (ret)
+ return ret;
- ret = axp805_probe();
+ /* Switch the AXP805 to master/single-PMIC mode. */
+ ret = axp_write(0xff, 0x0);
if (ret)
return ret;
pmic = AXP805;
axp_setup_regulators(fdt);
+ /* Switch the PMIC back to I2C mode. */
+ ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
+ if (ret)
+ return ret;
+
return 0;
}
@@ -96,10 +93,9 @@
{
switch (pmic) {
case AXP805:
- /* Re-initialise after rich OS might have used it. */
- sunxi_init_platform_r_twi(SUNXI_SOC_H6, false);
- /* initialise mi2cv driver */
- i2c_init((void *)SUNXI_R_I2C_BASE);
+ /* (Re-)init RSB in case the rich OS has disabled it. */
+ sunxi_init_platform_r_twi(SUNXI_SOC_H6, true);
+ rsb_init();
axp_power_off();
break;
default:
diff --git a/plat/amlogic/axg/include/platform_def.h b/plat/amlogic/axg/include/platform_def.h
index a47cf73..c97687e 100644
--- a/plat/amlogic/axg/include/platform_def.h
+++ b/plat/amlogic/axg/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,7 +24,7 @@
#define AML_PRIMARY_CPU U(0)
-#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
+#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT)
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 4b751fb..3ac1c01 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -59,7 +59,9 @@
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/cortex_a77.S \
lib/cpus/aarch64/cortex_a78.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index 934a01a..f4805db 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -5,13 +5,12 @@
*/
/dts-v1/;
-#define AFF 00
+#define AFF 00
#include "fvp-defs.dtsi"
#undef POST
-#define POST \
- enable-method = "psci"; \
- };
+#define POST \
+ };
/ {
compatible = "arm,ffa-core-manifest-1.0";
@@ -28,17 +27,14 @@
binary_size = <0x80000>;
};
- chosen {
- linux,initrd-start = <0>;
- linux,initrd-end = <0>;
- };
-
hypervisor {
compatible = "hafnium,hafnium";
vm1 {
is_ffa_partition;
debug_name = "cactus-primary";
load_address = <0x7000000>;
+ vcpu_count = <8>;
+ mem_size = <1048576>;
};
vm2 {
is_ffa_partition;
@@ -61,7 +57,11 @@
#size-cells = <0x0>;
CPU_0
- /* SPM(Hafnium) requires secondary cpu nodes are declared in descending order */
+
+ /*
+ * SPMC (Hafnium) requires secondary core nodes are declared
+ * in descending order.
+ */
CPU_7
CPU_6
CPU_5
@@ -71,7 +71,7 @@
CPU_1
};
- memory@60000000 {
+ memory@6000000 {
device_type = "memory";
reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */
};
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
index f5b31b4..57d6792 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
@@ -27,11 +27,6 @@
binary_size = <0x80000>;
};
- chosen {
- linux,initrd-start = <0>;
- linux,initrd-end = <0>;
- };
-
hypervisor {
compatible = "hafnium,hafnium";
vm1 {
@@ -39,6 +34,8 @@
debug_name = "op-tee";
load_address = <0x6280000>;
smc_whitelist = <0xbe000000>;
+ vcpu_count = <8>;
+ mem_size = <1048576>;
};
};
@@ -49,7 +46,7 @@
CPU_0
/*
- * SPMC(Hafnium) requires secondary core nodes are declared
+ * SPMC (Hafnium) requires secondary core nodes are declared
* in descending order.
*/
CPU_7
@@ -61,7 +58,7 @@
CPU_1
};
- memory@60000000 {
+ memory@6000000 {
device_type = "memory";
reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */
};
diff --git a/fdts/optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
similarity index 72%
rename from fdts/optee_sp_manifest.dts
rename to plat/arm/board/fvp/fdts/optee_sp_manifest.dts
index 02a5ef3..928d0d3 100644
--- a/fdts/optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
@@ -30,4 +30,20 @@
/* Boot protocol */
gp-register-num = <0x0>;
+
+ device-regions {
+ compatible = "arm,ffa-manifest-device-regions";
+
+ uart1 {
+ base-address = <0x00000000 0x1c0a0000>;
+ pages-count = <1>;
+ attributes = <0x3>; /* read-write */
+ };
+
+ gicd {
+ base-address = <0x00000000 0x2f000000>;
+ pages-count = <16>;
+ attributes = <0x3>; /* read-write */
+ };
+ };
};
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 50f6389..8defcf8 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -43,6 +43,15 @@
#define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000)
#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
+/*
+ * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to
+ * max size of BL32 image.
+ */
+#if defined(SPD_spmd)
+#define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE
+#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
+#endif
+
/* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 4da0d76..0a6fa56 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -118,7 +118,9 @@
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/cortex_a77.S \
lib/cpus/aarch64/cortex_a78.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index 4b621e3..f20397a 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk
@@ -69,7 +69,7 @@
USE_COHERENT_MEM := 0
# Enable the flag since N1SDP has a system level cache
-NEOVERSE_N1_EXTERNAL_LLC := 1
+NEOVERSE_Nx_EXTERNAL_LLC := 1
include plat/arm/common/arm_common.mk
include plat/arm/css/common/css_common.mk
include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/rddanielxlr/fdts/rddanielxlr_fw_config.dts b/plat/arm/board/rddanielxlr/fdts/rddanielxlr_fw_config.dts
deleted file mode 100644
index 9c9cefe..0000000
--- a/plat/arm/board/rddanielxlr/fdts/rddanielxlr_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-
-/ {
- dtb-registry {
- compatible = "fconf,dyn_cfg-dtb_registry";
-
- tb_fw-config {
- load-address = <0x0 0x4001300>;
- max-size = <0x200>;
- id = <TB_FW_CONFIG_ID>;
- };
-
- nt_fw-config {
- load-address = <0x0 0xFEF00000>;
- max-size = <0x0100000>;
- id = <NT_FW_CONFIG_ID>;
- };
- };
-};
diff --git a/plat/arm/board/rddanielxlr/fdts/rddanielxlr_nt_fw_config.dts b/plat/arm/board/rddanielxlr/fdts/rddanielxlr_nt_fw_config.dts
deleted file mode 100644
index 42d07a4..0000000
--- a/plat/arm/board/rddanielxlr/fdts/rddanielxlr_nt_fw_config.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
- /* compatible string */
- compatible = "arm,rd-daniel-xlr";
-
- /*
- * Place holder for system-id node with default values. The
- * value of platform-id and config-id will be set to the
- * correct values during the BL2 stage of boot.
- */
- system-id {
- platform-id = <0x0>;
- config-id = <0x0>;
- multi-chip-mode = <0x0>;
- };
-};
diff --git a/plat/arm/board/rddanielxlr/fdts/rddanielxlr_tb_fw_config.dts b/plat/arm/board/rddanielxlr/fdts/rddanielxlr_tb_fw_config.dts
deleted file mode 100644
index 49eda27..0000000
--- a/plat/arm/board/rddanielxlr/fdts/rddanielxlr_tb_fw_config.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
- tb_fw-config {
- compatible = "arm,tb_fw";
-
- /* Disable authentication for development */
- disable_auth = <0x0>;
-
- /*
- * The following two entries are placeholders for Mbed TLS
- * heap information. The default values don't matter since
- * they will be overwritten by BL1.
- * In case of having shared Mbed TLS heap between BL1 and BL2,
- * BL1 will populate these two properties with the respective
- * info about the shared heap. This info will be available for
- * BL2 in order to locate and re-use the heap.
- */
- mbedtls_heap_addr = <0x0 0x0>;
- mbedtls_heap_size = <0x0>;
- };
-};
diff --git a/plat/arm/board/rddanielxlr/rddanielxlr_trusted_boot.c b/plat/arm/board/rddanielxlr/rddanielxlr_trusted_boot.c
deleted file mode 100644
index 4592b8f..0000000
--- a/plat/arm/board/rddanielxlr/rddanielxlr_trusted_boot.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier ::= SEQUENCE {
- * algorithm OBJECT IDENTIFIER,
- * parameters ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- * digestAlgorithm AlgorithmIdentifier,
- * digest OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
- unsigned int *flags)
-{
- return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}
diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h
index 3fb6409..c39fe2b 100644
--- a/plat/arm/board/rde1edge/include/platform_def.h
+++ b/plat/arm/board/rde1edge/include/platform_def.h
@@ -9,7 +9,7 @@
#include <lib/utils_def.h>
-#include <sgi_base_platform_def.h>
+#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8)
diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk
index a7c0434..53074f4 100644
--- a/plat/arm/board/rde1edge/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -12,6 +12,8 @@
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_e1.S
+PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
+
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDE1EDGE_BASE}/rde1edge_err.c
diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h
index ab63e23..b167c46 100644
--- a/plat/arm/board/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/rdn1edge/include/platform_def.h
@@ -9,7 +9,7 @@
#include <lib/utils_def.h>
-#include <sgi_base_platform_def.h>
+#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk
index b313426..d65854f 100644
--- a/plat/arm/board/rdn1edge/platform.mk
+++ b/plat/arm/board/rdn1edge/platform.mk
@@ -15,6 +15,8 @@
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
+PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
+
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${RDN1EDGE_BASE}/rdn1edge_err.c
diff --git a/plat/arm/board/rdn1edge/rdn1edge_plat.c b/plat/arm/board/rdn1edge/rdn1edge_plat.c
index f62c6f4..1dbbf26 100644
--- a/plat/arm/board/rdn1edge/rdn1edge_plat.c
+++ b/plat/arm/board/rdn1edge/rdn1edge_plat.c
@@ -8,7 +8,7 @@
#include <drivers/arm/gic600_multichip.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-#include <sgi_base_platform_def.h>
+#include <sgi_soc_platform_def.h>
#include <sgi_plat.h>
#if defined(IMAGE_BL31)
diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts b/plat/arm/board/rdn2/fdts/rdn2_fw_config.dts
similarity index 100%
rename from plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts
rename to plat/arm/board/rdn2/fdts/rdn2_fw_config.dts
diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts b/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts
similarity index 92%
rename from plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts
rename to plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts
index 4d4580d..bbc36fc 100644
--- a/plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts
+++ b/plat/arm/board/rdn2/fdts/rdn2_nt_fw_config.dts
@@ -7,7 +7,7 @@
/dts-v1/;
/ {
/* compatible string */
- compatible = "arm,rd-daniel";
+ compatible = "arm,rd-n2";
/*
* Place holder for system-id node with default values. The
diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts b/plat/arm/board/rdn2/fdts/rdn2_tb_fw_config.dts
similarity index 100%
rename from plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts
rename to plat/arm/board/rdn2/fdts/rdn2_tb_fw_config.dts
diff --git a/plat/arm/board/rddaniel/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h
similarity index 87%
copy from plat/arm/board/rddaniel/include/platform_def.h
copy to plat/arm/board/rdn2/include/platform_def.h
index a118ca3..5561f8c 100644
--- a/plat/arm/board/rddaniel/include/platform_def.h
+++ b/plat/arm/board/rdn2/include/platform_def.h
@@ -9,27 +9,27 @@
#include <lib/utils_def.h>
-#include <sgi_base_platform_def.h>
+#include <sgi_soc_platform_def_v2.h>
#define PLAT_ARM_CLUSTER_COUNT U(16)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
#define CSS_SGI_MAX_PE_PER_CPU U(1)
-#define PLAT_CSS_MHU_BASE UL(0x45400000)
+#define PLAT_CSS_MHU_BASE UL(0x2A920000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE UL(0x21830000)
+#define PLAT_ARM_TZC_BASE UL(0x10820000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
#define TZC400_OFFSET UL(0x1000000)
-#define TZC400_COUNT 4
+#define TZC400_COUNT U(8)
#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
- (n * TZC400_OFFSET))
+ (n * TZC400_OFFSET))
#define TZC_NSAID_ALL_AP U(0)
#define TZC_NSAID_PCI U(1)
@@ -60,6 +60,6 @@
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
-#define PLAT_ARM_GICR_BASE UL(0x30140000)
+#define PLAT_ARM_GICR_BASE UL(0x301C0000)
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
new file mode 100644
index 0000000..6be6113
--- /dev/null
+++ b/plat/arm/board/rdn2/platform.mk
@@ -0,0 +1,59 @@
+# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# RD-N2 platform uses GIC-Clayton which is based on GICv4.1
+GIC_ENABLE_V4_EXTN := 1
+
+include plat/arm/css/sgi/sgi-common.mk
+
+RDN2_BASE = plat/arm/board/rdn2
+
+PLAT_INCLUDES += -I${RDN2_BASE}/include/
+
+SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n2.S
+
+PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat_v2.c
+
+BL1_SOURCES += ${SGI_CPU_SOURCES} \
+ ${RDN2_BASE}/rdn2_err.c
+
+BL2_SOURCES += ${RDN2_BASE}/rdn2_plat.c \
+ ${RDN2_BASE}/rdn2_security.c \
+ ${RDN2_BASE}/rdn2_err.c \
+ lib/utils/mem_region.c \
+ drivers/arm/tzc/tzc400.c \
+ plat/arm/common/arm_tzc400.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES += ${SGI_CPU_SOURCES} \
+ ${RDN2_BASE}/rdn2_plat.c \
+ ${RDN2_BASE}/rdn2_topology.c \
+ drivers/cfi/v2m/v2m_flash.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+BL1_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
+BL2_SOURCES += ${RDN2_BASE}/rdn2_trusted_boot.c
+endif
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \
+ ${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts
+FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
+TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+
+# Add the FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
+
+FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_nt_fw_config.dts
+NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
+
+# Add the NT_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
+
+override CTX_INCLUDE_AARCH32_REGS := 0
diff --git a/plat/arm/board/rddaniel/rddaniel_err.c b/plat/arm/board/rdn2/rdn2_err.c
similarity index 89%
copy from plat/arm/board/rddaniel/rddaniel_err.c
copy to plat/arm/board/rdn2/rdn2_err.c
index 5e10942..802ac21 100644
--- a/plat/arm/board/rddaniel/rddaniel_err.c
+++ b/plat/arm/board/rdn2/rdn2_err.c
@@ -7,7 +7,7 @@
#include <plat/arm/common/plat_arm.h>
/*
- * rddaniel error handler
+ * rdn2 error handler
*/
void __dead2 plat_arm_error_handler(int err)
{
diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c
new file mode 100644
index 0000000..5bf14e3
--- /dev/null
+++ b/plat/arm/board/rdn2/rdn2_plat.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/common/platform.h>
+#include <sgi_plat.h>
+
+unsigned int plat_arm_sgi_get_platform_id(void)
+{
+ return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
+ & SID_SYSTEM_ID_PART_NUM_MASK;
+}
+
+unsigned int plat_arm_sgi_get_config_id(void)
+{
+ return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
+}
+
+unsigned int plat_arm_sgi_get_multi_chip_mode(void)
+{
+ return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
+ SID_MULTI_CHIP_MODE_MASK) >>
+ SID_MULTI_CHIP_MODE_SHIFT;
+}
+
+void bl31_platform_setup(void)
+{
+ sgi_bl31_common_platform_setup();
+}
diff --git a/plat/arm/board/rdn2/rdn2_security.c b/plat/arm/board/rdn2/rdn2_security.c
new file mode 100644
index 0000000..9568b60
--- /dev/null
+++ b/plat/arm/board/rdn2/rdn2_security.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+
+
+static const arm_tzc_regions_info_t tzc_regions[] = {
+ ARM_TZC_REGIONS_DEF,
+ {}
+};
+
+/* Initialize the secure environment */
+void plat_arm_security_setup(void)
+{
+
+ int i;
+
+ for (i = 0; i < TZC400_COUNT; i++)
+ arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
+
+}
diff --git a/plat/arm/board/rddaniel/rddaniel_topology.c b/plat/arm/board/rdn2/rdn2_topology.c
similarity index 92%
copy from plat/arm/board/rddaniel/rddaniel_topology.c
copy to plat/arm/board/rdn2/rdn2_topology.c
index 55f5e04..5c2e287 100644
--- a/plat/arm/board/rddaniel/rddaniel_topology.c
+++ b/plat/arm/board/rdn2/rdn2_topology.c
@@ -10,7 +10,7 @@
/******************************************************************************
* The power domain tree descriptor.
******************************************************************************/
-const unsigned char rd_daniel_pd_tree_desc[] = {
+const unsigned char rd_n2_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
@@ -27,7 +27,7 @@
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ CSS_SGI_MAX_CPUS_PER_CLUSTER,
};
/*******************************************************************************
@@ -35,7 +35,7 @@
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
- return rd_daniel_pd_tree_desc;
+ return rd_n2_pd_tree_desc;
}
/*******************************************************************************
@@ -58,5 +58,5 @@
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF))
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
};
diff --git a/plat/arm/board/rddaniel/rddaniel_trusted_boot.c b/plat/arm/board/rdn2/rdn2_trusted_boot.c
similarity index 100%
rename from plat/arm/board/rddaniel/rddaniel_trusted_boot.c
rename to plat/arm/board/rdn2/rdn2_trusted_boot.c
diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts b/plat/arm/board/rdv1/fdts/rdv1_fw_config.dts
similarity index 100%
copy from plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts
copy to plat/arm/board/rdv1/fdts/rdv1_fw_config.dts
diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts b/plat/arm/board/rdv1/fdts/rdv1_nt_fw_config.dts
similarity index 92%
copy from plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts
copy to plat/arm/board/rdv1/fdts/rdv1_nt_fw_config.dts
index 4d4580d..62ba2c3 100644
--- a/plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts
+++ b/plat/arm/board/rdv1/fdts/rdv1_nt_fw_config.dts
@@ -7,7 +7,7 @@
/dts-v1/;
/ {
/* compatible string */
- compatible = "arm,rd-daniel";
+ compatible = "arm,rd-v1";
/*
* Place holder for system-id node with default values. The
diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts b/plat/arm/board/rdv1/fdts/rdv1_tb_fw_config.dts
similarity index 100%
copy from plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts
copy to plat/arm/board/rdv1/fdts/rdv1_tb_fw_config.dts
diff --git a/plat/arm/board/rddaniel/include/platform_def.h b/plat/arm/board/rdv1/include/platform_def.h
similarity index 97%
rename from plat/arm/board/rddaniel/include/platform_def.h
rename to plat/arm/board/rdv1/include/platform_def.h
index a118ca3..5b98b4e 100644
--- a/plat/arm/board/rddaniel/include/platform_def.h
+++ b/plat/arm/board/rdv1/include/platform_def.h
@@ -9,7 +9,7 @@
#include <lib/utils_def.h>
-#include <sgi_base_platform_def.h>
+#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(16)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
diff --git a/plat/arm/board/rddaniel/platform.mk b/plat/arm/board/rdv1/platform.mk
similarity index 65%
rename from plat/arm/board/rddaniel/platform.mk
rename to plat/arm/board/rdv1/platform.mk
index 7422d63..5033b18 100644
--- a/plat/arm/board/rddaniel/platform.mk
+++ b/plat/arm/board/rdv1/platform.mk
@@ -3,43 +3,45 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-# RD-Daniel platform uses GIC-Clayton which is based on GICv4.1
+# RD-V1 platform uses GIC-Clayton which is based on GICv4.1
GIC_ENABLE_V4_EXTN := 1
include plat/arm/css/sgi/sgi-common.mk
-RDDANIEL_BASE = plat/arm/board/rddaniel
+RDV1_BASE = plat/arm/board/rdv1
-PLAT_INCLUDES += -I${RDDANIEL_BASE}/include/
+PLAT_INCLUDES += -I${RDV1_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
-BL1_SOURCES += ${SGI_CPU_SOURCES} \
- ${RDDANIEL_BASE}/rddaniel_err.c
+PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
-BL2_SOURCES += ${RDDANIEL_BASE}/rddaniel_plat.c \
- ${RDDANIEL_BASE}/rddaniel_security.c \
- ${RDDANIEL_BASE}/rddaniel_err.c \
+BL1_SOURCES += ${SGI_CPU_SOURCES} \
+ ${RDV1_BASE}/rdv1_err.c
+
+BL2_SOURCES += ${RDV1_BASE}/rdv1_plat.c \
+ ${RDV1_BASE}/rdv1_security.c \
+ ${RDV1_BASE}/rdv1_err.c \
lib/utils/mem_region.c \
drivers/arm/tzc/tzc400.c \
plat/arm/common/arm_tzc400.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
- ${RDDANIEL_BASE}/rddaniel_plat.c \
- ${RDDANIEL_BASE}/rddaniel_topology.c \
+ ${RDV1_BASE}/rdv1_plat.c \
+ ${RDV1_BASE}/rdv1_topology.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += ${RDDANIEL_BASE}/rddaniel_trusted_boot.c
-BL2_SOURCES += ${RDDANIEL_BASE}/rddaniel_trusted_boot.c
+BL1_SOURCES += ${RDV1_BASE}/rdv1_trusted_boot.c
+BL2_SOURCES += ${RDV1_BASE}/rdv1_trusted_boot.c
endif
# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${RDDANIEL_BASE}/fdts/${PLAT}_fw_config.dts \
- ${RDDANIEL_BASE}/fdts/${PLAT}_tb_fw_config.dts
+FDT_SOURCES += ${RDV1_BASE}/fdts/${PLAT}_fw_config.dts \
+ ${RDV1_BASE}/fdts/${PLAT}_tb_fw_config.dts
FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
@@ -48,7 +50,7 @@
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-FDT_SOURCES += ${RDDANIEL_BASE}/fdts/${PLAT}_nt_fw_config.dts
+FDT_SOURCES += ${RDV1_BASE}/fdts/${PLAT}_nt_fw_config.dts
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
diff --git a/plat/arm/board/rddaniel/rddaniel_err.c b/plat/arm/board/rdv1/rdv1_err.c
similarity index 89%
rename from plat/arm/board/rddaniel/rddaniel_err.c
rename to plat/arm/board/rdv1/rdv1_err.c
index 5e10942..68f9a3e 100644
--- a/plat/arm/board/rddaniel/rddaniel_err.c
+++ b/plat/arm/board/rdv1/rdv1_err.c
@@ -7,7 +7,7 @@
#include <plat/arm/common/plat_arm.h>
/*
- * rddaniel error handler
+ * rdv1 error handler
*/
void __dead2 plat_arm_error_handler(int err)
{
diff --git a/plat/arm/board/rddaniel/rddaniel_plat.c b/plat/arm/board/rdv1/rdv1_plat.c
similarity index 100%
rename from plat/arm/board/rddaniel/rddaniel_plat.c
rename to plat/arm/board/rdv1/rdv1_plat.c
diff --git a/plat/arm/board/rddaniel/rddaniel_security.c b/plat/arm/board/rdv1/rdv1_security.c
similarity index 100%
rename from plat/arm/board/rddaniel/rddaniel_security.c
rename to plat/arm/board/rdv1/rdv1_security.c
diff --git a/plat/arm/board/rddaniel/rddaniel_topology.c b/plat/arm/board/rdv1/rdv1_topology.c
similarity index 96%
rename from plat/arm/board/rddaniel/rddaniel_topology.c
rename to plat/arm/board/rdv1/rdv1_topology.c
index 55f5e04..ab64fd8 100644
--- a/plat/arm/board/rddaniel/rddaniel_topology.c
+++ b/plat/arm/board/rdv1/rdv1_topology.c
@@ -10,7 +10,7 @@
/******************************************************************************
* The power domain tree descriptor.
******************************************************************************/
-const unsigned char rd_daniel_pd_tree_desc[] = {
+const unsigned char rd_v1_pd_tree_desc[] = {
PLAT_ARM_CLUSTER_COUNT,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
@@ -35,7 +35,7 @@
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
- return rd_daniel_pd_tree_desc;
+ return rd_v1_pd_tree_desc;
}
/*******************************************************************************
diff --git a/plat/arm/board/rddaniel/rddaniel_trusted_boot.c b/plat/arm/board/rdv1/rdv1_trusted_boot.c
similarity index 100%
copy from plat/arm/board/rddaniel/rddaniel_trusted_boot.c
copy to plat/arm/board/rdv1/rdv1_trusted_boot.c
diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts b/plat/arm/board/rdv1mc/fdts/rdv1mc_fw_config.dts
similarity index 100%
copy from plat/arm/board/rddaniel/fdts/rddaniel_fw_config.dts
copy to plat/arm/board/rdv1mc/fdts/rdv1mc_fw_config.dts
diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts b/plat/arm/board/rdv1mc/fdts/rdv1mc_nt_fw_config.dts
similarity index 92%
copy from plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts
copy to plat/arm/board/rdv1mc/fdts/rdv1mc_nt_fw_config.dts
index 4d4580d..71c7db3 100644
--- a/plat/arm/board/rddaniel/fdts/rddaniel_nt_fw_config.dts
+++ b/plat/arm/board/rdv1mc/fdts/rdv1mc_nt_fw_config.dts
@@ -7,7 +7,7 @@
/dts-v1/;
/ {
/* compatible string */
- compatible = "arm,rd-daniel";
+ compatible = "arm,rd-v1-mc";
/*
* Place holder for system-id node with default values. The
diff --git a/plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts b/plat/arm/board/rdv1mc/fdts/rdv1mc_tb_fw_config.dts
similarity index 100%
copy from plat/arm/board/rddaniel/fdts/rddaniel_tb_fw_config.dts
copy to plat/arm/board/rdv1mc/fdts/rdv1mc_tb_fw_config.dts
diff --git a/plat/arm/board/rddanielxlr/include/platform_def.h b/plat/arm/board/rdv1mc/include/platform_def.h
similarity index 96%
rename from plat/arm/board/rddanielxlr/include/platform_def.h
rename to plat/arm/board/rdv1mc/include/platform_def.h
index b1376b8..112b210 100644
--- a/plat/arm/board/rddanielxlr/include/platform_def.h
+++ b/plat/arm/board/rdv1mc/include/platform_def.h
@@ -8,7 +8,7 @@
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
-#include <sgi_base_platform_def.h>
+#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(4)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
diff --git a/plat/arm/board/rddanielxlr/platform.mk b/plat/arm/board/rdv1mc/platform.mk
similarity index 67%
rename from plat/arm/board/rddanielxlr/platform.mk
rename to plat/arm/board/rdv1mc/platform.mk
index 8cbad52..5072841 100644
--- a/plat/arm/board/rddanielxlr/platform.mk
+++ b/plat/arm/board/rdv1mc/platform.mk
@@ -9,40 +9,42 @@
include plat/arm/css/sgi/sgi-common.mk
-RDDANIELXLR_BASE = plat/arm/board/rddanielxlr
+RDV1MC_BASE = plat/arm/board/rdv1mc
-PLAT_INCLUDES += -I${RDDANIELXLR_BASE}/include/
+PLAT_INCLUDES += -I${RDV1MC_BASE}/include/
SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
-BL1_SOURCES += ${SGI_CPU_SOURCES} \
- ${RDDANIELXLR_BASE}/rddanielxlr_err.c
+PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
-BL2_SOURCES += ${RDDANIELXLR_BASE}/rddanielxlr_plat.c \
- ${RDDANIELXLR_BASE}/rddanielxlr_security.c \
- ${RDDANIELXLR_BASE}/rddanielxlr_err.c \
+BL1_SOURCES += ${SGI_CPU_SOURCES} \
+ ${RDV1MC_BASE}/rdv1mc_err.c
+
+BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_plat.c \
+ ${RDV1MC_BASE}/rdv1mc_security.c \
+ ${RDV1MC_BASE}/rdv1mc_err.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
- ${RDDANIELXLR_BASE}/rddanielxlr_plat.c \
- ${RDDANIELXLR_BASE}/rddanielxlr_topology.c \
+ ${RDV1MC_BASE}/rdv1mc_plat.c \
+ ${RDV1MC_BASE}/rdv1mc_topology.c \
drivers/cfi/v2m/v2m_flash.c \
drivers/arm/gic/v3/gic600_multichip.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += ${RDDANIELXLR_BASE}/rddanielxlr_trusted_boot.c
-BL2_SOURCES += ${RDDANIELXLR_BASE}/rddanielxlr_trusted_boot.c
+BL1_SOURCES += ${RDV1MC_BASE}/rdv1mc_trusted_boot.c
+BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_trusted_boot.c
endif
# Enable dynamic addition of MMAP regions in BL31
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${RDDANIELXLR_BASE}/fdts/${PLAT}_fw_config.dts \
- ${RDDANIELXLR_BASE}/fdts/${PLAT}_tb_fw_config.dts
+FDT_SOURCES += ${RDV1MC_BASE}/fdts/${PLAT}_fw_config.dts \
+ ${RDV1MC_BASE}/fdts/${PLAT}_tb_fw_config.dts
FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
@@ -53,11 +55,11 @@
$(eval $(call CREATE_SEQ,SEQ,4))
ifneq ($(CSS_SGI_CHIP_COUNT),$(filter $(CSS_SGI_CHIP_COUNT),$(SEQ)))
- $(error "Chip count for RD-Daniel Config-XLR should be either $(SEQ) \
+ $(error "Chip count for RD-V1-MC should be either $(SEQ) \
currently it is set to ${CSS_SGI_CHIP_COUNT}.")
endif
-FDT_SOURCES += ${RDDANIELXLR_BASE}/fdts/${PLAT}_nt_fw_config.dts
+FDT_SOURCES += ${RDV1MC_BASE}/fdts/${PLAT}_nt_fw_config.dts
NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
diff --git a/plat/arm/board/rddanielxlr/rddanielxlr_err.c b/plat/arm/board/rdv1mc/rdv1mc_err.c
similarity index 88%
rename from plat/arm/board/rddanielxlr/rddanielxlr_err.c
rename to plat/arm/board/rdv1mc/rdv1mc_err.c
index bff57cd..755a503 100644
--- a/plat/arm/board/rddanielxlr/rddanielxlr_err.c
+++ b/plat/arm/board/rdv1mc/rdv1mc_err.c
@@ -7,7 +7,7 @@
#include <plat/arm/common/plat_arm.h>
/*
- * rddanielxlr error handler
+ * rdv1mc error handler
*/
void __dead2 plat_arm_error_handler(int err)
{
diff --git a/plat/arm/board/rddanielxlr/rddanielxlr_plat.c b/plat/arm/board/rdv1mc/rdv1mc_plat.c
similarity index 82%
rename from plat/arm/board/rddanielxlr/rddanielxlr_plat.c
rename to plat/arm/board/rdv1mc/rdv1mc_plat.c
index 4b5f16a..d859400 100644
--- a/plat/arm/board/rddanielxlr/rddanielxlr_plat.c
+++ b/plat/arm/board/rdv1mc/rdv1mc_plat.c
@@ -8,11 +8,11 @@
#include <drivers/arm/gic600_multichip.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-#include <sgi_base_platform_def.h>
+#include <sgi_soc_platform_def.h>
#include <sgi_plat.h>
#if defined(IMAGE_BL31)
-static const mmap_region_t rddanielxlr_dynamic_mmap[] = {
+static const mmap_region_t rdv1mc_dynamic_mmap[] = {
ARM_MAP_SHARED_RAM_REMOTE_CHIP(1),
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
SOC_CSS_MAP_DEVICE_REMOTE_CHIP(1),
@@ -28,7 +28,7 @@
#endif
};
-static struct gic600_multichip_data rddanielxlr_multichip_data __init = {
+static struct gic600_multichip_data rdv1mc_multichip_data __init = {
.rt_owner_base = PLAT_ARM_GICD_BASE,
.rt_owner = 0,
.chip_count = CSS_SGI_CHIP_COUNT,
@@ -54,7 +54,7 @@
}
};
-static uintptr_t rddanielxlr_multichip_gicr_frames[] = {
+static uintptr_t rdv1mc_multichip_gicr_frames[] = {
/* Chip 0's GICR Base */
PLAT_ARM_GICR_BASE,
/* Chip 1's GICR BASE */
@@ -106,14 +106,14 @@
panic();
} else if ((plat_arm_sgi_get_multi_chip_mode() == 1) &&
(CSS_SGI_CHIP_COUNT > 1)) {
- INFO("Enabling support for multi-chip in RD-Daniel Cfg-XLR\n");
+ INFO("Enabling support for multi-chip in RD-V1-MC\n");
- for (i = 0; i < ARRAY_SIZE(rddanielxlr_dynamic_mmap); i++) {
+ for (i = 0; i < ARRAY_SIZE(rdv1mc_dynamic_mmap); i++) {
ret = mmap_add_dynamic_region(
- rddanielxlr_dynamic_mmap[i].base_pa,
- rddanielxlr_dynamic_mmap[i].base_va,
- rddanielxlr_dynamic_mmap[i].size,
- rddanielxlr_dynamic_mmap[i].attr);
+ rdv1mc_dynamic_mmap[i].base_pa,
+ rdv1mc_dynamic_mmap[i].base_va,
+ rdv1mc_dynamic_mmap[i].size,
+ rdv1mc_dynamic_mmap[i].attr);
if (ret != 0) {
ERROR("Failed to add dynamic mmap entry "
"(ret=%d)\n", ret);
@@ -122,8 +122,8 @@
}
plat_arm_override_gicr_frames(
- rddanielxlr_multichip_gicr_frames);
- gic600_multichip_init(&rddanielxlr_multichip_data);
+ rdv1mc_multichip_gicr_frames);
+ gic600_multichip_init(&rdv1mc_multichip_data);
}
sgi_bl31_common_platform_setup();
diff --git a/plat/arm/board/rddanielxlr/rddanielxlr_security.c b/plat/arm/board/rdv1mc/rdv1mc_security.c
similarity index 100%
rename from plat/arm/board/rddanielxlr/rddanielxlr_security.c
rename to plat/arm/board/rdv1mc/rdv1mc_security.c
diff --git a/plat/arm/board/rddanielxlr/rddanielxlr_topology.c b/plat/arm/board/rdv1mc/rdv1mc_topology.c
similarity index 95%
rename from plat/arm/board/rddanielxlr/rddanielxlr_topology.c
rename to plat/arm/board/rdv1mc/rdv1mc_topology.c
index 610e667..4486e5c 100644
--- a/plat/arm/board/rddanielxlr/rddanielxlr_topology.c
+++ b/plat/arm/board/rdv1mc/rdv1mc_topology.c
@@ -12,7 +12,7 @@
/******************************************************************************
* The power domain tree descriptor.
******************************************************************************/
-const unsigned char rd_daniel_xlr_pd_tree_desc_multi_chip[] = {
+const unsigned char rd_v1_mc_pd_tree_desc_multi_chip[] = {
((PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT)),
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
@@ -44,7 +44,7 @@
const unsigned char *plat_get_power_domain_tree_desc(void)
{
if (plat_arm_sgi_get_multi_chip_mode() == 1)
- return rd_daniel_xlr_pd_tree_desc_multi_chip;
+ return rd_v1_mc_pd_tree_desc_multi_chip;
panic();
}
diff --git a/plat/arm/board/rddaniel/rddaniel_trusted_boot.c b/plat/arm/board/rdv1mc/rdv1mc_trusted_boot.c
similarity index 100%
copy from plat/arm/board/rddaniel/rddaniel_trusted_boot.c
copy to plat/arm/board/rdv1mc/rdv1mc_trusted_boot.c
diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h
index 95986cf..c929334 100644
--- a/plat/arm/board/sgi575/include/platform_def.h
+++ b/plat/arm/board/sgi575/include/platform_def.h
@@ -9,7 +9,7 @@
#include <lib/utils_def.h>
-#include <sgi_base_platform_def.h>
+#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk
index 56f5733..89abcfe 100644
--- a/plat/arm/board/sgi575/platform.mk
+++ b/plat/arm/board/sgi575/platform.mk
@@ -12,6 +12,8 @@
SGI_CPU_SOURCES := lib/cpus/aarch64/cortex_a75.S
+PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c
+
BL1_SOURCES += ${SGI_CPU_SOURCES} \
${SGI575_BASE}/sgi575_err.c
diff --git a/plat/arm/board/tc0/fdts/tc0_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_fw_config.dts
index 381ce1f..4b6abd4 100644
--- a/plat/arm/board/tc0/fdts/tc0_fw_config.dts
+++ b/plat/arm/board/tc0/fdts/tc0_fw_config.dts
@@ -14,10 +14,16 @@
tb_fw-config {
load-address = <0x0 0x4001300>;
- max-size = <0x200>;
+ max-size = <0x400>;
id = <TB_FW_CONFIG_ID>;
};
+ tos_fw-config {
+ load-address = <0x0 0x04001700>;
+ max-size = <0x1000>;
+ id = <TOS_FW_CONFIG_ID>;
+ };
+
hw-config {
load-address = <0x0 0x83000000>;
max-size = <0x01000000>;
diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
new file mode 100644
index 0000000..b6c543a
--- /dev/null
+++ b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+/ {
+ compatible = "arm,ffa-core-manifest-1.0";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ attribute {
+ spmc_id = <0x8000>;
+ maj_ver = <0x1>;
+ min_ver = <0x0>;
+ exec_state = <0x0>;
+ load_address = <0x0 0xfd000000>;
+ entrypoint = <0x0 0xfd000000>;
+ binary_size = <0x80000>;
+ };
+
+ chosen {
+ linux,initrd-start = <0>;
+ linux,initrd-end = <0>;
+ };
+
+ hypervisor {
+ compatible = "hafnium,hafnium";
+ vm1 {
+ is_ffa_partition;
+ debug_name = "cactus-primary";
+ load_address = <0xfe000000>;
+ };
+ vm2 {
+ is_ffa_partition;
+ debug_name = "cactus-secondary";
+ load_address = <0xfe100000>;
+ vcpu_count = <4>;
+ mem_size = <1048576>;
+ };
+ vm3 {
+ is_ffa_partition;
+ debug_name = "cactus-tertiary";
+ load_address = <0xfe200000>;
+ vcpu_count = <4>;
+ mem_size = <1048576>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ CPU0:cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ /*
+ * SPM(Hafnium) requires secondary cpu nodes are declared in
+ * descending order
+ */
+ CPU3:cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ };
+
+ CPU2:cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+
+ CPU1:cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+ };
+
+ /* 32MB of TC0_TZC_DRAM1_BASE */
+ memory@fd000000 {
+ device_type = "memory";
+ reg = <0x0 0xfd000000 0x2000000>;
+ };
+};
diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
new file mode 100644
index 0000000..a58b911
--- /dev/null
+++ b/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+#define AFF 00
+
+#include "fvp-defs.dtsi"
+#undef POST
+#define POST \
+ };
+
+/ {
+ compatible = "arm,ffa-core-manifest-1.0";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ attribute {
+ spmc_id = <0x8000>;
+ maj_ver = <0x1>;
+ min_ver = <0x0>;
+ exec_state = <0x0>;
+ load_address = <0x0 0xfd000000>;
+ entrypoint = <0x0 0xfd000000>;
+ binary_size = <0x80000>;
+ };
+
+ /*
+ * temporary: This entry is added based on v2.4 hafnium and will be
+ * removed when rebased to upstream master.
+ */
+ chosen {
+ linux,initrd-start = <0>;
+ linux,initrd-end = <0>;
+ };
+
+ hypervisor {
+ compatible = "hafnium,hafnium";
+ vm1 {
+ is_ffa_partition;
+ debug_name = "op-tee";
+ load_address = <0xfd280000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ CPU_0
+
+ /*
+ * SPMC (Hafnium) requires secondary core nodes are declared
+ * in descending order.
+ */
+ CPU_3
+ CPU_2
+ CPU_1
+ };
+
+ /*
+ * temporary: This device-memory region is added based on v2.4 hafnium
+ * and will be removed when rebased to upstream master. As first
+ * Secure Partition no longer maps device memory.
+ */
+ device-memory@21000000 {
+ device_type = "device-memory";
+ reg = <0x0 0x21000000 0x5f000000>;
+ };
+
+ /* 32MB of TC0_TZC_DRAM1_BASE */
+ memory@fd000000 {
+ device_type = "memory";
+ reg = <0x0 0xfd000000 0x2000000>;
+ };
+};
diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
index 2fd25d9..de5f95d 100644
--- a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
+++ b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
@@ -24,4 +24,31 @@
mbedtls_heap_addr = <0x0 0x0>;
mbedtls_heap_size = <0x0>;
};
+
+ secure-partitions {
+ compatible = "arm,sp";
+#if OPTEE_SP_FW_CONFIG
+ op-tee {
+ uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
+ load-address = <0xfd280000>;
+ };
+#else
+ cactus-primary {
+ uuid = <0xb4b5671e 0x4a904fe1 0xb81ffb13 0xdae1dacb>;
+ load-address = <0xfe000000>;
+ owner = "SiP";
+ };
+
+ cactus-secondary {
+ uuid = <0xd1582309 0xf02347b9 0x827c4464 0xf5578fc8>;
+ load-address = <0xfe100000>;
+ owner = "Plat";
+ };
+
+ cactus-tertiary {
+ uuid = <0x79b55c73 0x1d8c44b9 0x859361e1 0x770ad8d2>;
+ load-address = <0xfe200000>;
+ };
+#endif
+ };
};
diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h
index 075c403..2ff2699 100644
--- a/plat/arm/board/tc0/include/platform_def.h
+++ b/plat/arm/board/tc0/include/platform_def.h
@@ -22,6 +22,49 @@
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
/*
+ * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC,
+ * its base is ARM_AP_TZC_DRAM1_BASE.
+ *
+ * Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for:
+ * - BL32_BASE when SPD_spmd is enabled
+ * - Region to load Trusted OS
+ */
+#define TC0_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
+ TC0_TZC_DRAM1_SIZE)
+#define TC0_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */
+#define TC0_TZC_DRAM1_END (TC0_TZC_DRAM1_BASE + \
+ TC0_TZC_DRAM1_SIZE - 1)
+
+#define TC0_NS_DRAM1_BASE ARM_DRAM1_BASE
+#define TC0_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ ARM_TZC_DRAM1_SIZE - \
+ TC0_TZC_DRAM1_SIZE)
+#define TC0_NS_DRAM1_END (TC0_NS_DRAM1_BASE + \
+ TC0_NS_DRAM1_SIZE - 1)
+
+/*
+ * Mappings for TC0 DRAM1 (non-secure) and TC0 TZC DRAM1 (secure)
+ */
+#define TC0_MAP_NS_DRAM1 MAP_REGION_FLAT( \
+ TC0_NS_DRAM1_BASE, \
+ TC0_NS_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+
+#define TC0_MAP_TZC_DRAM1 MAP_REGION_FLAT( \
+ TC0_TZC_DRAM1_BASE, \
+ TC0_TZC_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+/*
+ * Max size of SPMC is 2MB for tc0. With SPMD enabled this value corresponds to
+ * max size of BL32 image.
+ */
+#if defined(SPD_spmd)
+#define PLAT_ARM_SPMC_BASE TC0_TZC_DRAM1_BASE
+#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
+#endif
+
+/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
*/
@@ -69,9 +112,9 @@
* little space for growth.
*/
#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE 0x1E000
+# define PLAT_ARM_MAX_BL2_SIZE 0x20000
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x11000
+# define PLAT_ARM_MAX_BL2_SIZE 0x14000
#endif
/*
@@ -206,4 +249,18 @@
#define PLAT_ARM_TZC_NS_DEV_ACCESS \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
+/*
+ * The first region below, TC0_TZC_DRAM1_BASE (0xfd000000) to
+ * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as
+ * secure. The second region gives non secure access to rest of DRAM.
+ */
+#define TC0_TZC_REGIONS_DEF \
+ {TC0_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \
+ TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ {TC0_NS_DRAM1_BASE, TC0_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
+ PLAT_ARM_TZC_NS_DEV_ACCESS}
+
+/* virtual address used by dynamic mem_protect for chunk_base */
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/tc0/platform.mk b/plat/arm/board/tc0/platform.mk
index 05d691e..6cc5f46 100644
--- a/plat/arm/board/tc0/platform.mk
+++ b/plat/arm/board/tc0/platform.mk
@@ -85,6 +85,18 @@
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
+ifeq (${SPD},spmd)
+ifeq ($(ARM_SPMC_MANIFEST_DTS),)
+ARM_SPMC_MANIFEST_DTS := ${TC0_BASE}/fdts/${PLAT}_spmc_manifest.dts
+endif
+
+FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
+TC0_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
+
+# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TC0_TOS_FW_CONFIG},--tos-fw-config,${TC0_TOS_FW_CONFIG}))
+endif
+
#Device tree
TC0_HW_CONFIG_DTS := fdts/tc0.dts
TC0_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
@@ -98,6 +110,8 @@
override CTX_INCLUDE_PAUTH_REGS := 1
+override ENABLE_SPE_FOR_LOWER_ELS := 0
+
include plat/arm/common/arm_common.mk
include plat/arm/css/common/css_common.mk
include plat/arm/soc/common/soc_css.mk
diff --git a/plat/arm/board/tc0/tc0_plat.c b/plat/arm/board/tc0/tc0_plat.c
index 0546192..b5698c0 100644
--- a/plat/arm/board/tc0/tc0_plat.c
+++ b/plat/arm/board/tc0/tc0_plat.c
@@ -38,7 +38,10 @@
ARM_MAP_SHARED_RAM,
TC0_FLASH0_RO,
TC0_MAP_DEVICE,
- ARM_MAP_NS_DRAM1,
+ TC0_MAP_NS_DRAM1,
+#if defined(SPD_spmd)
+ TC0_MAP_TZC_DRAM1,
+#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
@@ -48,6 +51,10 @@
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
ARM_MAP_BL1_RW,
#endif
+#ifdef SPD_opteed
+ ARM_MAP_OPTEE_CORE_MEM,
+ ARM_OPTEE_PAGEABLE_LOAD_MEM,
+#endif
{0}
};
#endif
diff --git a/plat/arm/board/tc0/tc0_security.c b/plat/arm/board/tc0/tc0_security.c
index 5f1cb11..f543762 100644
--- a/plat/arm/board/tc0/tc0_security.c
+++ b/plat/arm/board/tc0/tc0_security.c
@@ -8,7 +8,7 @@
#include <platform_def.h>
static const arm_tzc_regions_info_t tzc_regions[] = {
- ARM_TZC_REGIONS_DEF,
+ TC0_TZC_REGIONS_DEF,
{}
};
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index fc238b1..81ef6e7 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -47,9 +47,12 @@
#if RECLAIM_INIT_CODE
IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE);
IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED);
+IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED);
#define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \
~(PAGE_SIZE - 1))
+#define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \
+ ~(PAGE_SIZE - 1))
#define MAP_BL_INIT_CODE MAP_REGION_FLAT( \
BL_INIT_CODE_BASE, \
@@ -291,14 +294,39 @@
#if RECLAIM_INIT_CODE
/*
- * Zero out and make RW memory used to store image boot time code so it can
- * be reclaimed during runtime
+ * Make memory for image boot time code RW to reclaim it as stack for the
+ * secondary cores, or RO where it cannot be reclaimed:
+ *
+ * |-------- INIT SECTION --------|
+ * -----------------------------------------
+ * | CORE 0 | CORE 1 | CORE 2 | EXTRA |
+ * | STACK | STACK | STACK | SPACE |
+ * -----------------------------------------
+ * <-------------------> <------>
+ * MAKE RW AND XN MAKE
+ * FOR STACKS RO AND XN
*/
void arm_free_init_memory(void)
{
- int ret = xlat_change_mem_attributes(BL_INIT_CODE_BASE,
+ int ret = 0;
+
+ if (BL_STACKS_END < BL_INIT_CODE_END) {
+ /* Reclaim some of the init section as stack if possible. */
+ if (BL_INIT_CODE_BASE < BL_STACKS_END) {
+ ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
+ BL_STACKS_END - BL_INIT_CODE_BASE,
+ MT_RW_DATA);
+ }
+ /* Make the rest of the init section read-only. */
+ ret |= xlat_change_mem_attributes(BL_STACKS_END,
+ BL_INIT_CODE_END - BL_STACKS_END,
+ MT_RO_DATA);
+ } else {
+ /* The stacks cover the init section, so reclaim it all. */
+ ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
BL_INIT_CODE_END - BL_INIT_CODE_BASE,
MT_RW_DATA);
+ }
if (ret != 0) {
ERROR("Could not reclaim initialization code");
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index 159084f..b805746 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -9,12 +9,9 @@
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <plat/arm/board/common/board_css_def.h>
-#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/common/arm_def.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/arm/css/common/css_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
#include <plat/common/common_def.h>
#define PLATFORM_CORE_COUNT (CSS_SGI_CHIP_COUNT * \
diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
new file mode 100644
index 0000000..03f1073
--- /dev/null
+++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_SOC_CSS_DEF_V2_H
+#define SGI_SOC_CSS_DEF_V2_H
+
+#include <lib/utils_def.h>
+#include <plat/common/common_def.h>
+
+/*
+ * Definitions common to all ARM CSS SoCs
+ */
+
+/* Following covers ARM CSS SoC Peripherals */
+
+#define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000)
+#define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000)
+
+#define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000)
+#define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000)
+
+#define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000)
+
+/* PL011 UART related constants */
+#define SOC_CSS_UART1_BASE UL(0x0ef80000)
+#define SOC_CSS_UART0_BASE UL(0x0ef70000)
+
+/* Memory controller */
+#define SOC_MEMCNTRL_BASE UL(0x10000000)
+#define SOC_MEMCNTRL_SIZE UL(0x10000000)
+
+#define SOC_CSS_UART0_CLK_IN_HZ UL(7372800)
+#define SOC_CSS_UART1_CLK_IN_HZ UL(7372800)
+
+/* SoC NIC-400 Global Programmers View (GPV) */
+#define SOC_CSS_NIC400_BASE UL(0x0ED00000)
+
+#define SOC_CSS_NIC400_USB_EHCI U(0)
+#define SOC_CSS_NIC400_TLX_MASTER U(1)
+#define SOC_CSS_NIC400_USB_OHCI U(2)
+#define SOC_CSS_NIC400_PL354_SMC U(3)
+/*
+ * The apb4_bridge controls access to:
+ * - the PCIe configuration registers
+ * - the MMU units for USB, HDLCD and DMA
+ */
+#define SOC_CSS_NIC400_APB4_BRIDGE U(4)
+
+/* Non-volatile counters */
+#define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000)
+#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000)
+#define TFW_NVCTR_SIZE U(4)
+#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
+#define NTFW_CTR_SIZE U(4)
+
+/* Keys */
+#define SOC_KEYS_BASE UL(0x0EE80000)
+#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
+#define TZ_PUB_KEY_HASH_SIZE U(32)
+#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
+#define HU_KEY_SIZE U(16)
+#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
+#define END_KEY_SIZE U(32)
+
+#define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
+ SOC_PLATFORM_PERIPH_BASE, \
+ SOC_PLATFORM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
+ SOC_SYSTEM_PERIPH_BASE, \
+ SOC_SYSTEM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define SOC_MEMCNTRL_MAP_DEVICE MAP_REGION_FLAT( \
+ SOC_MEMCNTRL_BASE, \
+ SOC_MEMCNTRL_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+/*
+ * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs.
+ */
+#define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5)
+#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12)
+
+/*
+ * Required platform porting definitions common to all ARM CSS SoCs
+ */
+/* 2MB used for SCP DDR retraining */
+#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x00200000)
+
+/* V2M motherboard system registers & offsets */
+#define V2M_SYSREGS_BASE UL(0x0C010000)
+#define V2M_SYS_LED U(0x8)
+
+/*
+ * V2M sysled bit definitions. The values written to this
+ * register are defined in arch.h & runtime_svc.h. Only
+ * used by the primary cpu to diagnose any cold boot issues.
+ *
+ * SYS_LED[0] - Security state (S=0/NS=1)
+ * SYS_LED[2:1] - Exception Level (EL3-EL0)
+ * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
+ *
+ */
+#define V2M_SYS_LED_SS_SHIFT U(0)
+#define V2M_SYS_LED_EL_SHIFT U(1)
+#define V2M_SYS_LED_EC_SHIFT U(3)
+
+#define V2M_SYS_LED_SS_MASK U(0x01)
+#define V2M_SYS_LED_EL_MASK U(0x03)
+#define V2M_SYS_LED_EC_MASK U(0x1f)
+
+/* NOR Flash */
+#define V2M_FLASH0_BASE UL(0x08000000)
+#define V2M_FLASH0_SIZE UL(0x04000000)
+#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
+
+/*
+ * The flash can be mapped either as read-only or read-write.
+ *
+ * If it is read-write then it should also be mapped as device memory because
+ * NOR flash programming involves sending a fixed, ordered sequence of commands.
+ *
+ * If it is read-only then it should also be mapped as:
+ * - Normal memory, because reading from NOR flash is transparent, it is like
+ * reading from RAM.
+ * - Non-executable by default. If some parts of the flash need to be executable
+ * then platform code is responsible for re-mapping the appropriate portion
+ * of it as executable.
+ */
+#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
+ V2M_FLASH0_SIZE, \
+ MT_RO_DATA | MT_SECURE)
+
+#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RO | MT_SECURE)
+
+/* Platform ID address */
+#define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0)
+
+/* Platform ID related accessors */
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F)
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08)
+#define BOARD_CSS_PLAT_TYPE_RTL U(0x00)
+#define BOARD_CSS_PLAT_TYPE_FPGA U(0x01)
+#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
+#define BOARD_CSS_PLAT_TYPE_FVP U(0x03)
+
+#ifndef __ASSEMBLER__
+
+#include <lib/mmio.h>
+
+#define BOARD_CSS_GET_PLAT_TYPE(addr) \
+ ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
+ >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
+
+#endif /* __ASSEMBLER__ */
+
+
+#define MAX_IO_DEVICES U(3)
+#define MAX_IO_HANDLES U(4)
+
+/* Reserve the last block of flash for PSCI MEM PROTECT flag */
+#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/* UART related constants */
+#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
+
+#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
+
+#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
+#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
+
+#endif /* SGI_SOC_CSS_DEF_V2_H */
diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def.h b/plat/arm/css/sgi/include/sgi_soc_platform_def.h
new file mode 100644
index 0000000..d7a839a
--- /dev/null
+++ b/plat/arm/css/sgi/include/sgi_soc_platform_def.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_SOC_PLATFORM_DEF_H
+#define SGI_SOC_PLATFORM_DEF_H
+
+#include <sgi_base_platform_def.h>
+#include <plat/arm/board/common/board_css_def.h>
+#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/soc/common/soc_css_def.h>
+
+#endif /* SGI_SOC_PLATFORM_DEF_H */
diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h
new file mode 100644
index 0000000..cb747c3
--- /dev/null
+++ b/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_SOC_PLATFORM_DEF_V2_H
+#define SGI_SOC_PLATFORM_DEF_V2_H
+
+#include <sgi_base_platform_def.h>
+#include <sgi_soc_css_def_v2.h>
+
+#endif /* SGI_SOC_PLATFORM_DEF_V2_H */
diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h
index f4c5300..ecf6d93 100644
--- a/plat/arm/css/sgi/include/sgi_variant.h
+++ b/plat/arm/css/sgi/include/sgi_variant.h
@@ -14,8 +14,11 @@
#define RD_N1E1_EDGE_SID_VER_PART_NUM 0x0786
#define RD_E1_EDGE_CONFIG_ID 0x2
-/* SID Version values for RD-Daniel */
-#define RD_DANIEL_SID_VER_PART_NUM 0x078a
+/* SID Version values for RD-V1 */
+#define RD_V1_SID_VER_PART_NUM 0x078a
+
+/* SID Version values for RD-N2 */
+#define RD_N2_SID_VER_PART_NUM 0x07B7
/* Structure containing SGI platform variant information */
typedef struct sgi_platform_info {
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index 6b9e0cd..615f53d 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -32,8 +32,7 @@
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c
-PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c \
- ${CSS_ENT_BASE}/aarch64/sgi_helper.S
+PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/aarch64/sgi_helper.S
BL1_SOURCES += ${INTERCONNECT_SOURCES} \
drivers/arm/sbsa/sbsa.c
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index a4aed00..89e2cab 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -74,7 +74,8 @@
scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
{
if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
- sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM) {
+ sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
+ sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM) {
if (channel_id >= ARRAY_SIZE(rd_n1e1_edge_scmi_plat_info))
panic();
return &rd_n1e1_edge_scmi_plat_info[channel_id];
@@ -107,12 +108,12 @@
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
{
/*
- * For RD-E1-Edge and RD-Daniel platforms, only CPU power ON/OFF
+ * For RD-E1-Edge and RD-V1 platforms, only CPU power ON/OFF
* PSCI platform callbacks are supported.
*/
if (((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
(sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)) ||
- (sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM)) {
+ (sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM)) {
ops->cpu_standby = NULL;
ops->system_off = NULL;
ops->system_reset = NULL;
diff --git a/plat/arm/css/sgi/sgi_plat_v2.c b/plat/arm/css/sgi/sgi_plat_v2.c
new file mode 100644
index 0000000..a770255
--- /dev/null
+++ b/plat/arm/css/sgi/sgi_plat_v2.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <drivers/arm/sbsa.h>
+
+/*
+ * Table of regions for different BL stages to map using the MMU.
+ */
+#if IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ SGI_MAP_FLASH0_RO,
+ CSS_SGI_MAP_DEVICE,
+ SOC_PLATFORM_PERIPH_MAP_DEVICE,
+ SOC_SYSTEM_PERIPH_MAP_DEVICE,
+ {0}
+};
+#endif
+
+#if IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ SGI_MAP_FLASH0_RO,
+#ifdef PLAT_ARM_MEM_PROT_ADDR
+ ARM_V2M_MAP_MEM_PROTECT,
+#endif
+ CSS_SGI_MAP_DEVICE,
+ SOC_MEMCNTRL_MAP_DEVICE,
+ SOC_PLATFORM_PERIPH_MAP_DEVICE,
+ SOC_SYSTEM_PERIPH_MAP_DEVICE,
+ ARM_MAP_NS_DRAM1,
+#if ARM_BL31_IN_DRAM
+ ARM_MAP_BL31_SEC_DRAM,
+#endif
+#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
+ ARM_MAP_BL1_RW,
+#endif
+ {0}
+};
+#endif
+
+#if IMAGE_BL31
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+#ifdef PLAT_ARM_MEM_PROT_ADDR
+ ARM_V2M_MAP_MEM_PROTECT,
+#endif
+ CSS_SGI_MAP_DEVICE,
+ SOC_PLATFORM_PERIPH_MAP_DEVICE,
+ SOC_SYSTEM_PERIPH_MAP_DEVICE,
+ {0}
+};
+
+#endif
+
+ARM_CASSERT_MMAP
+
+#if TRUSTED_BOARD_BOOT
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
+
+void plat_arm_secure_wdt_start(void)
+{
+ sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+}
+
+void plat_arm_secure_wdt_stop(void)
+{
+ sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+}
diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S
index ee0dbb4..c0668ea 100644
--- a/plat/common/aarch64/platform_mp_stack.S
+++ b/plat/common/aarch64/platform_mp_stack.S
@@ -14,7 +14,7 @@
.weak plat_set_my_stack
/* ---------------------------------------------------------------------
- * When the compatility layer is disabled, the platform APIs
+ * When the compatibility layer is disabled, the platform APIs
* plat_get_my_stack() and plat_set_my_stack() are supported by the
* platform and the previous APIs platform_get_stack() and
* platform_set_stack() are defined in terms of new APIs making use of
@@ -32,42 +32,9 @@
* -----------------------------------------------------
*/
func plat_get_my_stack
-#if (defined(IMAGE_BL31) && RECLAIM_INIT_CODE)
-#if (PLATFORM_CORE_COUNT == 1)
- /* Single CPU */
- adrp x0, __PRIMARY_STACK__
- add x0, x0, :lo12:__PRIMARY_STACK__
- ret
-#else
- mov x10, x30
- bl plat_my_core_pos
- cbnz x0, 2f
-
- /* Primary CPU */
- adrp x0, __PRIMARY_STACK__
- add x0, x0, :lo12:__PRIMARY_STACK__
- ret x10
-
- /* Secondary CPU */
-2: sub x0, x0, #(PLATFORM_CORE_COUNT - 1)
- adrp x1, __STACKS_END__
- adrp x2, __STACK_SIZE__
- add x1, x1, :lo12:__STACKS_END__
- add x2, x2, :lo12:__STACK_SIZE__
-
- madd x0, x0, x2, x1
- bic x0, x0, #(CACHE_WRITEBACK_GRANULE - 1)
- ret x10
-#endif
- /* Prevent linker from removal of stack section */
- .quad platform_normal_stacks
-
-#else /* !(IMAGE_BL31 && RECLAIM_INIT_CODE) */
mov x10, x30
get_my_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE
ret x10
-
-#endif /* IMAGE_BL31 && RECLAIM_INIT_CODE */
endfunc plat_get_my_stack
/* -----------------------------------------------------
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 6f32aff..168236b 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -39,6 +39,8 @@
{
static console_t console;
+ mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
+
console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
&console);
/*
@@ -99,6 +101,8 @@
******************************************************************************/
void bl31_platform_setup(void)
{
+ socfpga_delay_timer_init();
+
/* Initialize the gic cpu and distributor interfaces */
gicv2_driver_init(&plat_gicv2_gic_data);
gicv2_distif_init();
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index 814d9c6..bf5cc14 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -25,7 +25,8 @@
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
- plat/intel/soc/common/aarch64/plat_helpers.S
+ plat/intel/soc/common/aarch64/plat_helpers.S \
+ plat/intel/soc/common/socfpga_delay_timer.c
BL2_SOURCES += \
common/desc_image_load.c \
@@ -44,7 +45,6 @@
plat/intel/soc/agilex/soc/agilex_mmc.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
- plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_emac.c \
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 046d138..55600ee 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -134,6 +134,8 @@
#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16)
#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8)
+#define PLAT_SEC_WARM_ENTRY 0
+
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index 3c56d15..923c4f1 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,35 +9,16 @@
#include <lib/utils_def.h>
+
#define MBOX_OFFSET 0xffa30000
-#define MBOX_MAX_JOB_ID 0xf
-#define MBOX_ATF_CLIENT_ID 0x1
-#define MBOX_JOB_ID 0x1
+#define MBOX_ATF_CLIENT_ID 0x1U
+#define MBOX_MAX_JOB_ID 0xFU
+#define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U)
+#define MBOX_JOB_ID MBOX_MAX_JOB_ID
-/* Mailbox interrupt flags and masks */
-#define MBOX_INT_FLAG_COE 0x1
-#define MBOX_INT_FLAG_RIE 0x2
-#define MBOX_INT_FLAG_UAE 0x100
-#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
-#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8)))
-/* Mailbox response and status */
-#define MBOX_RESP_BUFFER_SIZE 16
-#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff)
-#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
-#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
-#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
-#define MBOX_STATUS_UA_MASK (1<<8)
-
-/* Mailbox command and response */
-#define MBOX_CMD_FREE_OFFSET 0x14
-#define MBOX_CMD_BUFFER_SIZE 32
-#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
-#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
-#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
-#define MBOX_INDIRECT (1 << 11)
-#define MBOX_INSUFFICIENT_BUFFER -2
+/* Mailbox Shared Memory Register Map */
#define MBOX_CIN 0x00
#define MBOX_ROUT 0x04
#define MBOX_URG 0x08
@@ -48,60 +29,63 @@
#define MBOX_CMD_BUFFER 0x40
#define MBOX_RESP_BUFFER 0xC0
-#define MBOX_RESP_BUFFER_SIZE 16
-#define MBOX_RESP_OK 0
-#define MBOX_RESP_INVALID_CMD 1
-#define MBOX_RESP_UNKNOWN_BR 2
-#define MBOX_RESP_UNKNOWN 3
-#define MBOX_RESP_NOT_CONFIGURED 256
-
/* Mailbox SDM doorbell */
#define MBOX_DOORBELL_TO_SDM 0x400
#define MBOX_DOORBELL_FROM_SDM 0x480
-/* Mailbox QSPI commands */
-#define MBOX_CMD_RESTART 2
-#define MBOX_CMD_QSPI_OPEN 50
-#define MBOX_CMD_QSPI_CLOSE 51
-#define MBOX_CMD_QSPI_DIRECT 59
-#define MBOX_CMD_GET_IDCODE 16
-#define MBOX_CMD_QSPI_SET_CS 52
-/* Mailbox CANCEL command */
-#define MBOX_CMD_CANCEL 0x3
+/* Mailbox commands */
-/* Mailbox REBOOT commands */
-#define MBOX_CMD_REBOOT_HPS 71
+#define MBOX_CMD_NOOP 0x00
+#define MBOX_CMD_SYNC 0x01
+#define MBOX_CMD_RESTART 0x02
+#define MBOX_CMD_CANCEL 0x03
+#define MBOX_CMD_GET_IDCODE 0x10
+#define MBOX_CMD_REBOOT_HPS 0x47
-/* Mailbox RSU commands */
-#define MBOX_GET_SUBPARTITION_TABLE 90
-#define MBOX_RSU_STATUS 91
-#define MBOX_RSU_UPDATE 92
+/* Reconfiguration Commands */
+#define MBOX_CONFIG_STATUS 0x04
+#define MBOX_RECONFIG 0x06
+#define MBOX_RECONFIG_DATA 0x08
+#define MBOX_RECONFIG_STATUS 0x09
-/* Mailbox RSU macros */
-#define RSU_VERSION_ACMF BIT(8)
-#define RSU_VERSION_ACMF_MASK 0xff00
+/* QSPI Commands */
+#define MBOX_CMD_QSPI_OPEN 0x32
+#define MBOX_CMD_QSPI_CLOSE 0x33
+#define MBOX_CMD_QSPI_SET_CS 0x34
+#define MBOX_CMD_QSPI_DIRECT 0x3B
-/* HPS stage notify command */
-#define MBOX_HPS_STAGE_NOTIFY 93
+/* RSU Commands */
+#define MBOX_GET_SUBPARTITION_TABLE 0x5A
+#define MBOX_RSU_STATUS 0x5B
+#define MBOX_RSU_UPDATE 0x5C
+#define MBOX_HPS_STAGE_NOTIFY 0x5D
+
+
+/* Mailbox Definitions */
+
+#define CMD_DIRECT 0
+#define CMD_INDIRECT 1
+#define CMD_CASUAL 0
+#define CMD_URGENT 1
+
+#define MBOX_RESP_BUFFER_SIZE 16
+#define MBOX_CMD_BUFFER_SIZE 32
/* Execution states for HPS_STAGE_NOTIFY */
#define HPS_EXECUTION_STATE_FSBL 0
#define HPS_EXECUTION_STATE_SSBL 1
#define HPS_EXECUTION_STATE_OS 2
-/* Mailbox reconfiguration commands */
-#define MBOX_CONFIG_STATUS 4
-#define MBOX_RECONFIG 6
-#define MBOX_RECONFIG_DATA 8
-#define MBOX_RECONFIG_STATUS 9
-
-/* Generic error handling */
-#define MBOX_TIMEOUT -2047
+/* Status Response */
+#define MBOX_RET_OK 0
+#define MBOX_RET_ERROR -1
#define MBOX_NO_RESPONSE -2
#define MBOX_WRONG_ID -3
+#define MBOX_BUFFER_FULL -4
+#define MBOX_TIMEOUT -2047
-/* Mailbox status */
+/* Reconfig Status Response */
#define RECONFIG_STATUS_STATE 0
#define RECONFIG_STATUS_PIN_STATUS 2
#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
@@ -121,17 +105,53 @@
#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
-void mailbox_set_int(int interrupt_input);
+
+/* Mailbox Macros */
+
+/* Mailbox interrupt flags and masks */
+#define MBOX_INT_FLAG_COE 0x1
+#define MBOX_INT_FLAG_RIE 0x2
+#define MBOX_INT_FLAG_UAE 0x100
+#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
+#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8)))
+
+/* Mailbox response and status */
+#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff)
+#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
+#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
+#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
+#define MBOX_STATUS_UA_MASK (1<<8)
+
+/* Mailbox command and response */
+#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
+#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
+#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
+#define MBOX_INDIRECT(val) ((val) << 11)
+#define MBOX_CMD_MASK(header) ((header) & 0x7ff)
+
+/* RSU Macros */
+#define RSU_VERSION_ACMF BIT(8)
+#define RSU_VERSION_ACMF_MASK 0xff00
+
+
+/* Mailbox Function Definitions */
+
+void mailbox_set_int(uint32_t interrupt_input);
int mailbox_init(void);
void mailbox_set_qspi_close(void);
void mailbox_set_qspi_open(void);
void mailbox_set_qspi_direct(void);
-int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
- int len, int urgent, uint32_t *response, int resp_len);
-int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
- int len, int urgent);
-int mailbox_read_response(int job_id, uint32_t *response, int resp_len);
-int mailbox_get_qspi_clock(void);
+
+int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args,
+ unsigned int len, uint32_t urgent, uint32_t *response,
+ unsigned int resp_len);
+int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args,
+ unsigned int len, unsigned int indirect);
+int mailbox_read_response(uint32_t *job_id, uint32_t *response,
+ unsigned int resp_len);
+unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
+ unsigned int resp_len);
+
void mailbox_reset_cold(void);
void mailbox_clear_response(void);
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 19a52f7..92adfa3 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,24 +17,34 @@
/* SMC SiP service function identifier */
+
+/* FPGA Reconfig */
#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
+
+/* Secure Register Access */
#define INTEL_SIP_SMC_REG_READ 0xC2000007
#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
+
+/* Remote System Update */
#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
-#define INTEL_SIP_LEGACY_SMC_ECC_DBE 0xC200000D
#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
+
+/* Send Mailbox Command */
#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
+
+/* SiP Definitions */
+
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
-#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 16777216
+#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
/* SMC function IDs for SiP Service queries */
#define SIP_SVC_CALL_COUNT 0x8200ff00
@@ -45,4 +55,19 @@
#define SIP_SVC_VERSION_MAJOR 0
#define SIP_SVC_VERSION_MINOR 1
+
+/* Structure Definitions */
+struct fpga_config_info {
+ uint32_t addr;
+ int size;
+ int size_written;
+ uint32_t write_requested;
+ int subblocks_sent;
+ int block_number;
+};
+
+/* Function Definitions */
+
+bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
+
#endif /* SOCFPGA_SIP_SVC_H */
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index d066f27..aec94af 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,188 +11,324 @@
#include "socfpga_mailbox.h"
#include "socfpga_sip_svc.h"
-static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args,
- int len)
+
+static bool is_mailbox_cmdbuf_full(uint32_t cin)
{
- uint32_t cmd_free_offset;
- int i;
+ uint32_t cout = mmio_read_32(MBOX_OFFSET + MBOX_COUT);
- cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN);
-
- mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER + (cmd_free_offset++ * 4),
- header_cmd);
-
-
- for (i = 0; i < len; i++) {
- cmd_free_offset %= MBOX_CMD_BUFFER_SIZE;
- mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER +
- (cmd_free_offset++ * 4), args[i]);
- }
-
- cmd_free_offset %= MBOX_CMD_BUFFER_SIZE;
- mmio_write_32(MBOX_OFFSET + MBOX_CIN, cmd_free_offset);
-
- return 0;
+ return (((cin + 1U) % MBOX_CMD_BUFFER_SIZE) == cout);
}
-int mailbox_read_response(int job_id, uint32_t *response, int resp_len)
+static bool is_mailbox_cmdbuf_empty(uint32_t cin)
{
- int rin = 0;
- int rout = 0;
- int response_length = 0;
- int resp = 0;
- int total_resp_len = 0;
+ uint32_t cout = mmio_read_32(MBOX_OFFSET + MBOX_COUT);
- if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM))
- mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0);
+ return (((cout + 1U) % MBOX_CMD_BUFFER_SIZE) == cin);
+}
+
+static int wait_for_mailbox_cmdbuf_empty(uint32_t cin)
+{
+ unsigned int timeout = 200U;
+
+ do {
+ if (is_mailbox_cmdbuf_empty(cin)) {
+ break;
+ }
+ mdelay(10U);
+ } while (--timeout != 0U);
+
+ if (timeout == 0U) {
+ return MBOX_TIMEOUT;
+ }
+
+ return MBOX_RET_OK;
+}
+
+static int write_mailbox_cmd_buffer(uint32_t *cin, uint32_t cout,
+ uint32_t data,
+ bool *is_doorbell_triggered)
+{
+ unsigned int timeout = 100U;
+
+ do {
+ if (is_mailbox_cmdbuf_full(*cin)) {
+ if (!(*is_doorbell_triggered)) {
+ mmio_write_32(MBOX_OFFSET +
+ MBOX_DOORBELL_TO_SDM, 1U);
+ *is_doorbell_triggered = true;
+ }
+ mdelay(10U);
+ } else {
+ mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER +
+ (*cin * 4), data);
+ (*cin)++;
+ *cin %= MBOX_CMD_BUFFER_SIZE;
+ mmio_write_32(MBOX_OFFSET + MBOX_CIN, *cin);
+ break;
+ }
+ } while (--timeout != 0U);
+
+ if (timeout == 0U) {
+ return MBOX_TIMEOUT;
+ }
+
+ if (*is_doorbell_triggered) {
+ int ret = wait_for_mailbox_cmdbuf_empty(*cin);
+ return ret;
+ }
+
+ return MBOX_RET_OK;
+}
+
+static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args,
+ unsigned int len)
+{
+ uint32_t sdm_read_offset, cmd_free_offset;
+ unsigned int i;
+ int ret;
+ bool is_doorbell_triggered = false;
+
+ cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN);
+ sdm_read_offset = mmio_read_32(MBOX_OFFSET + MBOX_COUT);
+
+ ret = write_mailbox_cmd_buffer(&cmd_free_offset, sdm_read_offset,
+ header_cmd, &is_doorbell_triggered);
+ if (ret != 0) {
+ goto restart_mailbox;
+ }
+
+ for (i = 0U; i < len; i++) {
+ is_doorbell_triggered = false;
+ ret = write_mailbox_cmd_buffer(&cmd_free_offset,
+ sdm_read_offset, args[i],
+ &is_doorbell_triggered);
+ if (ret != 0) {
+ goto restart_mailbox;
+ }
+ }
+
+ if (!is_doorbell_triggered) {
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
+ }
+
+ return MBOX_RET_OK;
+
+restart_mailbox:
+ /*
+ * Attempt to restart mailbox if the driver not able to write
+ * into mailbox command buffer
+ */
+ if (MBOX_CMD_MASK(header_cmd) != MBOX_CMD_RESTART) {
+ INFO("Mailbox timed out: Attempting mailbox reset\n");
+ ret = mailbox_init();
+
+ if (ret == MBOX_TIMEOUT) {
+ INFO("Error: Mailbox fail to restart\n");
+ }
+ }
+
+ return MBOX_TIMEOUT;
+}
+
+int mailbox_read_response(unsigned int *job_id, uint32_t *response,
+ unsigned int resp_len)
+{
+ uint32_t rin;
+ uint32_t rout;
+ uint32_t resp_data;
+ unsigned int ret_resp_len;
+
+ if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) == 1U) {
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
+ }
rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
if (rout != rin) {
- resp = mmio_read_32(MBOX_OFFSET +
- MBOX_RESP_BUFFER + ((rout++)*4));
+ resp_data = mmio_read_32(MBOX_OFFSET +
+ MBOX_RESP_BUFFER + ((rout++)*4U));
rout %= MBOX_RESP_BUFFER_SIZE;
mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
- if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID ||
- MBOX_RESP_JOB_ID(resp) != job_id) {
+
+ if (MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID) {
return MBOX_WRONG_ID;
}
- if (MBOX_RESP_ERR(resp) > 0) {
- INFO("Error in response: %x\n", resp);
- return -resp;
- }
- response_length = MBOX_RESP_LEN(resp);
+ *job_id = MBOX_RESP_JOB_ID(resp_data);
- while (response_length) {
+ ret_resp_len = MBOX_RESP_LEN(resp_data);
- response_length--;
- resp = mmio_read_32(MBOX_OFFSET +
- MBOX_RESP_BUFFER +
- (rout)*4);
- if (response && resp_len) {
- *(response + total_resp_len) = resp;
- resp_len--;
- total_resp_len++;
- }
- rout++;
- rout %= MBOX_RESP_BUFFER_SIZE;
- mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
+ if (ret_resp_len != 0U) {
+ ret_resp_len = iterate_resp(ret_resp_len, response,
+ resp_len);
}
- return total_resp_len;
+
+ if (MBOX_RESP_ERR(resp_data) > 0U) {
+ INFO("Error in response: %x\n", resp_data);
+ return -MBOX_RESP_ERR(resp_data);
+ }
+
+ return ret_resp_len;
}
-
return MBOX_NO_RESPONSE;
}
-int mailbox_poll_response(int job_id, int urgent, uint32_t *response,
- int resp_len)
+int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response,
+ unsigned int resp_len)
{
- int timeout = 0xFFFFFF;
- int rin = 0;
- int rout = 0;
- int response_length = 0;
- int resp = 0;
- int total_resp_len = 0;
+ unsigned int timeout = 40U;
+ unsigned int sdm_loop = 255U;
+ unsigned int ret_resp_len;
+ uint32_t rin;
+ uint32_t rout;
+ uint32_t resp_data;
- while (1) {
+ while (sdm_loop != 0U) {
- while (timeout > 0 &&
- !(mmio_read_32(MBOX_OFFSET +
- MBOX_DOORBELL_FROM_SDM) & 1)) {
- timeout--;
+ do {
+ if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)
+ == 1U) {
+ break;
+ }
+ mdelay(10U);
+ } while (--timeout != 0U);
+
+ if (timeout == 0U) {
+ break;
}
- if (!timeout) {
- INFO("Timed out waiting for SDM");
- return MBOX_TIMEOUT;
- }
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
- mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0);
-
- if (urgent & 1) {
- mdelay(5);
+ if ((urgent & 1U) != 0U) {
+ mdelay(5U);
if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) &
MBOX_STATUS_UA_MASK) ^
(urgent & MBOX_STATUS_UA_MASK)) {
- mmio_write_32(MBOX_OFFSET + MBOX_URG, 0);
- return 0;
+ mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
+ return MBOX_RET_OK;
}
- mmio_write_32(MBOX_OFFSET + MBOX_URG, 0);
+ mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
INFO("Error: Mailbox did not get UA");
- return -1;
+ return MBOX_RET_ERROR;
}
rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
while (rout != rin) {
- resp = mmio_read_32(MBOX_OFFSET +
- MBOX_RESP_BUFFER + ((rout++)*4));
+ resp_data = mmio_read_32(MBOX_OFFSET +
+ MBOX_RESP_BUFFER + ((rout++)*4U));
rout %= MBOX_RESP_BUFFER_SIZE;
mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
- if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID ||
- MBOX_RESP_JOB_ID(resp) != job_id)
+ if (MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID
+ || MBOX_RESP_JOB_ID(resp_data) != job_id) {
continue;
-
- if (MBOX_RESP_ERR(resp) > 0) {
- INFO("Error in response: %x\n", resp);
- return -MBOX_RESP_ERR(resp);
}
- response_length = MBOX_RESP_LEN(resp);
- while (response_length) {
- response_length--;
- resp = mmio_read_32(MBOX_OFFSET +
- MBOX_RESP_BUFFER +
- (rout)*4);
- if (response && resp_len) {
- *(response + total_resp_len) = resp;
- resp_len--;
- total_resp_len++;
- }
- rout++;
- rout %= MBOX_RESP_BUFFER_SIZE;
- mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
+ ret_resp_len = MBOX_RESP_LEN(resp_data);
+
+ if (ret_resp_len != 0U) {
+ ret_resp_len = iterate_resp(ret_resp_len,
+ response,
+ resp_len);
}
- return total_resp_len;
+
+ if (MBOX_RESP_ERR(resp_data) > 0U) {
+ INFO("Error in response: %x\n", resp_data);
+ return -MBOX_RESP_ERR(resp_data);
+ }
+
+ return ret_resp_len;
+ }
+
+ sdm_loop--;
+ }
+
+ INFO("Timed out waiting for SDM\n");
+ return MBOX_TIMEOUT;
+}
+
+unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
+ unsigned int resp_len)
+{
+ unsigned int timeout, total_resp_len = 0U;
+ uint32_t resp_data;
+ uint32_t rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+ uint32_t rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
+
+ while (mbox_resp_len > 0U) {
+ timeout = 100U;
+ mbox_resp_len--;
+ resp_data = mmio_read_32(MBOX_OFFSET +
+ MBOX_RESP_BUFFER +
+ (rout)*4U);
+
+ if ((resp_buf != NULL) && (resp_len != 0U)) {
+ *(resp_buf + total_resp_len)
+ = resp_data;
+ resp_len--;
+ total_resp_len++;
+ }
+ rout++;
+ rout %= MBOX_RESP_BUFFER_SIZE;
+ mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
+
+ do {
+ rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+ if (rout == rin) {
+ mdelay(10U);
+ } else {
+ break;
+ }
+ timeout--;
+ } while ((mbox_resp_len > 0U) && (timeout != 0U));
+
+ if (timeout == 0U) {
+ INFO("Timed out waiting for SDM\n");
+ return MBOX_TIMEOUT;
}
}
+ return total_resp_len;
}
-int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
- int len, int urgent)
+int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args,
+ unsigned int len, unsigned int indirect)
{
- if (urgent)
- mmio_write_32(MBOX_OFFSET + MBOX_URG, 1);
+ int status;
- fill_mailbox_circular_buffer(MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) |
- MBOX_JOB_ID_CMD(job_id) |
- MBOX_CMD_LEN_CMD(len) |
- MBOX_INDIRECT |
- cmd, args, len);
+ status = fill_mailbox_circular_buffer(
+ MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) |
+ MBOX_JOB_ID_CMD(*job_id) |
+ MBOX_CMD_LEN_CMD(len) |
+ MBOX_INDIRECT(indirect) |
+ cmd, args, len);
+ if (status < 0) {
+ return status;
+ }
- mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1);
+ *job_id = (*job_id + 1U) % MBOX_MAX_IND_JOB_ID;
- return 0;
+ return MBOX_RET_OK;
}
-int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
- int len, int urgent, uint32_t *response, int resp_len)
+int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args,
+ unsigned int len, uint32_t urgent, uint32_t *response,
+ unsigned int resp_len)
{
int status = 0;
- if (urgent) {
+ if (urgent != 0U) {
urgent |= mmio_read_32(MBOX_OFFSET + MBOX_STATUS) &
MBOX_STATUS_UA_MASK;
mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd);
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
}
else {
@@ -203,10 +339,10 @@
cmd, args, len);
}
- if (status)
+ if (status != 0) {
return status;
+ }
- mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1);
status = mailbox_poll_response(job_id, urgent, response, resp_len);
return status;
@@ -218,7 +354,7 @@
mmio_read_32(MBOX_OFFSET + MBOX_RIN));
}
-void mailbox_set_int(int interrupt)
+void mailbox_set_int(uint32_t interrupt)
{
mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) |
@@ -229,48 +365,45 @@
void mailbox_set_qspi_open(void)
{
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
- mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, 0, 0, 0, NULL, 0);
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_OPEN, NULL, 0U,
+ CMD_CASUAL, NULL, 0U);
}
void mailbox_set_qspi_direct(void)
{
- mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0, NULL, 0);
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, NULL, 0U,
+ CMD_CASUAL, NULL, 0U);
}
void mailbox_set_qspi_close(void)
{
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
- mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, 0, 0, 0, NULL, 0);
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_CLOSE, NULL, 0U,
+ CMD_CASUAL, NULL, 0U);
}
-int mailbox_get_qspi_clock(void)
+void mailbox_qspi_set_cs(uint32_t device_select)
{
- mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
- return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_DIRECT, 0, 0, 0,
- NULL, 0);
-}
-
-void mailbox_qspi_set_cs(int device_select)
-{
- uint32_t cs_setting = device_select;
+ uint32_t cs_setting;
/* QSPI device select settings at 31:28 */
- cs_setting = (cs_setting << 28);
+ cs_setting = (device_select << 28);
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_QSPI_SET_CS, &cs_setting,
- 1, 0, NULL, 0);
+ 1U, CMD_CASUAL, NULL, 0U);
}
void mailbox_reset_cold(void)
{
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
- mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, NULL, 0);
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, NULL, 0U,
+ CMD_CASUAL, NULL, 0U);
}
-int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len)
+int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, unsigned int resp_buf_len)
{
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_SUBPARTITION_TABLE,
- NULL, 0, 0, (uint32_t *)resp_buf,
+ NULL, 0U, CMD_CASUAL, resp_buf,
resp_buf_len);
}
@@ -284,22 +417,26 @@
uint32_t retry_counter;
};
-int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len)
+int mailbox_rsu_status(uint32_t *resp_buf, unsigned int resp_buf_len)
{
int ret;
struct rsu_status_info *info = (struct rsu_status_info *)resp_buf;
- info->retry_counter = ~0;
+ info->retry_counter = ~0U;
- ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0, 0,
- (uint32_t *)resp_buf, resp_buf_len);
+ ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0U,
+ CMD_CASUAL, resp_buf,
+ resp_buf_len);
- if (ret < 0)
+ if (ret < 0) {
return ret;
+ }
- if (info->retry_counter != ~0)
- if (!(info->version & RSU_VERSION_ACMF_MASK))
+ if (info->retry_counter != ~0U) {
+ if ((info->version & RSU_VERSION_ACMF_MASK) == 0U) {
info->version |= RSU_VERSION_ACMF;
+ }
+ }
return ret;
}
@@ -307,33 +444,37 @@
int mailbox_rsu_update(uint32_t *flash_offset)
{
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE,
- flash_offset, 2, 0, NULL, 0);
+ flash_offset, 2U,
+ CMD_CASUAL, NULL, 0U);
}
int mailbox_hps_stage_notify(uint32_t execution_stage)
{
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY,
- &execution_stage, 1, 0, NULL, 0);
+ &execution_stage, 1U, CMD_CASUAL,
+ NULL, 0U);
}
int mailbox_init(void)
{
- int status = 0;
+ int status;
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE |
MBOX_INT_FLAG_UAE);
- mmio_write_32(MBOX_OFFSET + MBOX_URG, 0);
- mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0);
+ mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
- status = mailbox_send_cmd(0, MBOX_CMD_RESTART, 0, 0, 1, NULL, 0);
+ status = mailbox_send_cmd(0U, MBOX_CMD_RESTART, NULL, 0U,
+ CMD_URGENT, NULL, 0U);
- if (status)
+ if (status != 0) {
return status;
+ }
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE |
MBOX_INT_FLAG_UAE);
- return 0;
+ return MBOX_RET_OK;
}
int intel_mailbox_get_config_status(uint32_t cmd)
@@ -341,27 +482,32 @@
int status;
uint32_t res, response[6];
- status = mailbox_send_cmd(1, cmd, NULL, 0, 0, response,
- sizeof(response) / sizeof(response[0]));
+ status = mailbox_send_cmd(MBOX_JOB_ID, cmd, NULL, 0U, CMD_CASUAL,
+ response, ARRAY_SIZE(response));
- if (status < 0)
+ if (status < 0) {
return status;
+ }
res = response[RECONFIG_STATUS_STATE];
- if (res && res != MBOX_CFGSTAT_STATE_CONFIG)
+ if ((res != 0U) && (res != MBOX_CFGSTAT_STATE_CONFIG)) {
return res;
+ }
res = response[RECONFIG_STATUS_PIN_STATUS];
- if (!(res & PIN_STATUS_NSTATUS))
+ if ((res & PIN_STATUS_NSTATUS) == 0U) {
return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+ }
res = response[RECONFIG_STATUS_SOFTFUNC_STATUS];
- if (res & SOFTFUNC_STATUS_SEU_ERROR)
+ if ((res & SOFTFUNC_STATUS_SEU_ERROR) != 0U) {
return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
+ }
- if ((res & SOFTFUNC_STATUS_CONF_DONE) &&
- (res & SOFTFUNC_STATUS_INIT_DONE))
- return 0;
+ if ((res & SOFTFUNC_STATUS_CONF_DONE) != 0U &&
+ (res & SOFTFUNC_STATUS_INIT_DONE) != 0U) {
+ return MBOX_RET_OK;
+ }
return MBOX_CFGSTAT_STATE_CONFIG;
}
@@ -370,8 +516,9 @@
{
int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
- if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
+ if ((ret != MBOX_RET_OK) && (ret != MBOX_CFGSTAT_STATE_CONFIG)) {
ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
+ }
return ret;
}
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index a20baab..86a4455 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,30 +14,15 @@
#include "socfpga_reset_manager.h"
#include "socfpga_sip_svc.h"
-/* Number of SiP Calls implemented */
-#define SIP_NUM_CALLS 0x3
/* Total buffer the driver can hold */
#define FPGA_CONFIG_BUFFER_SIZE 4
-static int current_block;
-static int read_block;
-static int current_buffer;
-static int send_id;
-static int rcv_id;
-static int max_blocks;
-static uint32_t bytes_per_block;
-static uint32_t blocks_submitted;
-static int is_partial_reconfig;
+static int current_block, current_buffer;
+static int read_block, max_blocks, is_partial_reconfig;
+static uint32_t send_id, rcv_id;
+static uint32_t bytes_per_block, blocks_submitted;
-struct fpga_config_info {
- uint32_t addr;
- int size;
- int size_written;
- uint32_t write_requested;
- int subblocks_sent;
- int block_number;
-};
/* SiP Service UUID */
DEFINE_SVC_UUID2(intl_svc_uid,
@@ -74,10 +59,8 @@
args[2] = bytes_per_block;
buffer->size_written += args[2];
- mailbox_send_cmd_async(
- send_id++ % MBOX_MAX_JOB_ID,
- MBOX_RECONFIG_DATA,
- args, 3, 0);
+ mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
+ 3U, CMD_INDIRECT);
buffer->subblocks_sent++;
max_blocks--;
@@ -143,7 +126,7 @@
}
static int intel_fpga_config_completed_write(uint32_t *completed_addr,
- uint32_t *count)
+ uint32_t *count, uint32_t *job_id)
{
uint32_t status = INTEL_SIP_SMC_STATUS_OK;
*count = 0;
@@ -153,14 +136,13 @@
while (*count < 3) {
- resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID,
- resp, sizeof(resp) / sizeof(resp[0]));
+ resp_len = mailbox_read_response(job_id,
+ resp, ARRAY_SIZE(resp));
if (resp_len < 0)
break;
max_blocks++;
- rcv_id++;
if (mark_last_buffer_xfer_completed(
&completed_addr[*count]) == 0)
@@ -208,10 +190,10 @@
mailbox_clear_response();
- mailbox_send_cmd(1, MBOX_CMD_CANCEL, 0, 0, 0, NULL, 0);
+ mailbox_send_cmd(1U, MBOX_CMD_CANCEL, NULL, 0U, CMD_CASUAL, NULL, 0U);
- status = mailbox_send_cmd(1, MBOX_RECONFIG, 0, 0, 0,
- response, sizeof(response) / sizeof(response[0]));
+ status = mailbox_send_cmd(1U, MBOX_RECONFIG, NULL, 0U, CMD_CASUAL,
+ response, ARRAY_SIZE(response));
if (status < 0)
return status;
@@ -232,8 +214,6 @@
current_block = 0;
read_block = 0;
current_buffer = 0;
- send_id = 0;
- rcv_id = 0;
/* full reconfiguration */
if (!is_partial_reconfig) {
@@ -252,7 +232,7 @@
return true;
}
-static bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
+bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
{
if (size > (UINT64_MAX - addr))
return false;
@@ -371,7 +351,7 @@
/* Intel Remote System Update (RSU) services */
uint64_t intel_rsu_update_address;
-static uint32_t intel_rsu_status(uint64_t *respbuf, uint32_t respbuf_sz)
+static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
{
if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
return INTEL_SIP_SMC_RSU_ERROR;
@@ -404,9 +384,9 @@
}
/* Mailbox services */
-static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, int len,
- int urgent, uint32_t *response,
- int resp_len, int *mbox_status,
+static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, uint32_t len,
+ uint32_t urgent, uint32_t *response,
+ uint32_t resp_len, int *mbox_status,
int *len_in_resp)
{
*len_in_resp = 0;
@@ -441,14 +421,14 @@
void *handle,
u_register_t flags)
{
- uint32_t val = 0;
+ uint32_t retval = 0;
uint32_t status = INTEL_SIP_SMC_STATUS_OK;
uint32_t completed_addr[3];
uint64_t rsu_respbuf[9];
- uint32_t count = 0;
u_register_t x5, x6;
int mbox_status, len_in_resp;
+
switch (smc_fid) {
case SIP_SVC_UID:
/* Return UID to the caller */
@@ -474,8 +454,8 @@
case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
status = intel_fpga_config_completed_write(completed_addr,
- &count);
- switch (count) {
+ &retval, &rcv_id);
+ switch (retval) {
case 1:
SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
completed_addr[0], 0, 0);
@@ -500,17 +480,17 @@
}
case INTEL_SIP_SMC_REG_READ:
- status = intel_secure_reg_read(x1, &val);
- SMC_RET3(handle, status, val, x1);
+ status = intel_secure_reg_read(x1, &retval);
+ SMC_RET3(handle, status, retval, x1);
case INTEL_SIP_SMC_REG_WRITE:
- status = intel_secure_reg_write(x1, (uint32_t)x2, &val);
- SMC_RET3(handle, status, val, x1);
+ status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
+ SMC_RET3(handle, status, retval, x1);
case INTEL_SIP_SMC_REG_UPDATE:
status = intel_secure_reg_update(x1, (uint32_t)x2,
- (uint32_t)x3, &val);
- SMC_RET3(handle, status, val, x1);
+ (uint32_t)x3, &retval);
+ SMC_RET3(handle, status, retval, x1);
case INTEL_SIP_SMC_RSU_STATUS:
status = intel_rsu_status(rsu_respbuf,
@@ -532,11 +512,11 @@
case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
- ARRAY_SIZE(rsu_respbuf), &val);
+ ARRAY_SIZE(rsu_respbuf), &retval);
if (status) {
SMC_RET1(handle, status);
} else {
- SMC_RET2(handle, status, val);
+ SMC_RET2(handle, status, retval);
}
case INTEL_SIP_SMC_MBOX_SEND_CMD:
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index 5813c8f..128a808 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,6 +47,8 @@
{
static console_t console;
+ mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
+
console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
&console);
/*
@@ -107,6 +109,8 @@
******************************************************************************/
void bl31_platform_setup(void)
{
+ socfpga_delay_timer_init();
+
/* Initialize the gic cpu and distributor interfaces */
gicv2_driver_init(&plat_gicv2_gic_data);
gicv2_distif_init();
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 3bd6af9..8bbd010 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -25,7 +25,8 @@
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
- plat/intel/soc/common/aarch64/plat_helpers.S
+ plat/intel/soc/common/aarch64/plat_helpers.S \
+ plat/intel/soc/common/socfpga_delay_timer.c
BL2_SOURCES += \
common/desc_image_load.c \
@@ -43,7 +44,6 @@
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
- plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_emac.c \
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index ace74a8..74cf78a 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2018 Marvell International Ltd.
+# Copyright (C) 2018-2021 Marvell International Ltd.
#
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
@@ -18,59 +18,6 @@
include plat/marvell/marvell.mk
#*********** A3700 *************
-DOIMAGEPATH := $(WTP)
-DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/linux/tbb_linux
-
-ifeq ($(MARVELL_SECURE_BOOT),1)
-DOIMAGE_CFG := $(DOIMAGEPATH)/atf-tim.txt
-IMAGESPATH := $(DOIMAGEPATH)/tim/trusted
-
-TIMNCFG := $(DOIMAGEPATH)/atf-timN.txt
-TIMNSIG := $(IMAGESPATH)/timnsign.txt
-TIM2IMGARGS := -i $(DOIMAGE_CFG) -n $(TIMNCFG)
-TIMN_IMAGE := $$(grep "Image Filename:" -m 1 $(TIMNCFG) | cut -c 17-)
-else #MARVELL_SECURE_BOOT
-DOIMAGE_CFG := $(DOIMAGEPATH)/atf-ntim.txt
-IMAGESPATH := $(DOIMAGEPATH)/tim/untrusted
-TIM2IMGARGS := -i $(DOIMAGE_CFG)
-endif #MARVELL_SECURE_BOOT
-
-TIMBUILD := $(DOIMAGEPATH)/script/buildtim.sh
-TIM2IMG := $(DOIMAGEPATH)/script/tim2img.pl
-
-# WTMI_IMG is used to specify the customized RTOS image running over
-# Service CPU (CM3 processor). By the default, it points to a
-# baremetal binary of fuse programming in A3700_utils.
-WTMI_IMG := $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin
-
-# WTMI_SYSINIT_IMG is used for the system early initialization,
-# such as AVS settings, clock-tree setup and dynamic DDR PHY training.
-# After the initialization is done, this image will be wiped out
-# from the memory and CM3 will continue with RTOS image or other application.
-WTMI_SYSINIT_IMG := $(DOIMAGEPATH)/wtmi/sys_init/build/sys_init.bin
-
-# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG)
-# and sys-init image (WTMI_SYSINIT_IMG).
-WTMI_MULTI_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi.bin
-
-WTMI_ENC_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi-enc.bin
-BUILD_UART := uart-images
-
-SRCPATH := $(dir $(BL33))
-
-CLOCKSPRESET ?= CPU_800_DDR_800
-
-DDR_TOPOLOGY ?= 0
-
-BOOTDEV ?= SPINOR
-PARTNUM ?= 0
-
-TIM_IMAGE := $$(grep "Image Filename:" -m 1 $(DOIMAGE_CFG) | cut -c 17-)
-TIMBLDARGS := $(MARVELL_SECURE_BOOT) $(BOOTDEV) $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
- $(DDR_TOPOLOGY) $(PARTNUM) $(DEBUG) $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 1
-TIMBLDUARTARGS := $(MARVELL_SECURE_BOOT) UART $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
- $(DDR_TOPOLOGY) 0 0 $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 0
-DOIMAGE_FLAGS := -r $(DOIMAGE_CFG) -v -D
# GICV3
$(eval $(call add_define,CONFIG_GICV3))
@@ -91,7 +38,6 @@
-I$/drivers/arm/gic/common/
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
- $(MARVELL_COMMON_BASE)/marvell_cci.c \
$(MARVELL_DRV_BASE)/uart/a3700_console.S
BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
@@ -103,12 +49,14 @@
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
+ $(PLAT_COMMON_BASE)/plat_cci.c \
$(PLAT_COMMON_BASE)/plat_pm.c \
$(PLAT_COMMON_BASE)/dram_win.c \
$(PLAT_COMMON_BASE)/io_addr_dec.c \
$(PLAT_COMMON_BASE)/marvell_plat_config.c \
$(PLAT_COMMON_BASE)/a3700_ea.c \
$(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \
+ $(MARVELL_COMMON_BASE)/marvell_cci.c \
$(MARVELL_COMMON_BASE)/marvell_ddr_info.c \
$(MARVELL_COMMON_BASE)/marvell_gicv3.c \
$(MARVELL_GIC_SOURCES) \
@@ -117,11 +65,83 @@
$(PLAT_COMMON_BASE)/a3700_sip_svc.c \
$(MARVELL_DRV)
-mrvl_flash: ${BUILD_PLAT}/${FIP_NAME} ${DOIMAGETOOL}
- $(shell truncate -s %128K ${BUILD_PLAT}/bl1.bin)
- $(shell cat ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/${FIP_NAME} > ${BUILD_PLAT}/${BOOT_IMAGE})
- $(shell truncate -s %4 ${BUILD_PLAT}/${BOOT_IMAGE})
- $(shell truncate -s %4 $(WTMI_IMG))
+ifeq ($(CM3_SYSTEM_RESET),1)
+BL31_SOURCES += $(PLAT_COMMON_BASE)/cm3_system_reset.c
+endif
+
+ifdef WTP
+
+DOIMAGEPATH := $(WTP)
+DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/src/TBB_Linux/release/TBB_linux
+
+ifeq ($(MARVELL_SECURE_BOOT),1)
+DOIMAGE_CFG := $(DOIMAGEPATH)/atf-tim.txt
+IMAGESPATH := $(DOIMAGEPATH)/tim/trusted
+
+TIMNCFG := $(DOIMAGEPATH)/atf-timN.txt
+TIMNSIG := $(IMAGESPATH)/timnsign.txt
+TIM2IMGARGS := -i $(DOIMAGE_CFG) -n $(TIMNCFG)
+TIMN_IMAGE := $$(grep "Image Filename:" -m 1 $(TIMNCFG) | cut -c 17-)
+else #MARVELL_SECURE_BOOT
+DOIMAGE_CFG := $(DOIMAGEPATH)/atf-ntim.txt
+IMAGESPATH := $(DOIMAGEPATH)/tim/untrusted
+TIM2IMGARGS := -i $(DOIMAGE_CFG)
+endif #MARVELL_SECURE_BOOT
+
+TIMBUILD := $(DOIMAGEPATH)/script/buildtim.sh
+TIM2IMG := $(DOIMAGEPATH)/script/tim2img.pl
+TIMDDRTOOL := $(DOIMAGEPATH)/tim/ddr/ddr_tool
+
+$(TIMBUILD): $(TIMDDRTOOL)
+
+# WTMI_IMG is used to specify the customized RTOS image running over
+# Service CPU (CM3 processor). By the default, it points to a
+# baremetal binary of fuse programming in A3700_utils.
+WTMI_IMG := $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin
+
+# WTMI_SYSINIT_IMG is used for the system early initialization,
+# such as AVS settings, clock-tree setup and dynamic DDR PHY training.
+# After the initialization is done, this image will be wiped out
+# from the memory and CM3 will continue with RTOS image or other application.
+WTMI_SYSINIT_IMG := $(DOIMAGEPATH)/wtmi/sys_init/build/sys_init.bin
+
+# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG)
+# and sys-init image (WTMI_SYSINIT_IMG).
+WTMI_MULTI_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi.bin
+
+WTMI_ENC_IMG := $(BUILD_PLAT)/wtmi-enc.bin
+BUILD_UART := uart-images
+
+SRCPATH := $(dir $(BL33))
+
+CLOCKSPRESET ?= CPU_800_DDR_800
+
+DDR_TOPOLOGY ?= 0
+
+BOOTDEV ?= SPINOR
+PARTNUM ?= 0
+
+TIM_IMAGE := $$(grep "Image Filename:" -m 1 $(DOIMAGE_CFG) | cut -c 17-)
+TIMBLDARGS := $(MARVELL_SECURE_BOOT) $(BOOTDEV) $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
+ $(DDR_TOPOLOGY) $(PARTNUM) $(DEBUG) $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 1
+TIMBLDUARTARGS := $(MARVELL_SECURE_BOOT) UART $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
+ $(DDR_TOPOLOGY) 0 0 $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 0
+DOIMAGE_FLAGS := -r $(DOIMAGE_CFG) -v -D
+
+$(DOIMAGETOOL): FORCE
+ $(if $(value CRYPTOPP_PATH),,$(error "Platform '${PLAT}' for WTP image tool requires CRYPTOPP_PATH. Please set CRYPTOPP_PATH to point to the right directory"))
+ $(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile
+ $(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_PATH)
+
+$(WTMI_MULTI_IMG): FORCE
+ $(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) WTMI_IMG=$(WTMI_IMG) WTMI
+
+$(TIMDDRTOOL): FORCE
+ $(if $(value MV_DDR_PATH),,$(error "Platform '${PLAT}' for ddr tool requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
+ $(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) MV_DDR_PATH=$(MV_DDR_PATH) mv_ddr
+
+.PHONY: mrvl_flash
+mrvl_flash: ${BUILD_PLAT}/${BOOT_IMAGE} ${WTMI_MULTI_IMG} ${DOIMAGETOOL} ${TIMBUILD}
@echo
@echo "Building uart images"
$(TIMBUILD) $(TIMBLDUARTARGS)
@@ -150,8 +170,9 @@
@echo -e "\n\t=======================================================\n";
@echo -e "\t Secure boot. Encrypting wtmi and boot-image \n";
@echo -e "\t=======================================================\n";
- @truncate -s %16 $(WTMI_MULTI_IMG)
- @openssl enc -aes-256-cbc -e -in $(WTMI_MULTI_IMG) \
+ @cp $(WTMI_MULTI_IMG) $(BUILD_PLAT)/wtmi-align.bin
+ @truncate -s %16 $(BUILD_PLAT)/wtmi-align.bin
+ @openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/wtmi-align.bin \
-out $(WTMI_ENC_IMG) \
-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
-iv `cat $(IMAGESPATH)/iv.txt` -p
@@ -163,8 +184,34 @@
endif
$(DOIMAGETOOL) $(DOIMAGE_FLAGS)
@if [ -e "$(TIMNCFG)" ]; then $(DOIMAGETOOL) -r $(TIMNCFG); fi
- @if [ "$(MARVELL_SECURE_BOOT)" = "1" ]; then sed -i 's|$(WTMI_MULTI_IMG)|$(WTMI_ENC_IMG)|1;s|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1;' $(TIMNCFG); fi
+ifeq ($(MARVELL_SECURE_BOOT),1)
+ @sed -i 's|$(WTMI_MULTI_IMG)|$(WTMI_ENC_IMG)|1;s|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1;' $(TIMNCFG)
+endif
$(TIM2IMG) $(TIM2IMGARGS) -o $(BUILD_PLAT)/$(FLASH_IMAGE)
- @mv -t $(BUILD_PLAT) $(TIM_IMAGE) $(DOIMAGE_CFG) $(TIMN_IMAGE) $(TIMNCFG) $(WTMI_IMG) $(WTMI_SYSINIT_IMG) $(WTMI_MULTI_IMG)
- @if [ "$(MARVELL_SECURE_BOOT)" = "1" ]; then mv -t $(BUILD_PLAT) $(WTMI_ENC_IMG) OtpHash.txt; fi
+ @mv -t $(BUILD_PLAT) $(TIM_IMAGE) $(DOIMAGE_CFG) $(TIMN_IMAGE) $(TIMNCFG)
+ @cp -t $(BUILD_PLAT) $(WTMI_IMG) $(WTMI_SYSINIT_IMG) $(WTMI_MULTI_IMG)
+ifeq ($(MARVELL_SECURE_BOOT),1)
+ @mv -t $(BUILD_PLAT) OtpHash.txt
+endif
@find . -name "*.txt" | grep -E "CSK[[:alnum:]]_KeyHash.txt|Tim_msg.txt|TIMHash.txt" | xargs rm -f
+
+clean realclean distclean: mrvl_clean
+
+.PHONY: mrvl_clean
+mrvl_clean:
+ -$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) MV_DDR_PATH=$(MV_DDR_PATH) clean
+ -$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_PATH) clean
+ifdef CRYPTOPP_PATH
+ -$(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile clean
+endif
+
+else # WTP
+
+.PHONY: mrvl_flash
+mrvl_flash:
+ $(error "Platform '${PLAT}' for target '$@' requires WTP. Please set WTP to point to the right directory")
+
+endif # WTP
+
+.PHONY: FORCE
+FORCE:;
diff --git a/plat/marvell/armada/a3k/common/cm3_system_reset.c b/plat/marvell/armada/a3k/common/cm3_system_reset.c
new file mode 100644
index 0000000..548ff51
--- /dev/null
+++ b/plat/marvell/armada/a3k/common/cm3_system_reset.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2020 Marek Behun, CZ.NIC
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mvebu_def.h>
+
+/* Cortex-M3 Secure Processor Mailbox Registers */
+#define MVEBU_RWTM_PARAM0_REG (MVEBU_RWTM_REG_BASE)
+#define MVEBU_RWTM_CMD_REG (MVEBU_RWTM_REG_BASE + 0x40)
+#define MVEBU_RWTM_HOST_INT_RESET_REG (MVEBU_RWTM_REG_BASE + 0xC8)
+#define MVEBU_RWTM_HOST_INT_MASK_REG (MVEBU_RWTM_REG_BASE + 0xCC)
+#define MVEBU_RWTM_HOST_INT_SP_COMPLETE BIT(0)
+
+#define MVEBU_RWTM_REBOOT_CMD 0x0009
+#define MVEBU_RWTM_REBOOT_MAGIC 0xDEADBEEF
+
+static inline bool rwtm_completed(void)
+{
+ return (mmio_read_32(MVEBU_RWTM_HOST_INT_RESET_REG) &
+ MVEBU_RWTM_HOST_INT_SP_COMPLETE) != 0;
+}
+
+static bool rwtm_wait(int ms)
+{
+ while (ms && !rwtm_completed()) {
+ mdelay(1);
+ --ms;
+ }
+
+ return rwtm_completed();
+}
+
+void cm3_system_reset(void)
+{
+ int tries = 5;
+
+ for (; tries > 0; --tries) {
+ mmio_clrbits_32(MVEBU_RWTM_HOST_INT_RESET_REG,
+ MVEBU_RWTM_HOST_INT_SP_COMPLETE);
+
+ mmio_write_32(MVEBU_RWTM_PARAM0_REG, MVEBU_RWTM_REBOOT_MAGIC);
+ mmio_write_32(MVEBU_RWTM_CMD_REG, MVEBU_RWTM_REBOOT_CMD);
+
+ if (rwtm_wait(10)) {
+ break;
+ }
+
+ mdelay(100);
+ }
+
+ /* If we reach here, the command is not implemented. */
+ ERROR("System reset command not implemented in WTMI firmware!\n");
+}
diff --git a/plat/marvell/armada/a3k/common/dram_win.c b/plat/marvell/armada/a3k/common/dram_win.c
index 694f6d4..e89f295 100644
--- a/plat/marvell/armada/a3k/common/dram_win.c
+++ b/plat/marvell/armada/a3k/common/dram_win.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -92,33 +92,35 @@
},
/*
- * If total dram size is more than 2GB, now there is only one case - 4GB
- * dram; we will use below cpu windows configurations:
- * - Internal Regs, CCI-400, Boot Rom and PCIe windows are kept as
- * default;
- * - Use 4 CPU decode windows for DRAM, which cover 3.375GB DRAM;
- * DDR window 0 is configured in tim header with 2GB size, no need to
- * configure it again here;
+ * If total DRAM size is more than 2GB, now there is only one case:
+ * 4GB of DRAM; to better utilize address space (for maximization of
+ * DRAM usage), we will use the configuration of CPU windows below:
+ * - Internal Regs and Boot ROM windows are kept as default;
+ * - CCI-400 is moved from its default address to another address
+ * (this is actually done even if DRAM size is not more than 2 GB,
+ * because the firmware is compiled with that address as a
+ * constant);
+ * - PCIe window is moved to another address;
+ * - Use 4 CPU decode windows for DRAM, which cover 3.75GB DRAM;
+ * DDR window 0 is configured in tim header with 2G B size, no need
+ * to configure it again here;
*
- * 0xFFFFFFFF ---> |-----------------------|
- * | Boot ROM | 64KB
+ * 0xFFFFFFFF ---> +-----------------------+
+ * | Boot ROM | 64 KB
* 0xFFF00000 ---> +-----------------------+
* : :
- * 0xF0000000 ---> |-----------------------|
- * | PCIE | 128 MB
- * 0xE8000000 ---> |-----------------------|
- * | DDR window 3 | 128 MB
- * 0xE0000000 ---> +-----------------------+
+ * 0xFE010000 ---> +-----------------------+
+ * | CCI Regs | 64 KB
+ * 0xFE000000 ---> +-----------------------+
* : :
- * 0xD8010000 ---> |-----------------------|
- * | CCI Regs | 64 KB
- * 0xD8000000 ---> +-----------------------+
- * : :
- * : :
+ * 0xFA000000 ---> +-----------------------+
+ * | PCIE | 128 MB
+ * 0xF2000000 ---> +-----------------------+
+ * | DDR window 3 | 512 MB
* 0xD2000000 ---> +-----------------------+
- * | Internal Regs | 32MB
+ * | Internal Regs | 32 MB
* 0xD0000000 ---> |-----------------------|
- * | DDR window 2 | 256 MB
+ * | DDR window 2 | 256 MB
* 0xC0000000 ---> |-----------------------|
* | |
* | DDR window 1 | 1 GB
@@ -155,14 +157,14 @@
0xc0000000},
{CPU_WIN_ENABLED,
CPU_WIN_TARGET_DRAM,
- 0xe0000000,
- 0x08000000,
- 0xe0000000},
+ 0xd2000000,
+ 0x20000000,
+ 0xd2000000},
{CPU_WIN_ENABLED,
CPU_WIN_TARGET_PCIE,
- 0xe8000000,
+ 0xf2000000,
0x08000000,
- 0xe8000000},
+ 0xf2000000},
},
};
diff --git a/plat/marvell/armada/a3k/common/include/a3700_plat_def.h b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
index c7f40ad..83d9561 100644
--- a/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
+++ b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -41,8 +41,14 @@
#define MVEBU_GICR_BASE 0x1D40000
#define MVEBU_GICC_BASE 0x1D80000
-/* CCI-400 */
-#define MVEBU_CCI_BASE 0x8000000
+/*
+ * CCI-400 base address
+ * This address is absolute, not relative to MVEBU_REGS_BASE.
+ * This is not the default CCI base address (that would be 0xD8000000).
+ * Rather we remap CCI to this address to better utilize the address space.
+ * (The remapping is done in plat/marvell/armada/a3k/common/plat_cci.c)
+ */
+#define MVEBU_CCI_BASE 0xFE000000
/*****************************************************************************
* North and south bridge register base
@@ -119,4 +125,10 @@
*/
#define MVEBU_COMPHY_REG_BASE (MVEBU_REGS_BASE + 0x18300)
+/*****************************************************************************
+ * Cortex-M3 Secure Processor Mailbox constants
+ *****************************************************************************
+ */
+#define MVEBU_RWTM_REG_BASE (MVEBU_REGS_BASE + 0xB0000)
+
#endif /* A3700_PLAT_DEF_H */
diff --git a/plat/marvell/armada/a3k/common/include/a3700_pm.h b/plat/marvell/armada/a3k/common/include/a3700_pm.h
index cc6cf43..44dbb9f 100644
--- a/plat/marvell/armada/a3k/common/include/a3700_pm.h
+++ b/plat/marvell/armada/a3k/common/include/a3700_pm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2016 Marvell International Ltd.
+ * Copyright (C) 2016-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -48,4 +48,6 @@
struct pm_wake_up_src_config *mv_wake_up_src_config_get(void);
+void cm3_system_reset(void);
+
#endif /* A3700_PM_H */
diff --git a/plat/marvell/armada/a3k/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
index 3d839f8..057ee2e 100644
--- a/plat/marvell/armada/a3k/common/include/platform_def.h
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2016-2019 Marvell International Ltd.
+ * Copyright (C) 2016-2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -148,7 +148,7 @@
#define PLAT_MARVELL_SHARED_RAM_CACHED 1
/* CCI related constants */
-#define PLAT_MARVELL_CCI_BASE (MVEBU_REGS_BASE + MVEBU_CCI_BASE)
+#define PLAT_MARVELL_CCI_BASE MVEBU_CCI_BASE
#define PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX 3
#define PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX 4
@@ -227,6 +227,8 @@
#define CPU_DEC_RLR_REMAP_LOW_MASK \
(0xffff << CPU_DEC_BR_BASE_OFFS)
+#define CPU_DEC_CCI_BASE_REG (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
+
/* Securities */
#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
diff --git a/plat/marvell/armada/a3k/common/plat_cci.c b/plat/marvell/armada/a3k/common/plat_cci.c
new file mode 100644
index 0000000..56f091f
--- /dev/null
+++ b/plat/marvell/armada/a3k/common/plat_cci.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2021 Marek Behun <marek.behun@nic.cz>
+ *
+ * Based on plat/marvell/armada/common/marvell_cci.c
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <drivers/arm/cci.h>
+#include <lib/mmio.h>
+
+#include <plat_marvell.h>
+
+static const int cci_map[] = {
+ PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX,
+ PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX
+};
+
+/*
+ * This redefines the weak definition in
+ * plat/marvell/armada/common/marvell_cci.c
+ */
+void plat_marvell_interconnect_init(void)
+{
+ /*
+ * To better utilize the address space, we remap CCI base address from
+ * the default (0xD8000000) to MVEBU_CCI_BASE.
+ * This has to be done here, rather than in cpu_wins_init(), because
+ * cpu_wins_init() is called later.
+ */
+ mmio_write_32(CPU_DEC_CCI_BASE_REG, MVEBU_CCI_BASE >> 20);
+
+ cci_init(PLAT_MARVELL_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
+}
diff --git a/plat/marvell/armada/a3k/common/plat_pm.c b/plat/marvell/armada/a3k/common/plat_pm.c
index f8ce6fe..2bae37e 100644
--- a/plat/marvell/armada/a3k/common/plat_pm.c
+++ b/plat/marvell/armada/a3k/common/plat_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -763,6 +763,11 @@
panic();
}
+#pragma weak cm3_system_reset
+void cm3_system_reset(void)
+{
+}
+
/*****************************************************************************
* A3700 handlers to reset the system
*****************************************************************************
@@ -780,6 +785,9 @@
2 * sizeof(uint64_t));
#endif
+ /* Use Cortex-M3 secure coprocessor for system reset */
+ cm3_system_reset();
+
/* Trigger the warm reset */
mmio_write_32(MVEBU_WARM_RESET_REG, MVEBU_WARM_RESET_MAGIC);
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index 02f1553..cf1516a 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -4,8 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
-include tools/marvell/doimage/doimage.mk
-
PLAT_FAMILY := a8k
PLAT_INCLUDE_BASE := include/plat/marvell/armada/$(PLAT_FAMILY)
PLAT_COMMON_BASE := plat/marvell/armada/a8k/common
@@ -33,6 +31,36 @@
DOIMAGEPATH ?= tools/marvell/doimage
DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage
+include plat/marvell/marvell.mk
+include tools/marvell/doimage/doimage.mk
+
+ifeq (${MARVELL_SECURE_BOOT},1)
+DOIMAGE_SEC_FLAGS := -c $(DOIMAGE_SEC)
+DOIMAGE_LIBS_CHECK = \
+ if ! [ -d "/usr/include/mbedtls" ]; then \
+ echo "****************************************" >&2; \
+ echo "Missing mbedTLS installation! " >&2; \
+ echo "Please download it from \"tls.mbed.org\"" >&2; \
+ echo "Alternatively on Debian/Ubuntu system install" >&2; \
+ echo "\"libmbedtls-dev\" package" >&2; \
+ echo "Make sure to use version 2.1.0 or later" >&2; \
+ echo "****************************************" >&2; \
+ exit 1; \
+ else if ! [ -f "/usr/include/libconfig.h" ]; then \
+ echo "********************************************************" >&2; \
+ echo "Missing Libconfig installation!" >&2; \
+ echo "Please download it from \"www.hyperrealm.com/libconfig/\"" >&2; \
+ echo "Alternatively on Debian/Ubuntu system install packages" >&2; \
+ echo "\"libconfig8\" and \"libconfig8-dev\"" >&2; \
+ echo "********************************************************" >&2; \
+ exit 1; \
+ fi \
+ fi
+else #MARVELL_SECURE_BOOT
+DOIMAGE_LIBS_CHECK =
+DOIMAGE_SEC_FLAGS =
+endif #MARVELL_SECURE_BOOT
+
ROM_BIN_EXT ?= $(BUILD_PLAT)/ble.bin
DOIMAGE_FLAGS += -b $(ROM_BIN_EXT) $(NAND_DOIMAGE_FLAGS) $(DOIMAGE_SEC_FLAGS)
@@ -124,8 +152,20 @@
include ${BLE_PATH}/ble.mk
$(eval $(call MAKE_BL,e))
-mrvl_flash: ${BUILD_PLAT}/${FIP_NAME} ${DOIMAGETOOL} ${BUILD_PLAT}/ble.bin
- $(shell truncate -s %128K ${BUILD_PLAT}/bl1.bin)
- $(shell cat ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/${FIP_NAME} > ${BUILD_PLAT}/${BOOT_IMAGE})
+clean realclean distclean: mrvl_clean
+
+.PHONY: mrvl_clean
+mrvl_clean:
+ @echo " Doimage CLEAN"
+ ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${DOIMAGEPATH} clean
+
+${DOIMAGETOOL}: FORCE
+ @$(DOIMAGE_LIBS_CHECK)
+ ${Q}${MAKE} --no-print-directory -C ${DOIMAGEPATH}
+
+.PHONY: mrvl_flash
+mrvl_flash: ${BUILD_PLAT}/${BOOT_IMAGE} ${DOIMAGETOOL}
${DOIMAGETOOL} ${DOIMAGE_FLAGS} ${BUILD_PLAT}/${BOOT_IMAGE} ${BUILD_PLAT}/${FLASH_IMAGE}
+.PHONY: FORCE
+FORCE:;
diff --git a/plat/marvell/armada/common/marvell_common.mk b/plat/marvell/armada/common/marvell_common.mk
index 2e96e2f..e5ee710 100644
--- a/plat/marvell/armada/common/marvell_common.mk
+++ b/plat/marvell/armada/common/marvell_common.mk
@@ -7,7 +7,6 @@
MARVELL_PLAT_INCLUDE_BASE := include/plat/marvell/armada
include plat/marvell/version.mk
-include plat/marvell/marvell.mk
VERSION_STRING +=(Marvell-${SUBVERSION})
@@ -87,4 +86,13 @@
include $(MARVELL_PLAT_BASE)/common/mss/mss_common.mk
endif
-fip: mrvl_flash
+$(BUILD_PLAT)/$(BOOT_IMAGE): $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/$(FIP_NAME)
+ $(if $(shell find $(BUILD_PLAT)/bl1.bin -type f -size +128k),$(error "Image '$(BUILD_PLAT)/bl1.bin' is bigger than 128kB"))
+ @cp $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ @truncate -s %128K $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ @cat $(BUILD_PLAT)/$(FIP_NAME) >> $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ @truncate -s %4 $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ @echo "Built $@ successfully"
+
+.PHONY: mrvl_bootimage
+mrvl_bootimage: $(BUILD_PLAT)/$(BOOT_IMAGE)
diff --git a/plat/marvell/marvell.mk b/plat/marvell/marvell.mk
index 8245753..b6a2b99 100644
--- a/plat/marvell/marvell.mk
+++ b/plat/marvell/marvell.mk
@@ -19,40 +19,3 @@
# Set board to work with DDR 32bit
DDR32 := 0
$(eval $(call add_define,DDR32))
-
-ifeq (${MARVELL_SECURE_BOOT},1)
-DOIMAGE_SEC_FLAGS := -c $(DOIMAGE_SEC)
-DOIMAGE_LIBS_CHECK = \
- if ! [ -d "/usr/include/mbedtls" ]; then \
- echo "****************************************" >&2; \
- echo "Missing mbedTLS installation! " >&2; \
- echo "Please download it from \"tls.mbed.org\"" >&2; \
- echo "Alternatively on Debian/Ubuntu system install" >&2; \
- echo "\"libmbedtls-dev\" package" >&2; \
- echo "Make sure to use version 2.1.0 or later" >&2; \
- echo "****************************************" >&2; \
- exit 1; \
- else if ! [ -f "/usr/include/libconfig.h" ]; then \
- echo "********************************************************" >&2; \
- echo "Missing Libconfig installation!" >&2; \
- echo "Please download it from \"www.hyperrealm.com/libconfig/\"" >&2; \
- echo "Alternatively on Debian/Ubuntu system install packages" >&2; \
- echo "\"libconfig8\" and \"libconfig8-dev\"" >&2; \
- echo "********************************************************" >&2; \
- exit 1; \
- fi \
- fi
-else #MARVELL_SECURE_BOOT
-DOIMAGE_LIBS_CHECK =
-DOIMAGE_SEC_FLAGS =
-endif #MARVELL_SECURE_BOOT
-
-mrvl_clean:
- @echo " Doimage CLEAN"
- ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${DOIMAGEPATH} clean
-
-${DOIMAGETOOL}: mrvl_clean
- @$(DOIMAGE_LIBS_CHECK)
- ${Q}${MAKE} --no-print-directory -C ${DOIMAGEPATH} VERSION=$(SUBVERSION) WTMI_IMG=$(WTMI_IMG)
-
-
diff --git a/plat/marvell/version.mk b/plat/marvell/version.mk
index e072e12..bb22255 100644
--- a/plat/marvell/version.mk
+++ b/plat/marvell/version.mk
@@ -1 +1 @@
-SUBVERSION = devel-18.12.0
+SUBVERSION = devel-18.12.2
diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
new file mode 100644
index 0000000..fca6913
--- /dev/null
+++ b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include "platform_def.h"
+#include "pmic_wrap_init.h"
+
+/* pmic wrap module wait_idle and read polling interval (in microseconds) */
+enum pwrap_polling_interval {
+ WAIT_IDLE_POLLING_DELAY_US = 1,
+ READ_POLLING_DELAY_US = 2
+};
+
+static uint32_t pwrap_check_idle(void *wacs_register, uint32_t timeout_us)
+{
+ uint32_t reg_rdata = 0U, retry;
+
+ retry = (timeout_us + WAIT_IDLE_POLLING_DELAY_US) /
+ WAIT_IDLE_POLLING_DELAY_US;
+ while (retry != 0) {
+ udelay(WAIT_IDLE_POLLING_DELAY_US);
+ reg_rdata = mmio_read_32((uintptr_t)wacs_register);
+ if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_IDLE) {
+ break;
+ }
+ retry--;
+ };
+
+ if (retry == 0) {
+ /* timeout */
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+
+ return 0U;
+}
+
+static uint32_t pwrap_check_vldclr(void *wacs_register, uint32_t timeout_us)
+{
+ uint32_t reg_rdata = 0U, retry;
+
+ retry = (timeout_us + READ_POLLING_DELAY_US) / READ_POLLING_DELAY_US;
+ while (retry != 0) {
+ udelay(READ_POLLING_DELAY_US);
+ reg_rdata = mmio_read_32((uintptr_t)wacs_register);
+ if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_WFVLDCLR) {
+ break;
+ }
+ retry--;
+ };
+
+ if (retry == 0) {
+ /* timeout */
+ return E_PWR_WAIT_IDLE_TIMEOUT;
+ }
+
+ return 0U;
+}
+
+static int32_t pwrap_wacs2(uint32_t write, uint32_t adr, uint32_t wdata,
+ uint32_t *rdata, uint32_t init_check)
+{
+ uint32_t reg_rdata, return_value;
+
+ if (init_check != 0) {
+ if ((mmio_read_32((uintptr_t)&mtk_pwrap->init_done) & 0x1) == 0) {
+ ERROR("initialization isn't finished\n");
+ return E_PWR_NOT_INIT_DONE;
+ }
+ }
+
+ /* Wait for Software Interface FSM state to be IDLE. */
+ return_value = pwrap_check_idle(&mtk_pwrap->wacs2_sta,
+ PWRAP_WAIT_IDLE_US);
+ if (return_value != 0) {
+ return return_value;
+ }
+
+ /* Set the write data */
+ if (write == 1) {
+ /* Set the write data. */
+ mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_wdata, wdata);
+ }
+
+ /* Send the command. */
+ mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_cmd, (write << 29) | adr);
+
+ if (write == 0) {
+ /*
+ * Wait for Software Interface FSM state to be WFVLDCLR,
+ * read the data and clear the valid flag.
+ */
+ return_value = pwrap_check_vldclr(&mtk_pwrap->wacs2_sta,
+ PWRAP_READ_US);
+ if (return_value != 0) {
+ return return_value;
+ }
+
+ if (rdata == NULL) {
+ return E_PWR_INVALID_ARG;
+ }
+
+ reg_rdata = mmio_read_32((uintptr_t)&mtk_pwrap->wacs2_rdata);
+ *rdata = reg_rdata;
+ mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_vldclr, 0x1);
+ }
+
+ return return_value;
+}
+
+/* external API for pmic_wrap user */
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata)
+{
+ return pwrap_wacs2(0, adr, 0, rdata, 1);
+}
+
+int32_t pwrap_write(uint32_t adr, uint32_t wdata)
+{
+ return pwrap_wacs2(1, adr, wdata, 0, 1);
+}
diff --git a/plat/mediatek/mt8183/drivers/uart/uart.c b/plat/mediatek/common/drivers/uart/uart.c
similarity index 94%
rename from plat/mediatek/mt8183/drivers/uart/uart.c
rename to plat/mediatek/common/drivers/uart/uart.c
index 3c6a980..b940eb3 100644
--- a/plat/mediatek/mt8183/drivers/uart/uart.c
+++ b/plat/mediatek/common/drivers/uart/uart.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,7 @@
static struct mt_uart uart_save_addr[DRV_SUPPORT_UART_PORTS];
-static const unsigned int uart_base_addr[DRV_SUPPORT_UART_PORTS] = {
+static const uint32_t uart_base_addr[DRV_SUPPORT_UART_PORTS] = {
UART0_BASE,
UART1_BASE
};
@@ -99,13 +99,14 @@
void mt_console_uart_cg(int on)
{
- if (on)
+ if (on == 1) {
mmio_write_32(UART_CLOCK_GATE_CLR, UART0_CLOCK_GATE_BIT);
- else
+ } else {
mmio_write_32(UART_CLOCK_GATE_SET, UART0_CLOCK_GATE_BIT);
+ }
}
-int mt_console_uart_cg_status(void)
+uint32_t mt_console_uart_cg_status(void)
{
return mmio_read_32(UART_CLOCK_GATE_STA) & UART0_CLOCK_GATE_BIT;
}
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index e96b4ad..7dac8a4 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -16,6 +16,7 @@
#include <drivers/generic_delay_timer.h>
#include <mcucfg.h>
#include <mt_gic_v3.h>
+#include <mt_timer.h>
#include <lib/coreboot.h>
#include <lib/mmio.h>
#include <mtk_mcdi.h>
@@ -148,6 +149,8 @@
mt_gic_driver_init();
mt_gic_init();
+ mt_systimer_init();
+
/* Init mcsi SF */
plat_mtk_cci_init_sf();
diff --git a/plat/mediatek/mt8183/drivers/timer/mt_timer.c b/plat/mediatek/mt8183/drivers/timer/mt_timer.c
new file mode 100644
index 0000000..0da4815
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/timer/mt_timer.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mcucfg.h>
+#include <mt_timer.h>
+#include <platform_def.h>
+
+static void enable_systimer_compensation(void)
+{
+ unsigned int reg;
+
+ reg = mmio_read_32(CNTCR_REG);
+ reg &= ~COMP_15_EN;
+ reg |= COMP_20_EN;
+ mmio_write_32(CNTCR_REG, reg);
+
+ NOTICE("[systimer] CNTCR_REG(0x%x)\n", mmio_read_32(CNTCR_REG));
+}
+
+void mt_systimer_init(void)
+{
+ /* systimer is default on, so we only enable systimer compensation */
+ enable_systimer_compensation();
+}
diff --git a/plat/mediatek/mt8183/drivers/timer/mt_timer.h b/plat/mediatek/mt8183/drivers/timer/mt_timer.h
new file mode 100644
index 0000000..0b8edc5
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/timer/mt_timer.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_TIMER_H
+#define MT_TIMER_H
+
+
+#define SYSTIMER_BASE (0x10017000)
+#define CNTCR_REG (SYSTIMER_BASE + 0x0)
+#define CNTSR_REG (SYSTIMER_BASE + 0x4)
+
+#define COMP_15_EN (1 << 10)
+#define COMP_20_EN (1 << 11)
+
+void mt_systimer_init(void);
+
+#endif /* MT_TIMER_H */
diff --git a/plat/mediatek/mt8183/drivers/uart/uart.h b/plat/mediatek/mt8183/drivers/uart/uart.h
index be04c35..062ce3a 100644
--- a/plat/mediatek/mt8183/drivers/uart/uart.h
+++ b/plat/mediatek/mt8183/drivers/uart/uart.h
@@ -95,6 +95,6 @@
void mt_uart_save(void);
void mt_uart_restore(void);
void mt_console_uart_cg(int on);
-int mt_console_uart_cg_status(void);
+uint32_t mt_console_uart_cg_status(void);
#endif /* __UART_H__ */
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 3ccc928..07da1af 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -14,6 +14,7 @@
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/spmc/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
+ -I${MTK_PLAT_SOC}/drivers/timer/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
-I${MTK_PLAT_SOC}/drivers/spm/ \
-I${MTK_PLAT_SOC}/drivers/sspm/ \
@@ -44,6 +45,7 @@
${MTK_PLAT}/common/mtk_plat_common.c \
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
+ ${MTK_PLAT}/common/drivers/uart/uart.c \
${MTK_PLAT}/common/params_setup.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/aarch64/platform_common.c \
@@ -57,7 +59,7 @@
${MTK_PLAT_SOC}/drivers/spm/spm_pmic_wrap.c \
${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
- ${MTK_PLAT_SOC}/drivers/uart/uart.c \
+ ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c \
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_topology.c \
diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c
index f965281..9de4a2e 100644
--- a/plat/mediatek/mt8192/bl31_plat_setup.c
+++ b/plat/mediatek/mt8192/bl31_plat_setup.c
@@ -11,11 +11,16 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
+#include <drivers/generic_delay_timer.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/coreboot.h>
/* Platform Includes */
+#include <emi_mpu/emi_mpu.h>
+#include <gpio/mtgpio.h>
#include <mt_gic_v3.h>
+#include <mt_timer.h>
+#include <mtk_dcm.h>
#include <plat_params.h>
#include <plat_private.h>
@@ -80,9 +85,21 @@
******************************************************************************/
void bl31_platform_setup(void)
{
+ /* Set dcm on */
+ if (!dcm_set_default()) {
+ ERROR("Failed to set default dcm on!!\n");
+ }
+
+ /* MPU Init */
+ emi_mpu_init();
+
/* Initialize the GIC driver, CPU and distributor interfaces */
mt_gic_driver_init();
mt_gic_init();
+
+ plat_mt8192_gpio_init();
+ mt_systimer_init();
+ generic_delay_timer_init();
}
/*******************************************************************************
diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c
new file mode 100644
index 0000000..dd8bf4e
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_dcm.h>
+#include <mtk_dcm_utils.h>
+
+static void dcm_armcore(bool mode)
+{
+ dcm_mp_cpusys_top_bus_pll_div_dcm(mode);
+ dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode);
+ dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode);
+}
+
+static void dcm_mcusys(bool on)
+{
+ dcm_mp_cpusys_top_adb_dcm(on);
+ dcm_mp_cpusys_top_apb_dcm(on);
+ dcm_mp_cpusys_top_cpubiu_dcm(on);
+ dcm_mp_cpusys_top_misc_dcm(on);
+ dcm_mp_cpusys_top_mp0_qdcm(on);
+ dcm_cpccfg_reg_emi_wfifo(on);
+ dcm_mp_cpusys_top_last_cor_idle_dcm(on);
+}
+
+static void dcm_stall(bool on)
+{
+ dcm_mp_cpusys_top_core_stall_dcm(on);
+ dcm_mp_cpusys_top_fcm_stall_dcm(on);
+}
+
+static bool check_dcm_state(void)
+{
+ bool ret = true;
+
+ ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on();
+
+ ret &= dcm_mp_cpusys_top_adb_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_apb_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_misc_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on();
+ ret &= dcm_cpccfg_reg_emi_wfifo_is_on();
+ ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on();
+
+ ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on();
+
+ return ret;
+}
+
+bool dcm_set_default(void)
+{
+ dcm_armcore(true);
+ dcm_mcusys(true);
+ dcm_stall(true);
+
+ return check_dcm_state();
+}
diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h
new file mode 100644
index 0000000..ee98d0e
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_DCM_H
+#define MTK_DCM_H
+
+#include <stdbool.h>
+
+bool dcm_set_default(void);
+
+#endif /* #ifndef MTK_DCM_H */
diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c
new file mode 100644
index 0000000..15a700c
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.c
@@ -0,0 +1,562 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mtk_dcm_utils.h>
+
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \
+ BIT(16) | \
+ BIT(17) | \
+ BIT(18) | \
+ BIT(21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \
+ BIT(16) | \
+ BIT(17) | \
+ BIT(18))
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \
+ BIT(16) | \
+ BIT(17) | \
+ BIT(18) | \
+ BIT(21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \
+ BIT(16) | \
+ BIT(17) | \
+ BIT(18))
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \
+ (0x0 << 16) | \
+ (0x0 << 17) | \
+ (0x0 << 18) | \
+ (0x0 << 21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \
+ (0x0 << 16) | \
+ (0x0 << 17) | \
+ (0x0 << 18))
+
+bool dcm_mp_cpusys_top_adb_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_ADB_DCM_CFG0) &
+ MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
+ ret &= ((mmio_read_32(MP_ADB_DCM_CFG4) &
+ MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
+ ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) &
+ MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_adb_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */
+ mmio_clrsetbits_32(MP_ADB_DCM_CFG0,
+ MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
+ mmio_clrsetbits_32(MP_ADB_DCM_CFG4,
+ MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
+ mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
+ MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */
+ mmio_clrsetbits_32(MP_ADB_DCM_CFG0,
+ MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG0_OFF);
+ mmio_clrsetbits_32(MP_ADB_DCM_CFG4,
+ MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG1_OFF);
+ mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
+ MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG2_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16))
+#define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16))
+#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16))
+
+bool dcm_mp_cpusys_top_apb_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
+ MP_CPUSYS_TOP_APB_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON);
+ ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) &
+ MP_CPUSYS_TOP_APB_DCM_REG1_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON);
+ ret &= ((mmio_read_32(MP0_DCM_CFG0) &
+ MP_CPUSYS_TOP_APB_DCM_REG2_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_apb_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */
+ mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG0_ON);
+ mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG1_ON);
+ mmio_clrsetbits_32(MP0_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG2_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */
+ mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG0_OFF);
+ mmio_clrsetbits_32(MCUSYS_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG1_OFF);
+ mmio_clrsetbits_32(MP0_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG2_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(BUS_PLLDIV_CFG) &
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
+ mmio_clrsetbits_32(BUS_PLLDIV_CFG,
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
+ mmio_clrsetbits_32(BUS_PLLDIV_CFG,
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0))
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0))
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0))
+
+bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP0_DCM_CFG7) &
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_core_stall_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */
+ mmio_clrsetbits_32(MP0_DCM_CFG7,
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */
+ mmio_clrsetbits_32(MP0_DCM_CFG7,
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0))
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0))
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0))
+
+bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MCSI_DCM0) &
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_cpubiu_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */
+ mmio_clrsetbits_32(MCSI_DCM0,
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */
+ mmio_clrsetbits_32(MCSI_DCM0,
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(CPU_PLLDIV_CFG0) &
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG0,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG0,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(CPU_PLLDIV_CFG1) &
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG1,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG1,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(CPU_PLLDIV_CFG2) &
+ MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG2,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_2_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG2,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_2_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(CPU_PLLDIV_CFG3) &
+ MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG3,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_3_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG3,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_3_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON (BIT(11))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF ((0x0 << 11))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(CPU_PLLDIV_CFG4) &
+ MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG4,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_4_dcm'" */
+ mmio_clrsetbits_32(CPU_PLLDIV_CFG4,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_4_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4))
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4))
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4))
+
+bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP0_DCM_CFG7) &
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_fcm_stall_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */
+ mmio_clrsetbits_32(MP0_DCM_CFG7,
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */
+ mmio_clrsetbits_32(MP0_DCM_CFG7,
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31))
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31))
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0U << 31))
+
+bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(BUS_PLLDIV_CFG) &
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
+ mmio_clrsetbits_32(BUS_PLLDIV_CFG,
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
+ mmio_clrsetbits_32(BUS_PLLDIV_CFG,
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \
+ BIT(4))
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \
+ BIT(4))
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \
+ (0x0 << 4))
+
+bool dcm_mp_cpusys_top_misc_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
+ MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_misc_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */
+ mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */
+ mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_MISC_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \
+ BIT(1) | \
+ BIT(2) | \
+ BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \
+ BIT(1) | \
+ BIT(2) | \
+ BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 2) | \
+ (0x0 << 3))
+
+bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) &
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
+ ret &= ((mmio_read_32(MP0_DCM_CFG0) &
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_mp0_qdcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */
+ mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
+ mmio_clrsetbits_32(MP0_DCM_CFG0,
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */
+ mmio_clrsetbits_32(MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF);
+ mmio_clrsetbits_32(MP0_DCM_CFG0,
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF);
+ }
+}
+
+#define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \
+ BIT(1) | \
+ BIT(2) | \
+ BIT(3))
+#define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \
+ BIT(1) | \
+ BIT(2) | \
+ BIT(3))
+#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 2) | \
+ (0x0 << 3))
+
+bool dcm_cpccfg_reg_emi_wfifo_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(EMI_WFIFO) &
+ CPCCFG_REG_EMI_WFIFO_REG0_MASK) ==
+ (unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON);
+
+ return ret;
+}
+
+void dcm_cpccfg_reg_emi_wfifo(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */
+ mmio_clrsetbits_32(EMI_WFIFO,
+ CPCCFG_REG_EMI_WFIFO_REG0_MASK,
+ CPCCFG_REG_EMI_WFIFO_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */
+ mmio_clrsetbits_32(EMI_WFIFO,
+ CPCCFG_REG_EMI_WFIFO_REG0_MASK,
+ CPCCFG_REG_EMI_WFIFO_REG0_OFF);
+ }
+}
+
diff --git a/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h
new file mode 100644
index 0000000..1cf7834
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dcm/mtk_dcm_utils.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_DCM_UTILS_H
+#define MTK_DCM_UTILS_H
+
+#include <stdbool.h>
+
+#include <mtk_dcm.h>
+#include <platform_def.h>
+
+/* Base */
+#define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)
+#define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
+
+/* Register Definition */
+#define CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
+#define CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
+#define CPU_PLLDIV_CFG2 (MP_CPUSYS_TOP_BASE + 0x22a8)
+#define CPU_PLLDIV_CFG3 (MP_CPUSYS_TOP_BASE + 0x22ac)
+#define CPU_PLLDIV_CFG4 (MP_CPUSYS_TOP_BASE + 0x22b0)
+#define BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
+#define MCSI_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
+#define MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500)
+#define MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
+#define MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518)
+#define MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
+#define EMI_WFIFO (CPCCFG_REG_BASE + 0x100)
+#define MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
+#define MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c)
+
+/* MP_CPUSYS_TOP */
+bool dcm_mp_cpusys_top_adb_dcm_is_on(void);
+void dcm_mp_cpusys_top_adb_dcm(bool on);
+bool dcm_mp_cpusys_top_apb_dcm_is_on(void);
+void dcm_mp_cpusys_top_apb_dcm(bool on);
+bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void);
+void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on);
+bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void);
+void dcm_mp_cpusys_top_core_stall_dcm(bool on);
+bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpubiu_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_3_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_3_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_4_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_4_dcm(bool on);
+bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void);
+void dcm_mp_cpusys_top_fcm_stall_dcm(bool on);
+bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void);
+void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on);
+bool dcm_mp_cpusys_top_misc_dcm_is_on(void);
+void dcm_mp_cpusys_top_misc_dcm(bool on);
+bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void);
+void dcm_mp_cpusys_top_mp0_qdcm(bool on);
+/* CPCCFG_REG */
+bool dcm_cpccfg_reg_emi_wfifo_is_on(void);
+void dcm_cpccfg_reg_emi_wfifo(bool on);
+
+#endif
diff --git a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
new file mode 100644
index 0000000..d5d7e2e
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <emi_mpu.h>
+#include <lib/mmio.h>
+
+/*
+ * emi_mpu_set_region_protection: protect a region.
+ * @start: start address of the region
+ * @end: end address of the region
+ * @access_permission: EMI MPU access permission
+ * Return 0 for success, otherwise negative status code.
+ */
+static int _emi_mpu_set_protection(
+ unsigned long start, unsigned long end,
+ unsigned int apc)
+{
+ unsigned int dgroup;
+ unsigned int region;
+
+ region = (start >> 24) & 0xFF;
+ start &= 0x00FFFFFF;
+ dgroup = (end >> 24) & 0xFF;
+ end &= 0x00FFFFFF;
+
+ if ((region >= EMI_MPU_REGION_NUM) || (dgroup > EMI_MPU_DGROUP_NUM)) {
+ WARN("Region:%u or dgroup:%u is wrong!\n", region, dgroup);
+ return -1;
+ }
+
+ apc &= 0x80FFFFFF;
+
+ if ((start >= DRAM_OFFSET) && (end >= start)) {
+ start -= DRAM_OFFSET;
+ end -= DRAM_OFFSET;
+ } else {
+ WARN("start:0x%lx or end:0x%lx address is wrong!\n",
+ start, end);
+ return -2;
+ }
+
+ mmio_write_32(EMI_MPU_SA(region), start);
+ mmio_write_32(EMI_MPU_EA(region), end);
+ mmio_write_32(EMI_MPU_APC(region, dgroup), apc);
+
+ return 0;
+}
+
+void dump_emi_mpu_regions(void)
+{
+ unsigned long apc[EMI_MPU_DGROUP_NUM], sa, ea;
+
+ int region, i;
+
+ /* Only dump 8 regions(max: EMI_MPU_REGION_NUM --> 32) */
+ for (region = 0; region < 8; ++region) {
+ for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i)
+ apc[i] = mmio_read_32(EMI_MPU_APC(region, i));
+ sa = mmio_read_32(EMI_MPU_SA(region));
+ ea = mmio_read_32(EMI_MPU_EA(region));
+
+ WARN("region %d:\n", region);
+ WARN("\tsa:0x%lx, ea:0x%lx, apc0: 0x%lx apc1: 0x%lx\n",
+ sa, ea, apc[0], apc[1]);
+ }
+}
+
+int emi_mpu_set_protection(struct emi_region_info_t *region_info)
+{
+ unsigned long start, end;
+ int i;
+
+ if (region_info->region >= EMI_MPU_REGION_NUM)
+ return -1;
+
+ start = (unsigned long)(region_info->start >> EMI_MPU_ALIGN_BITS) |
+ (region_info->region << 24);
+
+ for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) {
+ end = (unsigned long)(region_info->end >> EMI_MPU_ALIGN_BITS) |
+ (i << 24);
+ _emi_mpu_set_protection(start, end, region_info->apc[i]);
+ }
+
+ return 0;
+}
+
+void emi_mpu_init(void)
+{
+ /* Set permission */
+ struct emi_region_info_t region_info;
+
+ /* PCE-e protect address(TODO) */
+ region_info.start = 0x80000000ULL;
+ region_info.end = 0x83FF0000ULL;
+ region_info.region = 1;
+ SET_ACCESS_PERMISSION(region_info.apc, 1,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, NO_PROT,
+ NO_PROT /*FORBIDDEN*/);
+ emi_mpu_set_protection(®ion_info);
+
+ /* Forbidden All */
+ region_info.start = 0x40000000ULL; /* dram base addr */
+ region_info.end = 0x1FFFF0000ULL;
+ region_info.region = 2;
+ SET_ACCESS_PERMISSION(region_info.apc, 1,
+ NO_PROT, NO_PROT, NO_PROT, NO_PROT,
+ NO_PROT, NO_PROT, NO_PROT, NO_PROT,
+ NO_PROT, NO_PROT, NO_PROT, NO_PROT,
+ NO_PROT, FORBIDDEN, NO_PROT, NO_PROT);
+ emi_mpu_set_protection(®ion_info);
+
+ dump_emi_mpu_regions();
+}
+
diff --git a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.h
new file mode 100644
index 0000000..0b15431
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EMI_MPU_H
+#define EMI_MPU_H
+
+#include <platform_def.h>
+
+#define EMI_MPUP (EMI_BASE + 0x01D8)
+#define EMI_MPUQ (EMI_BASE + 0x01E0)
+#define EMI_MPUR (EMI_BASE + 0x01E8)
+#define EMI_MPUS (EMI_BASE + 0x01F0)
+#define EMI_MPUT (EMI_BASE + 0x01F8)
+#define EMI_MPUY (EMI_BASE + 0x0220)
+#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000)
+#define EMI_MPUD0_ST (EMI_BASE + 0x0160)
+#define EMI_MPUD1_ST (EMI_BASE + 0x0164)
+#define EMI_MPUD2_ST (EMI_BASE + 0x0168)
+#define EMI_MPUD3_ST (EMI_BASE + 0x016C)
+#define EMI_MPUD0_ST2 (EMI_BASE + 0x0200)
+#define EMI_MPUD1_ST2 (EMI_BASE + 0x0204)
+#define EMI_MPUD2_ST2 (EMI_BASE + 0x0208)
+#define EMI_MPUD3_ST2 (EMI_BASE + 0x020C)
+
+#define EMI_PHY_OFFSET (0x40000000UL)
+
+#define NO_PROT (0)
+#define SEC_RW (1)
+#define SEC_RW_NSEC_R (2)
+#define SEC_RW_NSEC_W (3)
+#define SEC_R_NSEC_R (4)
+#define FORBIDDEN (5)
+#define SEC_R_NSEC_RW (6)
+
+#define SECURE_OS_MPU_REGION_ID (0)
+#define ATF_MPU_REGION_ID (1)
+
+#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
+#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
+#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region) * 4)
+#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region) * 4)
+
+#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
+#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region) * 4 + \
+ (dgroup) * 0x100)
+
+#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
+#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + domain * 4)
+#define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
+#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + domain * 4)
+
+#define EMI_MPU_DOMAIN_NUM 16
+#define EMI_MPU_REGION_NUM 32
+#define EMI_MPU_ALIGN_BITS 16
+#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
+
+#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
+
+#if (EMI_MPU_DGROUP_NUM == 1)
+#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \
+do { \
+ apc_ary[0] = 0; \
+ apc_ary[0] = \
+ (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \
+ | (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \
+ | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \
+ | (((unsigned int) d1) << 3) | ((unsigned int) d0) \
+ | (((unsigned int) lock) << 31); \
+} while (0)
+#elif (EMI_MPU_DGROUP_NUM == 2)
+#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \
+ d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \
+do { \
+ apc_ary[1] = \
+ (((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) \
+ | (((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) \
+ | (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) \
+ | (((unsigned int) d9) << 3) | ((unsigned int) d8); \
+ apc_ary[0] = \
+ (((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \
+ | (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \
+ | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \
+ | (((unsigned int) d1) << 3) | ((unsigned int) d0) \
+ | (((unsigned int) lock) << 31); \
+} while (0)
+#endif
+
+struct emi_region_info_t {
+ unsigned long long start;
+ unsigned long long end;
+ unsigned int region;
+ unsigned long apc[EMI_MPU_DGROUP_NUM];
+};
+
+void emi_mpu_init(void);
+int emi_mpu_set_protection(struct emi_region_info_t *region_info);
+void dump_emi_mpu_regions(void);
+
+#endif /* __EMI_MPU_H */
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
new file mode 100644
index 0000000..e07b75a
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/gpio.h>
+#include <lib/mmio.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+/******************************************************************************
+ *Macro Definition
+ ******************************************************************************/
+#define GPIO_MODE_BITS 4
+#define MAX_GPIO_MODE_PER_REG 8
+#define MAX_GPIO_REG_BITS 32
+#define DIR_BASE (GPIO_BASE + 0x000)
+#define DOUT_BASE (GPIO_BASE + 0x100)
+#define DIN_BASE (GPIO_BASE + 0x200)
+#define MODE_BASE (GPIO_BASE + 0x300)
+#define SET 0x4
+#define CLR 0x8
+
+static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(dir < MT_GPIO_DIR_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (dir == MT_GPIO_DIR_IN) {
+ mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
+ } else {
+ mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
+ }
+}
+
+static int mt_get_gpio_dir_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIR_BASE + 0x10U * pos);
+ return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
+}
+
+static void mt_set_gpio_out_chip(uint32_t pin, int output)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(output < MT_GPIO_OUT_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (output == MT_GPIO_OUT_ZERO) {
+ mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
+ } else {
+ mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
+ }
+}
+
+static int mt_get_gpio_in_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIN_BASE + 0x10U * pos);
+ return (((reg & (1U << bit)) != 0U) ? 1 : 0);
+}
+
+static uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+{
+ uintptr_t reg_addr = 0U;
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt8192_pin_infos[pin];
+
+ switch (gpio_info.base & 0x0f) {
+ case 0:
+ reg_addr = IOCFG_RM_BASE;
+ break;
+ case 1:
+ reg_addr = IOCFG_BM_BASE;
+ break;
+ case 2:
+ reg_addr = IOCFG_BL_BASE;
+ break;
+ case 3:
+ reg_addr = IOCFG_BR_BASE;
+ break;
+ case 4:
+ reg_addr = IOCFG_LM_BASE;
+ break;
+ case 5:
+ reg_addr = IOCFG_LB_BASE;
+ break;
+ case 6:
+ reg_addr = IOCFG_RT_BASE;
+ break;
+ case 7:
+ reg_addr = IOCFG_LT_BASE;
+ break;
+ case 8:
+ reg_addr = IOCFG_TL_BASE;
+ break;
+ default:
+ break;
+ }
+
+ return reg_addr;
+}
+
+static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
+ int select)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt8192_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 + (gpio_info.base & 0xf0);
+ if (enable == MT_GPIO_PULL_ENABLE) {
+ mmio_write_32(reg2 + SET, (1U << bit));
+ if (select == MT_GPIO_PULL_DOWN) {
+ mmio_write_32(reg1 + SET, (1U << bit));
+ } else {
+ mmio_write_32(reg1 + CLR, (1U << bit));
+ }
+ } else {
+ mmio_write_32(reg2 + CLR, (1U << bit));
+ mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
+ }
+}
+
+static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
+ int select)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt8192_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 - (gpio_info.base & 0xf0);
+
+ if (enable == MT_GPIO_PULL_ENABLE) {
+ if (select == MT_GPIO_PULL_DOWN) {
+ mmio_write_32(reg1 + CLR, (1U << bit));
+ mmio_write_32(reg2 + SET, (1U << bit));
+ } else {
+ mmio_write_32(reg2 + CLR, (1U << bit));
+ mmio_write_32(reg1 + SET, (1U << bit));
+ }
+ } else {
+ mmio_write_32(reg1 + CLR, (1U << bit));
+ mmio_write_32(reg2 + CLR, (1U << bit));
+ }
+}
+
+static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
+ int select)
+{
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt8192_pin_infos[pin];
+ if (gpio_info.flag) {
+ mt_gpio_set_spec_pull_pupd(pin, enable, select);
+ } else {
+ mt_gpio_set_pull_pu_pd(pin, enable, select);
+ }
+}
+
+static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ uint32_t r0;
+ uint32_t r1;
+
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt8192_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 + (gpio_info.base & 0xf0);
+
+ r0 = (mmio_read_32(reg2) >> bit) & 1U;
+ r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
+ if (r0 == 0U && r1 == 0U) {
+ return MT_GPIO_PULL_NONE;
+ } else {
+ if (mmio_read_32(reg1) & (1U << bit)) {
+ return MT_GPIO_PULL_DOWN;
+ } else {
+ return MT_GPIO_PULL_UP;
+ }
+ }
+}
+
+static int mt_gpio_get_pull_pu_pd(uint32_t pin)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ uint32_t pu;
+ uint32_t pd;
+
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt8192_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 - (gpio_info.base & 0xf0);
+ pu = (mmio_read_32(reg1) >> bit) & 1U;
+ pd = (mmio_read_32(reg2) >> bit) & 1U;
+ if (pu == 1U) {
+ return MT_GPIO_PULL_UP;
+ } else if (pd == 1U) {
+ return MT_GPIO_PULL_DOWN;
+ } else {
+ return MT_GPIO_PULL_NONE;
+ }
+}
+
+static int mt_gpio_get_pull_chip(uint32_t pin)
+{
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt8192_pin_infos[pin];
+ if (gpio_info.flag) {
+ return mt_gpio_get_spec_pull_pupd(pin);
+ } else {
+ return mt_gpio_get_pull_pu_pd(pin);
+ }
+}
+
+static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
+{
+ assert(pin < MAX_GPIO_PIN);
+
+ if (sel == MT_GPIO_PULL_NONE) {
+ mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
+ } else if (sel == MT_GPIO_PULL_UP) {
+ mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
+ } else if (sel == MT_GPIO_PULL_DOWN) {
+ mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
+ }
+}
+
+/* get pull-up or pull-down, regardless of resistor value */
+static int mt_get_gpio_pull_select_chip(uint32_t pin)
+{
+ assert(pin < MAX_GPIO_PIN);
+
+ return mt_gpio_get_pull_chip(pin);
+}
+
+static void mt_set_gpio_dir(int gpio, int direction)
+{
+ mt_set_gpio_dir_chip((uint32_t)gpio, direction);
+}
+
+static int mt_get_gpio_dir(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_dir_chip(pin);
+}
+
+static void mt_set_gpio_pull(int gpio, int pull)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_pull_select_chip(pin, pull);
+}
+
+static int mt_get_gpio_pull(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_pull_select_chip(pin);
+}
+
+static void mt_set_gpio_out(int gpio, int value)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_out_chip(pin, value);
+}
+
+static int mt_get_gpio_in(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_in_chip(pin);
+}
+
+const gpio_ops_t mtgpio_ops = {
+ .get_direction = mt_get_gpio_dir,
+ .set_direction = mt_set_gpio_dir,
+ .get_value = mt_get_gpio_in,
+ .set_value = mt_set_gpio_out,
+ .set_pull = mt_set_gpio_pull,
+ .get_pull = mt_get_gpio_pull,
+};
+
+void plat_mt8192_gpio_init(void)
+{
+ gpio_init(&mtgpio_ops);
+}
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
new file mode 100644
index 0000000..ca0c964
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <plat/common/common_def.h>
+
+/* Error Code No. */
+#define RSUCCESS 0
+#define ERACCESS 1
+#define ERINVAL 2
+#define ERWRAPPER 3
+#define MAX_GPIO_PIN MT_GPIO_BASE_MAX
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+ GPIO_UNSUPPORTED = -1,
+
+ GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
+ GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15,
+ GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23,
+ GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31,
+ GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39,
+ GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47,
+ GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55,
+ GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63,
+ GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71,
+ GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79,
+ GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87,
+ GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95,
+ GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103,
+ GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111,
+ GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119,
+ GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127,
+ GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135,
+ GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143,
+ GPIO144, GPIO145, GPIO146, GPIO147, GPIO148, GPIO149, GPIO150, GPIO151,
+ GPIO152, GPIO153, GPIO154, GPIO155, GPIO156, GPIO157, GPIO158, GPIO159,
+ GPIO160, GPIO161, GPIO162, GPIO163, GPIO164, GPIO165, GPIO166, GPIO167,
+ GPIO168, GPIO169, GPIO170, GPIO171, GPIO172, GPIO173, GPIO174, GPIO175,
+ GPIO176, GPIO177, GPIO178, GPIO179, GPIO180, GPIO181, GPIO182, GPIO183,
+ GPIO184, GPIO185, GPIO186, GPIO187, GPIO188, GPIO189, GPIO190, GPIO191,
+ GPIO192, GPIO193, GPIO194, GPIO195, GPIO196, GPIO197, GPIO198, GPIO199,
+ GPIO200, GPIO201, GPIO202, GPIO203, GPIO204, GPIO205, GPIO206, GPIO207,
+ GPIO208, GPIO209, GPIO210, GPIO211, GPIO212, GPIO213, GPIO214, GPIO215,
+ GPIO216, GPIO217, GPIO218, GPIO219,
+ MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+/* GPIO MODE CONTROL VALUE*/
+typedef enum {
+ GPIO_MODE_UNSUPPORTED = -1,
+ GPIO_MODE_GPIO = 0,
+ GPIO_MODE_00 = 0,
+ GPIO_MODE_01,
+ GPIO_MODE_02,
+ GPIO_MODE_03,
+ GPIO_MODE_04,
+ GPIO_MODE_05,
+ GPIO_MODE_06,
+ GPIO_MODE_07,
+
+ GPIO_MODE_MAX,
+ GPIO_MODE_DEFAULT = GPIO_MODE_00,
+} GPIO_MODE;
+
+/* GPIO DIRECTION */
+typedef enum {
+ MT_GPIO_DIR_UNSUPPORTED = -1,
+ MT_GPIO_DIR_OUT = 0,
+ MT_GPIO_DIR_IN = 1,
+ MT_GPIO_DIR_MAX,
+ MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
+} GPIO_DIR;
+
+/* GPIO PULL ENABLE*/
+typedef enum {
+ MT_GPIO_PULL_EN_UNSUPPORTED = -1,
+ MT_GPIO_PULL_DISABLE = 0,
+ MT_GPIO_PULL_ENABLE = 1,
+ MT_GPIO_PULL_ENABLE_R0 = 2,
+ MT_GPIO_PULL_ENABLE_R1 = 3,
+ MT_GPIO_PULL_ENABLE_R0R1 = 4,
+
+ MT_GPIO_PULL_EN_MAX,
+ MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
+} GPIO_PULL_EN;
+
+/* GPIO PULL-UP/PULL-DOWN*/
+typedef enum {
+ MT_GPIO_PULL_UNSUPPORTED = -1,
+ MT_GPIO_PULL_NONE = 0,
+ MT_GPIO_PULL_UP = 1,
+ MT_GPIO_PULL_DOWN = 2,
+ MT_GPIO_PULL_MAX,
+ MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
+} GPIO_PULL;
+
+/* GPIO OUTPUT */
+typedef enum {
+ MT_GPIO_OUT_UNSUPPORTED = -1,
+ MT_GPIO_OUT_ZERO = 0,
+ MT_GPIO_OUT_ONE = 1,
+
+ MT_GPIO_OUT_MAX,
+ MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
+ MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO, /*compatible with DCT*/
+} GPIO_OUT;
+
+/* GPIO INPUT */
+typedef enum {
+ MT_GPIO_IN_UNSUPPORTED = -1,
+ MT_GPIO_IN_ZERO = 0,
+ MT_GPIO_IN_ONE = 1,
+
+ MT_GPIO_IN_MAX,
+} GPIO_IN;
+
+typedef struct {
+ uint32_t val;
+ uint32_t set;
+ uint32_t rst;
+ uint32_t _align1;
+} VAL_REGS;
+
+typedef struct {
+ VAL_REGS dir[7];
+ uint8_t rsv00[144];
+ VAL_REGS dout[7];
+ uint8_t rsv01[144];
+ VAL_REGS din[7];
+ uint8_t rsv02[144];
+ VAL_REGS mode[28];
+} GPIO_REGS;
+
+
+#define PIN(_id, _flag, _bit, _base, _offset) { \
+ .id = _id, \
+ .flag = _flag, \
+ .bit = _bit, \
+ .base = _base, \
+ .offset = _offset, \
+ }
+
+struct mt_pin_info {
+ uint8_t id;
+ uint8_t flag;
+ uint8_t bit;
+ uint16_t base;
+ uint16_t offset;
+};
+
+static const struct mt_pin_info mt8192_pin_infos[] = {
+ PIN(0, 0, 9, 0x23, 0xb0),
+ PIN(1, 0, 10, 0x23, 0xb0),
+ PIN(2, 0, 11, 0x23, 0xb0),
+ PIN(3, 0, 12, 0x23, 0xb0),
+ PIN(4, 0, 13, 0x23, 0xb0),
+ PIN(5, 0, 14, 0x23, 0xb0),
+ PIN(6, 0, 15, 0x23, 0xb0),
+ PIN(7, 0, 16, 0x23, 0xb0),
+ PIN(8, 0, 17, 0x23, 0xb0),
+ PIN(9, 0, 18, 0x23, 0xb0),
+ PIN(10, 1, 0, 0x15, 0x20),
+ PIN(11, 1, 1, 0x15, 0x20),
+ PIN(12, 1, 2, 0x15, 0x20),
+ PIN(13, 1, 3, 0x15, 0x20),
+ PIN(14, 1, 4, 0x15, 0x20),
+ PIN(15, 1, 5, 0x15, 0x20),
+ PIN(16, 0, 2, 0x17, 0x50),
+ PIN(17, 0, 3, 0x17, 0x50),
+ PIN(18, 0, 21, 0x36, 0xa0),
+ PIN(19, 0, 22, 0x36, 0xa0),
+ PIN(20, 0, 23, 0x36, 0xa0),
+ PIN(21, 0, 24, 0x36, 0xa0),
+ PIN(22, 0, 3, 0x21, 0x90),
+ PIN(23, 0, 4, 0x21, 0x90),
+ PIN(24, 0, 5, 0x21, 0x90),
+ PIN(25, 0, 6, 0x21, 0x90),
+ PIN(26, 0, 5, 0x22, 0x80),
+ PIN(27, 0, 6, 0x22, 0x80),
+ PIN(28, 0, 7, 0x22, 0x80),
+ PIN(29, 0, 8, 0x22, 0x80),
+ PIN(30, 0, 9, 0x22, 0x80),
+ PIN(31, 0, 27, 0x22, 0x70),
+ PIN(32, 0, 24, 0x22, 0x70),
+ PIN(33, 0, 26, 0x22, 0x70),
+ PIN(34, 0, 23, 0x22, 0x70),
+ PIN(35, 0, 25, 0x22, 0x70),
+ PIN(36, 0, 20, 0x21, 0x90),
+ PIN(37, 0, 21, 0x21, 0x90),
+ PIN(38, 0, 22, 0x21, 0x90),
+ PIN(39, 0, 23, 0x21, 0x90),
+ PIN(40, 0, 0, 0x17, 0x50),
+ PIN(41, 0, 1, 0x17, 0x50),
+ PIN(42, 0, 4, 0x17, 0x50),
+ PIN(43, 0, 25, 0x36, 0xa0),
+ PIN(44, 0, 26, 0x36, 0xa0),
+ PIN(45, 1, 9, 0x20, 0x60),
+ PIN(46, 1, 11, 0x20, 0x60),
+ PIN(47, 1, 10, 0x20, 0x60),
+ PIN(48, 1, 7, 0x20, 0x60),
+ PIN(49, 1, 8, 0x20, 0x60),
+ PIN(50, 1, 6, 0x20, 0x60),
+ PIN(51, 1, 0, 0x20, 0x60),
+ PIN(52, 1, 1, 0x20, 0x60),
+ PIN(53, 1, 5, 0x20, 0x60),
+ PIN(54, 1, 2, 0x20, 0x60),
+ PIN(55, 1, 4, 0x20, 0x60),
+ PIN(56, 1, 3, 0x20, 0x60),
+ PIN(57, 0, 1, 0x22, 0x80),
+ PIN(58, 0, 2, 0x22, 0x80),
+ PIN(59, 0, 3, 0x22, 0x80),
+ PIN(60, 0, 4, 0x22, 0x80),
+ PIN(61, 0, 28, 0x22, 0x70),
+ PIN(62, 0, 22, 0x22, 0x70),
+ PIN(63, 0, 0, 0x22, 0x70),
+ PIN(64, 0, 1, 0x22, 0x70),
+ PIN(65, 0, 12, 0x22, 0x70),
+ PIN(66, 0, 15, 0x22, 0x70),
+ PIN(67, 0, 16, 0x22, 0x70),
+ PIN(68, 0, 17, 0x22, 0x70),
+ PIN(69, 0, 18, 0x22, 0x70),
+ PIN(70, 0, 19, 0x22, 0x70),
+ PIN(71, 0, 20, 0x22, 0x70),
+ PIN(72, 0, 21, 0x22, 0x70),
+ PIN(73, 0, 2, 0x22, 0x70),
+ PIN(74, 0, 3, 0x22, 0x70),
+ PIN(75, 0, 4, 0x22, 0x70),
+ PIN(76, 0, 5, 0x22, 0x70),
+ PIN(77, 0, 6, 0x22, 0x70),
+ PIN(78, 0, 7, 0x22, 0x70),
+ PIN(79, 0, 8, 0x22, 0x70),
+ PIN(80, 0, 9, 0x22, 0x70),
+ PIN(81, 0, 10, 0x22, 0x70),
+ PIN(82, 0, 11, 0x22, 0x70),
+ PIN(83, 0, 13, 0x22, 0x70),
+ PIN(84, 0, 14, 0x22, 0x70),
+ PIN(85, 0, 31, 0x22, 0x70),
+ PIN(86, 0, 0, 0x22, 0x80),
+ PIN(87, 0, 29, 0x22, 0x70),
+ PIN(88, 0, 30, 0x22, 0x70),
+ PIN(89, 0, 24, 0x21, 0x90),
+ PIN(90, 0, 25, 0x21, 0x90),
+ PIN(91, 0, 0, 0x21, 0x90),
+ PIN(92, 0, 2, 0x21, 0xa0),
+ PIN(93, 0, 4, 0x21, 0xa0),
+ PIN(94, 0, 3, 0x21, 0xa0),
+ PIN(95, 0, 5, 0x21, 0xa0),
+ PIN(96, 0, 31, 0x21, 0x90),
+ PIN(97, 0, 26, 0x21, 0x90),
+ PIN(98, 0, 0, 0x21, 0xa0),
+ PIN(99, 0, 27, 0x21, 0x90),
+ PIN(100, 0, 28, 0x21, 0x90),
+ PIN(101, 0, 29, 0x21, 0x90),
+ PIN(102, 0, 30, 0x21, 0x90),
+ PIN(103, 0, 18, 0x21, 0x90),
+ PIN(104, 0, 17, 0x21, 0x90),
+ PIN(105, 0, 19, 0x21, 0x90),
+ PIN(106, 0, 16, 0x21, 0x90),
+ PIN(107, 0, 1, 0x21, 0x90),
+ PIN(108, 0, 2, 0x21, 0x90),
+ PIN(109, 0, 10, 0x21, 0x90),
+ PIN(110, 0, 7, 0x21, 0x90),
+ PIN(111, 0, 9, 0x21, 0x90),
+ PIN(112, 0, 11, 0x21, 0x90),
+ PIN(113, 0, 8, 0x21, 0x90),
+ PIN(114, 0, 14, 0x21, 0x90),
+ PIN(115, 0, 13, 0x21, 0x90),
+ PIN(116, 0, 15, 0x21, 0x90),
+ PIN(117, 0, 12, 0x21, 0x90),
+ PIN(118, 0, 23, 0x23, 0xb0),
+ PIN(119, 0, 29, 0x23, 0xb0),
+ PIN(120, 0, 28, 0x23, 0xb0),
+ PIN(121, 0, 2, 0x23, 0xc0),
+ PIN(122, 0, 27, 0x23, 0xb0),
+ PIN(123, 0, 1, 0x23, 0xc0),
+ PIN(124, 0, 26, 0x23, 0xb0),
+ PIN(125, 0, 0, 0x23, 0xc0),
+ PIN(126, 0, 19, 0x23, 0xb0),
+ PIN(127, 0, 20, 0x23, 0xb0),
+ PIN(128, 0, 21, 0x23, 0xb0),
+ PIN(129, 0, 22, 0x23, 0xb0),
+ PIN(130, 0, 6, 0x23, 0xb0),
+ PIN(131, 0, 7, 0x23, 0xb0),
+ PIN(132, 0, 8, 0x23, 0xb0),
+ PIN(133, 0, 3, 0x23, 0xb0),
+ PIN(134, 0, 4, 0x23, 0xb0),
+ PIN(135, 0, 5, 0x23, 0xb0),
+ PIN(136, 0, 0, 0x23, 0xb0),
+ PIN(137, 0, 1, 0x23, 0xb0),
+ PIN(138, 0, 2, 0x23, 0xb0),
+ PIN(139, 0, 25, 0x23, 0xb0),
+ PIN(140, 0, 31, 0x23, 0xb0),
+ PIN(141, 0, 24, 0x23, 0xb0),
+ PIN(142, 0, 30, 0x23, 0xb0),
+ PIN(143, 0, 6, 0x20, 0x70),
+ PIN(144, 0, 7, 0x20, 0x70),
+ PIN(145, 0, 8, 0x20, 0x70),
+ PIN(146, 0, 3, 0x20, 0x70),
+ PIN(147, 0, 4, 0x20, 0x70),
+ PIN(148, 0, 5, 0x20, 0x70),
+ PIN(149, 0, 0, 0x20, 0x70),
+ PIN(150, 0, 1, 0x20, 0x70),
+ PIN(151, 0, 2, 0x20, 0x70),
+ PIN(152, 1, 3, 0x36, 0x90),
+ PIN(153, 1, 2, 0x36, 0x90),
+ PIN(154, 1, 0, 0x36, 0x906),
+ PIN(155, 1, 1, 0x36, 0x90),
+ PIN(156, 0, 29, 0x36, 0xa0),
+ PIN(157, 0, 30, 0x36, 0xa0),
+ PIN(158, 0, 31, 0x36, 0xa0),
+ PIN(159, 0, 0, 0x36, 0xb0),
+ PIN(160, 0, 27, 0x36, 0xa04),
+ PIN(161, 0, 28, 0x36, 0xa0),
+ PIN(162, 0, 0, 0x36, 0xa0),
+ PIN(163, 0, 1, 0x36, 0xa0),
+ PIN(164, 0, 2, 0x36, 0xa0),
+ PIN(165, 0, 3, 0x36, 0xa0),
+ PIN(166, 0, 4, 0x36, 0xa0),
+ PIN(167, 0, 5, 0x36, 0xa0),
+ PIN(168, 0, 6, 0x36, 0xa0),
+ PIN(169, 0, 7, 0x36, 0xa0),
+ PIN(170, 0, 8, 0x36, 0xa0),
+ PIN(171, 0, 9, 0x36, 0xa0),
+ PIN(172, 0, 13, 0x36, 0xa0),
+ PIN(173, 0, 14, 0x36, 0xa0),
+ PIN(174, 0, 12, 0x36, 0xa0),
+ PIN(175, 0, 15, 0x36, 0xa0),
+ PIN(176, 0, 10, 0x36, 0xa0),
+ PIN(177, 0, 11, 0x36, 0xa0),
+ PIN(178, 0, 16, 0x36, 0xa0),
+ PIN(179, 0, 17, 0x36, 0xa0),
+ PIN(180, 0, 18, 0x36, 0xa0),
+ PIN(181, 0, 19, 0x36, 0xa0),
+ PIN(182, 0, 20, 0x36, 0xa0),
+ PIN(183, 1, 1, 0x18, 0x30),
+ PIN(184, 1, 2, 0x18, 0x30),
+ PIN(185, 1, 4, 0x18, 0x30),
+ PIN(186, 1, 6, 0x18, 0x30),
+ PIN(187, 1, 8, 0x18, 0x30),
+ PIN(188, 1, 3, 0x18, 0x30),
+ PIN(189, 1, 7, 0x18, 0x30),
+ PIN(190, 1, 9, 0x18, 0x30),
+ PIN(191, 1, 10, 0x18, 0x30),
+ PIN(192, 1, 0, 0x18, 0x30),
+ PIN(193, 1, 5, 0x18, 0x30),
+ PIN(194, 1, 11, 0x18, 0x30),
+ PIN(195, 0, 16, 0x14, 0x50),
+ PIN(196, 0, 6, 0x14, 0x50),
+ PIN(197, 0, 8, 0x14, 0x50),
+ PIN(198, 0, 7, 0x14, 0x50),
+ PIN(199, 0, 3, 0x14, 0x50),
+ PIN(200, 0, 6, 0x17, 0x50),
+ PIN(201, 0, 8, 0x17, 0x50),
+ PIN(202, 0, 15, 0x14, 0x50),
+ PIN(203, 0, 17, 0x14, 0x50),
+ PIN(204, 0, 5, 0x17, 0x50),
+ PIN(205, 0, 7, 0x17, 0x50),
+ PIN(206, 0, 18, 0x14, 0x50),
+ PIN(207, 0, 19, 0x14, 0x50),
+ PIN(208, 0, 20, 0x14, 0x50),
+ PIN(209, 0, 12, 0x14, 0x50),
+ PIN(210, 0, 11, 0x14, 0x50),
+ PIN(211, 0, 13, 0x14, 0x50),
+ PIN(212, 0, 10, 0x14, 0x50),
+ PIN(213, 0, 14, 0x14, 0x50),
+ PIN(214, 0, 0, 0x14, 0x50),
+ PIN(215, 0, 9, 0x14, 0x50),
+ PIN(216, 0, 4, 0x14, 0x50),
+ PIN(217, 0, 5, 0x14, 0x50),
+ PIN(218, 0, 1, 0x14, 0x50),
+ PIN(219, 0, 2, 0x14, 0x50),
+};
+
+void plat_mt8192_gpio_init(void);
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c
new file mode 100644
index 0000000..d6d4af7
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+#include <lib/spinlock.h>
+
+#include <mt_cpu_pm_cpc.h>
+#include <mt_mcdi.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1);
+
+static int plat_mt_lp_cpu_rc;
+
+static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state)
+{
+ return 0;
+}
+
+static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state)
+{
+ mtk_cpc_core_on_hint_clr(cpu);
+
+ if (IS_SYSTEM_SUSPEND_STATE(state)) {
+ mtk_cpc_time_sync();
+ }
+
+ return 0;
+}
+
+static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+ return 0;
+}
+
+static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+ /* clear DBGPRCR.CORENPDRQ to allow CPU power down */
+ write_dbgprcr_el1(0ULL);
+
+ return 0;
+}
+
+static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+ return 0;
+}
+
+static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+ return 0;
+}
+
+static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+ if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
+ return -1;
+ }
+
+ mtk_cpc_mcusys_off_reflect();
+
+ return 0;
+}
+
+static int pwr_mcusys_pwron_finished(unsigned int cpu,
+ const psci_power_state_t *state)
+{
+ if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
+ return -1;
+ }
+
+ return 0;
+}
+
+static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+ if (!IS_MCUSYS_OFF_STATE(state)) {
+ goto mt_pwr_mcusysoff_break;
+ }
+
+ if (mcdi_try_init() != 0) { /* not ready to process mcusys-off */
+ goto mt_pwr_mcusysoff_break;
+ }
+
+ return 0;
+
+mt_pwr_mcusysoff_break:
+
+ plat_mt_lp_cpu_rc = -1;
+
+ return -1;
+}
+
+static const struct mt_lpm_tz plat_pm = {
+ .pwr_prompt = pwr_state_prompt,
+ .pwr_reflect = pwr_state_reflect,
+ .pwr_cpu_on = pwr_cpu_pwron,
+ .pwr_cpu_dwn = pwr_cpu_pwrdwn,
+ .pwr_cluster_on = pwr_cluster_pwron,
+ .pwr_cluster_dwn = pwr_cluster_pwrdwn,
+ .pwr_mcusys_dwn = pwr_mcusys_pwrdwn,
+ .pwr_mcusys_on = pwr_mcusys_pwron,
+ .pwr_mcusys_on_finished = pwr_mcusys_pwron_finished
+};
+
+const struct mt_lpm_tz *mt_plat_cpu_pm_init(void)
+{
+ mtk_cpc_init();
+
+ if (mcdi_try_init() == 0) {
+ INFO("MCDI init done.\n");
+ }
+
+ return &plat_pm;
+}
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.c b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.c
new file mode 100644
index 0000000..f8c51a1
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <drivers/delay_timer.h>
+
+#include <mt_cpu_pm_cpc.h>
+#include <mt_timer.h>
+
+struct mtk_cpc_dev {
+ int auto_off;
+ unsigned int auto_thres_tick;
+};
+
+static struct mtk_cpc_dev cpc;
+
+static int mtk_cpc_last_core_prot(uint32_t prot_req,
+ uint32_t resp_reg, uint32_t resp_ofs)
+{
+ uint32_t sta, retry;
+
+ retry = 0U;
+
+ while (retry++ < RETRY_CNT_MAX) {
+
+ mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req);
+
+ udelay(1U);
+
+ sta = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK;
+
+ if (sta == PROT_SUCCESS) {
+ return CPC_SUCCESS;
+ } else if (sta == PROT_GIVEUP) {
+ return CPC_ERR_FAIL;
+ }
+ }
+
+ return CPC_ERR_TIMEOUT;
+}
+
+int mtk_cpu_pm_mcusys_prot_aquire(void)
+{
+ return mtk_cpc_last_core_prot(
+ MCUSYS_PROT_SET,
+ CPC_MCUSYS_LAST_CORE_RESP,
+ MCUSYS_RESP_OFS);
+}
+
+void mtk_cpu_pm_mcusys_prot_release(void)
+{
+ mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR);
+}
+
+int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster)
+{
+ return mtk_cpc_last_core_prot(
+ CPUSYS_PROT_SET,
+ CPC_MCUSYS_MP_LAST_CORE_RESP,
+ CPUSYS_RESP_OFS);
+}
+
+void mtk_cpu_pm_cluster_prot_release(unsigned int cluster)
+{
+ mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR);
+}
+
+static void mtk_cpc_cluster_cnt_backup(void)
+{
+ uint32_t backup_cnt;
+ uint32_t curr_cnt;
+ uint32_t cnt_mask = GENMASK(14, 0);
+ uint32_t clr_mask = GENMASK(1, 0);
+
+ /* Single Cluster */
+ backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP);
+ curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER);
+
+ /* Get off count if dormant count is 0 */
+ if ((curr_cnt & cnt_mask) == 0U) {
+ curr_cnt = (curr_cnt >> 16) & cnt_mask;
+ } else {
+ curr_cnt = curr_cnt & cnt_mask;
+ }
+
+ mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt);
+ mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask);
+}
+
+static inline void mtk_cpc_mcusys_off_en(void)
+{
+ mmio_write_32(CPC_MCUSYS_PWR_CTRL, 1U);
+}
+
+static inline void mtk_cpc_mcusys_off_dis(void)
+{
+ mmio_write_32(CPC_MCUSYS_PWR_CTRL, 0U);
+}
+
+void mtk_cpc_mcusys_off_reflect(void)
+{
+ mtk_cpc_mcusys_off_dis();
+ mtk_cpu_pm_mcusys_prot_release();
+}
+
+int mtk_cpc_mcusys_off_prepare(void)
+{
+ if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) {
+ return CPC_ERR_FAIL;
+ }
+
+ mtk_cpc_cluster_cnt_backup();
+ mtk_cpc_mcusys_off_en();
+
+ return CPC_SUCCESS;
+}
+
+void mtk_cpc_core_on_hint_set(unsigned int cpu)
+{
+ mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu));
+}
+
+void mtk_cpc_core_on_hint_clr(unsigned int cpu)
+{
+ mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu));
+}
+
+static void mtk_cpc_dump_timestamp(void)
+{
+ uint32_t id;
+
+ for (id = 0U; id < CPC_TRACE_ID_NUM; id++) {
+ mmio_write_32(CPC_MCUSYS_TRACE_SEL, id);
+
+ memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id),
+ (const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA,
+ CPC_TRACE_SIZE);
+ }
+}
+
+void mtk_cpc_time_sync(void)
+{
+ uint64_t kt;
+ uint32_t systime_l, systime_h;
+
+ kt = sched_clock();
+ systime_l = mmio_read_32(CNTSYS_L_REG);
+ systime_h = mmio_read_32(CNTSYS_H_REG);
+
+ /* sync kernel timer to cpc */
+ mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt);
+ mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32));
+ /* sync system timer to cpc */
+ mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l);
+ mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h);
+}
+
+static void mtk_cpc_config(uint32_t cfg, uint32_t data)
+{
+ uint32_t val;
+ uint32_t reg = 0U;
+
+ switch (cfg) {
+ case CPC_SMC_CONFIG_PROF:
+ reg = CPC_MCUSYS_CPC_DBG_SETTING;
+ val = mmio_read_32(reg);
+ val = (data != 0U) ? (val | CPC_PROF_EN) : (val & ~CPC_PROF_EN);
+ break;
+ case CPC_SMC_CONFIG_AUTO_OFF:
+ reg = CPC_MCUSYS_CPC_FLOW_CTRL_CFG;
+ val = mmio_read_32(reg);
+ if (data != 0U) {
+ val |= CPC_AUTO_OFF_EN;
+ cpc.auto_off = 1;
+ } else {
+ val &= ~CPC_AUTO_OFF_EN;
+ cpc.auto_off = 0;
+ }
+ break;
+ case CPC_SMC_CONFIG_AUTO_OFF_THRES:
+ reg = CPC_MCUSYS_CPC_OFF_THRES;
+ cpc.auto_thres_tick = us_to_ticks(data);
+ val = cpc.auto_thres_tick;
+ break;
+ case CPC_SMC_CONFIG_CNT_CLR:
+ reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR;
+ val = GENMASK(1, 0); /* clr_mask */
+ break;
+ case CPC_SMC_CONFIG_TIME_SYNC:
+ mtk_cpc_time_sync();
+ break;
+ default:
+ break;
+ }
+
+ if (reg != 0U) {
+ mmio_write_32(reg, val);
+ }
+}
+
+static uint32_t mtk_cpc_read_config(uint32_t cfg)
+{
+ uint32_t res = 0U;
+
+ switch (cfg) {
+ case CPC_SMC_CONFIG_PROF:
+ res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ?
+ 1U : 0U;
+ break;
+ case CPC_SMC_CONFIG_AUTO_OFF:
+ res = cpc.auto_off;
+ break;
+ case CPC_SMC_CONFIG_AUTO_OFF_THRES:
+ res = ticks_to_us(cpc.auto_thres_tick);
+ break;
+ case CPC_SMC_CONFIG_CNT_CLR:
+ break;
+ default:
+ break;
+ }
+
+ return res;
+}
+
+uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2)
+{
+ uint64_t res = 0ULL;
+
+ switch (act) {
+ case CPC_SMC_EVENT_DUMP_TRACE_DATA:
+ mtk_cpc_dump_timestamp();
+ break;
+ case CPC_SMC_EVENT_GIC_DPG_SET:
+ /* isolated_status = x2; */
+ break;
+ case CPC_SMC_EVENT_CPC_CONFIG:
+ mtk_cpc_config((uint32_t)arg1, (uint32_t)arg2);
+ break;
+ case CPC_SMC_EVENT_READ_CONFIG:
+ res = mtk_cpc_read_config((uint32_t)arg1);
+ break;
+ default:
+ break;
+ }
+
+ return res;
+}
+
+void mtk_cpc_init(void)
+{
+ mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING,
+ mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING)
+ | CPC_DBG_EN
+ | CPC_CALC_EN);
+
+ cpc.auto_off = 1;
+ cpc.auto_thres_tick = us_to_ticks(8000);
+
+ mmio_write_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG,
+ mmio_read_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG)
+ | CPC_OFF_PRE_EN
+ | (cpc.auto_off ? CPC_AUTO_OFF_EN : 0U));
+
+ mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick);
+}
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.h b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.h
new file mode 100644
index 0000000..19dd6a2
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm_cpc.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_CPU_PM_CPC_H
+#define MT_CPU_PM_CPC_H
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mcucfg.h>
+#include <platform_def.h>
+
+#define NEED_CPUSYS_PROT_WORKAROUND 1
+
+/* system sram registers */
+#define CPUIDLE_SRAM_REG(r) (uint32_t)(MTK_MCDI_SRAM_BASE + (r))
+
+/* db dump */
+#define CPC_TRACE_SIZE U(0x20)
+#define CPC_TRACE_ID_NUM U(10)
+#define CPC_TRACE_SRAM(id) (CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE)
+
+/* buckup off count */
+#define CPC_CLUSTER_CNT_BACKUP CPUIDLE_SRAM_REG(0x1F0)
+#define CPC_MCUSYS_CNT CPUIDLE_SRAM_REG(0x1F4)
+
+/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG(0xA814): debug setting */
+#define CPC_PWR_ON_SEQ_DIS BIT(1)
+#define CPC_PWR_ON_PRIORITY BIT(2)
+#define CPC_AUTO_OFF_EN BIT(5)
+#define CPC_DORMANT_WAIT_EN BIT(14)
+#define CPC_CTRL_EN BIT(16)
+#define CPC_OFF_PRE_EN BIT(29)
+
+/* CPC_MCUSYS_LAST_CORE_REQ(0xA818) : last core protection */
+#define CPUSYS_PROT_SET BIT(0)
+#define MCUSYS_PROT_SET BIT(8)
+#define CPUSYS_PROT_CLR BIT(8)
+#define MCUSYS_PROT_CLR BIT(9)
+
+#define CPC_PROT_RESP_MASK U(0x3)
+#define CPUSYS_RESP_OFS U(16)
+#define MCUSYS_RESP_OFS U(30)
+
+#define cpusys_resp(r) (((r) >> CPUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
+#define mcusys_resp(r) (((r) >> MCUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
+
+#define RETRY_CNT_MAX U(1000)
+
+#define PROT_RETRY U(0)
+#define PROT_SUCCESS U(1)
+#define PROT_GIVEUP U(2)
+
+/* CPC_MCUSYS_CPC_DBG_SETTING(0xAB00): debug setting */
+#define CPC_PROF_EN BIT(0)
+#define CPC_DBG_EN BIT(1)
+#define CPC_FREEZE BIT(2)
+#define CPC_CALC_EN BIT(3)
+
+enum {
+ CPC_SUCCESS = 0,
+
+ CPC_ERR_FAIL,
+ CPC_ERR_TIMEOUT,
+
+ NF_CPC_ERR
+};
+
+enum {
+ CPC_SMC_EVENT_DUMP_TRACE_DATA,
+ CPC_SMC_EVENT_GIC_DPG_SET,
+ CPC_SMC_EVENT_CPC_CONFIG,
+ CPC_SMC_EVENT_READ_CONFIG,
+
+ NF_CPC_SMC_EVENT
+};
+
+enum {
+ CPC_SMC_CONFIG_PROF,
+ CPC_SMC_CONFIG_AUTO_OFF,
+ CPC_SMC_CONFIG_AUTO_OFF_THRES,
+ CPC_SMC_CONFIG_CNT_CLR,
+ CPC_SMC_CONFIG_TIME_SYNC,
+
+ NF_CPC_SMC_CONFIG
+};
+
+#define us_to_ticks(us) ((us) * 13)
+#define ticks_to_us(tick) ((tick) / 13)
+
+int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster);
+void mtk_cpu_pm_cluster_prot_release(unsigned int cluster);
+
+void mtk_cpc_mcusys_off_reflect(void);
+int mtk_cpc_mcusys_off_prepare(void);
+
+void mtk_cpc_core_on_hint_set(unsigned int cpu);
+void mtk_cpc_core_on_hint_clr(unsigned int cpu);
+void mtk_cpc_time_sync(void);
+
+uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2);
+void mtk_cpc_init(void);
+
+#endif /* MT_CPU_PM_CPC_H */
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c
new file mode 100644
index 0000000..df74122
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cdefs.h>
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mt_mcdi.h>
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY U(0)
+#define APMCU_MCUPM_MBOX_RESERVED_1 U(1)
+#define APMCU_MCUPM_MBOX_RESERVED_2 U(2)
+#define APMCU_MCUPM_MBOX_RESERVED_3 U(3)
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN U(4)
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE U(5)
+#define APMCU_MCUPM_MBOX_BUCK_MODE U(6)
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE U(7)
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA U(8)
+#define APMCU_MCUPM_MBOX_RESERVED_9 U(9)
+#define APMCU_MCUPM_MBOX_RESERVED_10 U(10)
+#define APMCU_MCUPM_MBOX_RESERVED_11 U(11)
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU U(12)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN */
+#define MCUPM_MCUSYS_CTRL BIT(0)
+#define MCUPM_BUCK_CTRL BIT(1)
+#define MCUPM_ARMPLL_CTRL BIT(2)
+#define MCUPM_CM_CTRL BIT(3)
+#define MCUPM_PWR_CTRL_MASK GENMASK(3, 0)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE */
+#define MCUPM_BUCK_NORMAL_MODE U(0) /* default */
+#define MCUPM_BUCK_LP_MODE U(1)
+#define MCUPM_BUCK_OFF_MODE U(2)
+#define NF_MCUPM_BUCK_MODE U(3)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE */
+#define MCUPM_ARMPLL_ON U(0) /* default */
+#define MCUPM_ARMPLL_GATING U(1)
+#define MCUPM_ARMPLL_OFF U(2)
+#define NF_MCUPM_ARMPLL_MODE U(3)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA */
+#define MCUPM_TASK_UNINIT U(0)
+#define MCUPM_TASK_INIT U(1)
+#define MCUPM_TASK_INIT_FINISH U(2)
+#define MCUPM_TASK_WAIT U(3)
+#define MCUPM_TASK_RUN U(4)
+#define MCUPM_TASK_PAUSE U(5)
+
+#define SSPM_MBOX_3_BASE U(0x0c55fce0)
+
+#define MCDI_NOT_INIT 0
+#define MCDI_INIT_1 1
+#define MCDI_INIT_2 2
+#define MCDI_INIT_DONE 3
+
+static int mcdi_init_status __section("tzfw_coherent_mem");
+
+static inline uint32_t mcdi_mbox_read(uint32_t id)
+{
+ return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2));
+}
+
+static inline void mcdi_mbox_write(uint32_t id, uint32_t val)
+{
+ mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val);
+}
+
+static void mtk_mcupm_pwr_ctrl_setting(uint32_t dev)
+{
+ mcdi_mbox_write(APMCU_MCUPM_MBOX_PWR_CTRL_EN, dev);
+}
+
+static void mtk_set_mcupm_pll_mode(uint32_t mode)
+{
+ if (mode < NF_MCUPM_ARMPLL_MODE) {
+ mcdi_mbox_write(APMCU_MCUPM_MBOX_ARMPLL_MODE, mode);
+ }
+}
+
+static void mtk_set_mcupm_buck_mode(uint32_t mode)
+{
+ if (mode < NF_MCUPM_BUCK_MODE) {
+ mcdi_mbox_write(APMCU_MCUPM_MBOX_BUCK_MODE, mode);
+ }
+}
+
+static int mtk_mcupm_is_ready(void)
+{
+ unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
+
+ return (sta == MCUPM_TASK_WAIT) || (sta == MCUPM_TASK_INIT_FINISH);
+}
+
+static int mcdi_init_1(void)
+{
+ unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
+
+ if (sta != MCUPM_TASK_INIT) {
+ return -1;
+ }
+
+ mtk_set_mcupm_pll_mode(MCUPM_ARMPLL_OFF);
+ mtk_set_mcupm_buck_mode(MCUPM_BUCK_OFF_MODE);
+
+ mtk_mcupm_pwr_ctrl_setting(
+ MCUPM_MCUSYS_CTRL |
+ MCUPM_BUCK_CTRL |
+ MCUPM_ARMPLL_CTRL);
+
+ mcdi_mbox_write(APMCU_MCUPM_MBOX_AP_READY, 1);
+
+ return 0;
+}
+
+static int mcdi_init_2(void)
+{
+ return mtk_mcupm_is_ready() ? 0 : -1;
+}
+
+int mcdi_try_init(void)
+{
+ if (mcdi_init_status == MCDI_INIT_DONE) {
+ return 0;
+ }
+
+ if (mcdi_init_status == MCDI_NOT_INIT) {
+ mcdi_init_status = MCDI_INIT_1;
+ }
+
+ if (mcdi_init_status == MCDI_INIT_1 && mcdi_init_1() == 0) {
+ mcdi_init_status = MCDI_INIT_2;
+ }
+
+ if (mcdi_init_status == MCDI_INIT_2 && mcdi_init_2() == 0) {
+ mcdi_init_status = MCDI_INIT_DONE;
+ }
+
+ return (mcdi_init_status == MCDI_INIT_DONE) ? 0 : mcdi_init_status;
+}
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.h b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.h
new file mode 100644
index 0000000..f3545aa
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_MCDI_H
+#define MT_MCDI_H
+
+int mcdi_try_init(void);
+
+#endif /* MT_MCDI_H */
diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic.c b/plat/mediatek/mt8192/drivers/pmic/pmic.c
new file mode 100644
index 0000000..cca4413
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/pmic/pmic.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <pmic.h>
+#include <pmic_wrap_init.h>
+
+void pmic_power_off(void)
+{
+ pwrap_write(PMIC_PWRHOLD, 0x0);
+}
diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic.h b/plat/mediatek/mt8192/drivers/pmic/pmic.h
new file mode 100644
index 0000000..aac22af
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/pmic/pmic.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_H
+#define PMIC_H
+
+#define PMIC_PWRHOLD 0xa08
+
+/* external API */
+void pmic_power_off(void);
+
+#endif /* PMIC_H */
diff --git a/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h
new file mode 100644
index 0000000..ae892ed
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/pmic/pmic_wrap_init.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <stdint.h>
+
+#include "platform_def.h"
+
+/* external API */
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+
+static struct mt8192_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+/* PMIC_WRAP registers */
+struct mt8192_pmic_wrap_regs {
+ uint32_t init_done;
+ uint32_t reserved[799];
+ uint32_t wacs2_cmd;
+ uint32_t wacs2_wdata;
+ uint32_t reserved1[3];
+ uint32_t wacs2_rdata;
+ uint32_t reserved2[3];
+ uint32_t wacs2_vldclr;
+ uint32_t wacs2_sta;
+};
+
+#define GET_WACS_FSM(x) ((x >> 1) & 0x7)
+
+/* macro for SWINF_FSM */
+#define SWINF_FSM_IDLE (0x00)
+#define SWINF_FSM_REQ (0x02)
+#define SWINF_FSM_WFDLE (0x04)
+#define SWINF_FSM_WFVLDCLR (0x06)
+#define SWINF_INIT_DONE (0x01)
+
+/* timeout setting */
+#define PWRAP_READ_US 1000
+#define PWRAP_WAIT_IDLE_US 1000
+
+/* error information flag */
+enum pwrap_errno {
+ E_PWR_INVALID_ARG = 1,
+ E_PWR_INVALID_RW = 2,
+ E_PWR_INVALID_ADDR = 3,
+ E_PWR_INVALID_WDAT = 4,
+ E_PWR_INVALID_OP_MANUAL = 5,
+ E_PWR_NOT_IDLE_STATE = 6,
+ E_PWR_NOT_INIT_DONE = 7,
+ E_PWR_NOT_INIT_DONE_READ = 8,
+ E_PWR_WAIT_IDLE_TIMEOUT = 9,
+ E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
+ E_PWR_INIT_SIDLY_FAIL = 11,
+ E_PWR_RESET_TIMEOUT = 12,
+ E_PWR_TIMEOUT = 13,
+ E_PWR_INIT_RESET_SPI = 20,
+ E_PWR_INIT_SIDLY = 21,
+ E_PWR_INIT_REG_CLOCK = 22,
+ E_PWR_INIT_ENABLE_PMIC = 23,
+ E_PWR_INIT_DIO = 24,
+ E_PWR_INIT_CIPHER = 25,
+ E_PWR_INIT_WRITE_TEST = 26,
+ E_PWR_INIT_ENABLE_CRC = 27,
+ E_PWR_INIT_ENABLE_DEWRAP = 28,
+ E_PWR_INIT_ENABLE_EVENT = 29,
+ E_PWR_READ_TEST_FAIL = 30,
+ E_PWR_WRITE_TEST_FAIL = 31,
+ E_PWR_SWITCH_DIO = 32
+};
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_common.h b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_common.h
new file mode 100644
index 0000000..92c71bc
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_common.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_PTP3_H
+#define MTK_PTP3_H
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+/************************************************
+ * BIT Operation and REG r/w
+ ************************************************/
+#define ptp3_read(addr) mmio_read_32((uintptr_t)addr)
+#define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val)
+
+/************************************************
+ * CPU info
+ ************************************************/
+#define NR_PTP3_CFG1_CPU U(8)
+#define PTP3_CFG1_CPU_START_ID U(0)
+#define PTP3_CFG1_MASK 0x00100000
+
+#define NR_PTP3_CFG2_CPU U(4)
+#define PTP3_CFG2_CPU_START_ID U(4)
+
+#define NR_PTP3_CFG3_CPU U(4)
+#define PTP3_CFG3_CPU_START_ID U(4)
+
+/************************************************
+ * config enum
+ ************************************************/
+enum PTP3_CFG {
+ PTP3_CFG_ADDR,
+ PTP3_CFG_VALUE,
+ NR_PTP3_CFG,
+};
+
+/************************************
+ * prototype
+ ************************************/
+/* init trigger for ptp3 feature */
+extern void ptp3_init(unsigned int core);
+extern void ptp3_deinit(unsigned int core);
+
+#endif /* MTK_PTP3_H */
diff --git a/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c
new file mode 100644
index 0000000..f1d8493
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved. \
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "mtk_ptp3_common.h"
+
+/************************************************
+ * Central control: turn on sysPi protection
+ ************************************************/
+static unsigned int ptp3_cfg1[NR_PTP3_CFG1_CPU][NR_PTP3_CFG] = {
+ {0x0C530610, 0x110842},
+ {0x0C530E10, 0x110842},
+ {0x0C531610, 0x110842},
+ {0x0C531E10, 0x110842},
+ {0x0C532610, 0x110842},
+ {0x0C532E10, 0x110842},
+ {0x0C533610, 0x110842},
+ {0x0C533E10, 0x110842}
+};
+static unsigned int ptp3_cfg2[NR_PTP3_CFG2_CPU][NR_PTP3_CFG] = {
+ {0x0C53B830, 0x68000},
+ {0x0C53BA30, 0x68000},
+ {0x0C53BC30, 0x68000},
+ {0x0C53BE30, 0x68000}
+};
+static unsigned int ptp3_cfg3[NR_PTP3_CFG3_CPU][NR_PTP3_CFG] = {
+ {0x0C532480, 0x7C607C6},
+ {0x0C532C80, 0x7C607C6},
+ {0x0C533480, 0x7C607C6},
+ {0x0C533C80, 0x7C607C6}
+};
+
+/************************************************
+ * API
+ ************************************************/
+void ptp3_init(unsigned int core)
+{
+ unsigned int _core;
+
+ /* Apply ptp3_cfg1 for core 0 to 7 */
+ if (core < NR_PTP3_CFG1_CPU) {
+ /* update ptp3_cfg1 */
+ ptp3_write(
+ ptp3_cfg1[core][PTP3_CFG_ADDR],
+ ptp3_cfg1[core][PTP3_CFG_VALUE]);
+ }
+
+ /* Apply ptp3_cfg2 for core 4 to 7 */
+ if (core >= PTP3_CFG2_CPU_START_ID) {
+ _core = core - PTP3_CFG2_CPU_START_ID;
+
+ if (_core < NR_PTP3_CFG2_CPU) {
+ /* update ptp3_cfg2 */
+ ptp3_write(
+ ptp3_cfg2[_core][PTP3_CFG_ADDR],
+ ptp3_cfg2[_core][PTP3_CFG_VALUE]);
+ }
+ }
+
+ /* Apply ptp3_cfg3 for core 4 to 7 */
+ if (core >= PTP3_CFG3_CPU_START_ID) {
+ _core = core - PTP3_CFG3_CPU_START_ID;
+
+ if (_core < NR_PTP3_CFG3_CPU) {
+ /* update ptp3_cfg3 */
+ ptp3_write(
+ ptp3_cfg3[_core][PTP3_CFG_ADDR],
+ ptp3_cfg3[_core][PTP3_CFG_VALUE]);
+ }
+ }
+}
+
+void ptp3_deinit(unsigned int core)
+{
+ if (core < NR_PTP3_CFG1_CPU) {
+ /* update ptp3_cfg1 */
+ ptp3_write(
+ ptp3_cfg1[core][PTP3_CFG_ADDR],
+ ptp3_cfg1[core][PTP3_CFG_VALUE] &
+ ~PTP3_CFG1_MASK);
+ }
+}
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.c b/plat/mediatek/mt8192/drivers/rtc/rtc.c
new file mode 100644
index 0000000..124bc8f
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/rtc/rtc.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <rtc.h>
+
+
+static void RTC_Config_Interface(uint32_t addr, uint16_t data,
+ uint16_t mask, uint16_t shift)
+{
+ uint16_t pmic_reg;
+
+ pmic_reg = RTC_Read(addr);
+
+ pmic_reg &= ~(mask << shift);
+ pmic_reg |= (data << shift);
+
+ RTC_Write(addr, pmic_reg);
+}
+
+static int32_t rtc_disable_2sec_reboot(void)
+{
+ uint16_t reboot;
+
+ reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) &
+ ~RTC_BBPU_AUTO_PDN_SEL;
+ RTC_Write(RTC_AL_SEC, reboot);
+
+ return RTC_Write_Trigger();
+}
+
+static int32_t rtc_enable_k_eosc(void)
+{
+ uint16_t alm_dow, alm_sec;
+ int16_t ret;
+
+ /* Turning on eosc cali mode clock */
+ RTC_Config_Interface(PMIC_RG_SCK_TOP_CKPDN_CON0_CLR, 1,
+ PMIC_RG_RTC_EOSC32_CK_PDN_MASK,
+ PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT);
+
+ alm_sec = RTC_Read(RTC_AL_SEC) & (~RTC_LPD_OPT_MASK);
+ RTC_Write(RTC_AL_SEC, alm_sec);
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return 0;
+ }
+
+ RTC_Write(RTC_CON, RTC_LPD_EN);
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return 0;
+ }
+
+ RTC_Write(RTC_CON, RTC_LPD_RST);
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return 0;
+ }
+
+ RTC_Write(RTC_CON, RTC_LPD_EN);
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return 0;
+ }
+
+ RTC_Write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
+ RTC_Write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return 0;
+ }
+
+ /* set RTC EOSC calibration period = 8sec */
+ alm_dow = (RTC_Read(RTC_AL_DOW) & (~RTC_RG_EOSC_CALI_TD_MASK)) |
+ RTC_RG_EOSC_CALI_TD_8SEC;
+ RTC_Write(RTC_AL_DOW, alm_dow);
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return 0;
+ }
+
+ RTC_Write(RTC_BBPU,
+ RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return 0;
+ }
+
+ /* Enable K EOSC mode :use solution1 of eosc cali to fix mt6359p 32K*/
+ RTC_Write(RTC_AL_YEA, (((RTC_Read(RTC_AL_YEA) | RTC_K_EOSC_RSV_0)
+ & (~RTC_K_EOSC_RSV_1)) | (RTC_K_EOSC_RSV_2)));
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return 0;
+ }
+
+ INFO("[RTC] RTC_enable_k_eosc\n");
+
+ return 1;
+}
+
+void rtc_power_off_sequence(void)
+{
+ uint16_t bbpu;
+ int16_t ret;
+
+ ret = rtc_disable_2sec_reboot();
+ if (ret == 0) {
+ return;
+ }
+
+ ret = rtc_enable_k_eosc();
+ if (ret == 0) {
+ return;
+ }
+
+ bbpu = RTC_BBPU_KEY | RTC_BBPU_PWREN;
+
+ if (Writeif_unlock() != 0) {
+ RTC_Write(RTC_BBPU,
+ bbpu | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR);
+ RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW);
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return;
+ }
+ mdelay(1);
+
+ bbpu = RTC_Read(RTC_BBPU);
+
+ if (((bbpu & RTC_BBPU_RESET_ALARM) > 0) ||
+ ((bbpu & RTC_BBPU_RESET_SPAR) > 0)) {
+ INFO("[RTC] timeout\n");
+ }
+
+ bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
+ RTC_Write(RTC_BBPU, bbpu);
+ ret = RTC_Write_Trigger();
+ if (ret == 0) {
+ return;
+ }
+ }
+}
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.h b/plat/mediatek/mt8192/drivers/rtc/rtc.h
new file mode 100644
index 0000000..419bfe4
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/rtc/rtc.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+/* RTC registers */
+enum {
+ RTC_BBPU = 0x0588,
+ RTC_IRQ_STA = 0x058A,
+ RTC_IRQ_EN = 0x058C,
+ RTC_CII_EN = 0x058E
+};
+
+enum {
+ RTC_AL_SEC = 0x05A0,
+ RTC_AL_MIN = 0x05A2,
+ RTC_AL_HOU = 0x05A4,
+ RTC_AL_DOM = 0x05A6,
+ RTC_AL_DOW = 0x05A8,
+ RTC_AL_MTH = 0x05AA,
+ RTC_AL_YEA = 0x05AC,
+ RTC_AL_MASK = 0x0590
+};
+
+enum {
+ RTC_OSC32CON = 0x05AE,
+ RTC_CON = 0x05C4,
+ RTC_WRTGR = 0x05C2
+};
+
+enum {
+ RTC_POWERKEY1 = 0x05B0,
+ RTC_POWERKEY2 = 0x05B2
+};
+
+enum {
+ RTC_POWERKEY1_KEY = 0xA357,
+ RTC_POWERKEY2_KEY = 0x67D2
+};
+
+enum {
+ RTC_PDN1 = 0x05B4,
+ RTC_PDN2 = 0x05B6,
+ RTC_SPAR0 = 0x05B8,
+ RTC_SPAR1 = 0x05BA,
+ RTC_PROT = 0x05BC,
+ RTC_DIFF = 0x05BE,
+ RTC_CALI = 0x05C0
+};
+
+enum {
+ RTC_OSC32CON_UNLOCK1 = 0x1A57,
+ RTC_OSC32CON_UNLOCK2 = 0x2B68
+};
+
+enum {
+ RTC_LPD_EN = 0x0406,
+ RTC_LPD_RST = 0x040E
+};
+
+enum {
+ RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
+ RTC_LPD_OPT_EOSC_LPD = 1U << 13,
+ RTC_LPD_OPT_XOSC_LPD = 2U << 13,
+ RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
+};
+
+#define RTC_LPD_OPT_MASK (3U << 13)
+
+enum {
+ RTC_PROT_UNLOCK1 = 0x586A,
+ RTC_PROT_UNLOCK2 = 0x9136
+};
+
+enum {
+ RTC_BBPU_PWREN = 1U << 0,
+ RTC_BBPU_SPAR_SW = 1U << 1,
+ RTC_BBPU_RESET_SPAR = 1U << 2,
+ RTC_BBPU_RESET_ALARM = 1U << 3,
+ RTC_BBPU_CLRPKY = 1U << 4,
+ RTC_BBPU_RELOAD = 1U << 5,
+ RTC_BBPU_CBUSY = 1U << 6
+};
+
+enum {
+ RTC_AL_MASK_SEC = 1U << 0,
+ RTC_AL_MASK_MIN = 1U << 1,
+ RTC_AL_MASK_HOU = 1U << 2,
+ RTC_AL_MASK_DOM = 1U << 3,
+ RTC_AL_MASK_DOW = 1U << 4,
+ RTC_AL_MASK_MTH = 1U << 5,
+ RTC_AL_MASK_YEA = 1U << 6
+};
+
+enum {
+ RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
+ RTC_BBPU_2SEC_CK_SEL = 1U << 7,
+ RTC_BBPU_2SEC_EN = 1U << 8,
+ RTC_BBPU_2SEC_MODE = 0x3 << 9,
+ RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
+ RTC_BBPU_2SEC_STAT_STA = 1U << 12
+};
+
+enum {
+ RTC_BBPU_KEY = 0x43 << 8
+};
+
+enum {
+ RTC_EMBCK_SRC_SEL = 1 << 8,
+ RTC_EMBCK_SEL_MODE = 3 << 6,
+ RTC_XOSC32_ENB = 1 << 5,
+ RTC_REG_XOSC32_ENB = 1 << 15
+};
+
+enum {
+ RTC_K_EOSC_RSV_0 = 1 << 8,
+ RTC_K_EOSC_RSV_1 = 1 << 9,
+ RTC_K_EOSC_RSV_2 = 1 << 10
+};
+
+enum {
+ RTC_RG_EOSC_CALI_TD_1SEC = 3 << 5,
+ RTC_RG_EOSC_CALI_TD_2SEC = 4 << 5,
+ RTC_RG_EOSC_CALI_TD_4SEC = 5 << 5,
+ RTC_RG_EOSC_CALI_TD_8SEC = 6 << 5,
+ RTC_RG_EOSC_CALI_TD_16SEC = 7 << 5,
+ RTC_RG_EOSC_CALI_TD_MASK = 7 << 5
+};
+
+/* PMIC TOP Register Definition */
+enum {
+ PMIC_RG_TOP_CON = 0x0020,
+ PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
+ PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
+ PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
+ PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
+ PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
+ PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
+};
+
+/* PMIC SCK Register Definition */
+enum {
+ PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x0514,
+ PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x0516,
+ PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x0518,
+ PMIC_RG_EOSC_CALI_CON0 = 0x53A
+};
+
+enum {
+ PMIC_EOSC_CALI_START_ADDR = 0x53A
+};
+
+enum {
+ PMIC_EOSC_CALI_START_MASK = 0x1,
+ PMIC_EOSC_CALI_START_SHIFT = 0
+};
+
+/* PMIC DCXO Register Definition */
+enum {
+ PMIC_RG_DCXO_CW00 = 0x0788,
+ PMIC_RG_DCXO_CW02 = 0x0790,
+ PMIC_RG_DCXO_CW08 = 0x079C,
+ PMIC_RG_DCXO_CW09 = 0x079E,
+ PMIC_RG_DCXO_CW09_CLR = 0x07A2,
+ PMIC_RG_DCXO_CW10 = 0x07A4,
+ PMIC_RG_DCXO_CW12 = 0x07A8,
+ PMIC_RG_DCXO_CW13 = 0x07AA,
+ PMIC_RG_DCXO_CW15 = 0x07AE,
+ PMIC_RG_DCXO_CW19 = 0x07B6,
+};
+
+enum {
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1,
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3,
+ PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1,
+ PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2,
+ PMIC_RG_EOSC_CALI_TD_MASK = 0x7,
+ PMIC_RG_EOSC_CALI_TD_SHIFT = 5,
+ PMIC_RG_XO_EN32K_MAN_MASK = 0x1,
+ PMIC_RG_XO_EN32K_MAN_SHIFT = 0
+};
+
+/* external API */
+uint16_t RTC_Read(uint32_t addr);
+void RTC_Write(uint32_t addr, uint16_t data);
+int32_t rtc_busy_wait(void);
+int32_t RTC_Write_Trigger(void);
+int32_t Writeif_unlock(void);
+void rtc_power_off_sequence(void);
+
+#endif /* RTC_H */
diff --git a/plat/mediatek/mt8192/drivers/spmc/mtspmc.c b/plat/mediatek/mt8192/drivers/spmc/mtspmc.c
new file mode 100644
index 0000000..7ccebd6
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spmc/mtspmc.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mcucfg.h>
+#include <mtspmc.h>
+#include <mtspmc_private.h>
+
+
+void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu)
+{
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
+}
+
+void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu)
+{
+ mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
+}
+
+void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr)
+{
+ assert(cluster == 0U);
+
+ mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr);
+}
+
+uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu)
+{
+ assert(cluster == 0U);
+
+ return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR));
+}
+
+void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64)
+{
+ uint32_t reg;
+
+ assert(cluster == 0U);
+
+ reg = per_cluster(cluster, MCUCFG_INITARCH);
+
+ if (arm64) {
+ mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
+ } else {
+ mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
+ }
+}
+
+/**
+ * Return subsystem's power state.
+ *
+ * @mask: mask to SPM_CPU_PWR_STATUS to query the power state
+ * of one subsystem.
+ * RETURNS:
+ * 0 (the subsys was powered off)
+ * 1 (the subsys was powered on)
+ */
+bool spm_get_powerstate(uint32_t mask)
+{
+ return (mmio_read_32(SPM_CPU_PWR_STATUS) & mask) != 0U;
+}
+
+bool spm_get_cluster_powerstate(uint32_t cluster)
+{
+ assert(cluster == 0U);
+
+ return spm_get_powerstate(MP0_CPUTOP);
+}
+
+bool spm_get_cpu_powerstate(uint32_t cluster, uint32_t cpu)
+{
+ uint32_t mask = BIT(cpu);
+
+ assert(cluster == 0U);
+
+ return spm_get_powerstate(mask);
+}
+
+int spmc_init(void)
+{
+ INFO("SPM: enable CPC mode\n");
+
+ mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN);
+
+ mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B);
+
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(1));
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(2));
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(3));
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(4));
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(5));
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(6));
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(7));
+
+ mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG);
+ mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG);
+ mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG);
+
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE);
+
+ return 0;
+}
+
+/**
+ * Power on a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered on
+ * @cpu: the CPU ID of the CPU which to be powered on
+ */
+void spm_poweron_cpu(uint32_t cluster, uint32_t cpu)
+{
+ /* set to 0 after BIG VPROC bulk on & before B-core power on seq. */
+ if (cpu >= 4U) {
+ mmio_write_32(DREQ20_BIG_VPROC_ISO, 0U);
+ }
+
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN);
+ mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
+
+ while (!spm_get_cpu_powerstate(cluster, cpu)) {
+ }
+
+ mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_ALL_PWR_CTRL_EN);
+
+ /* Enable Big CPU Last PC */
+ if (cpu >= 4U) {
+ mmio_clrbits_32(LAST_PC_REG(cpu), BIT(3));
+ }
+}
+
+/**
+ * Power off a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered off
+ * @cpu: the CPU ID of the CPU which to be powered off
+ */
+void spm_poweroff_cpu(uint32_t cluster, uint32_t cpu)
+{
+ /* Set mp0_spmc_pwr_on_cpuX = 0 */
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
+}
+
+/**
+ * Power off a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered off
+ */
+void spm_poweroff_cluster(uint32_t cluster)
+{
+ /* No need to power on/off cluster on single cluster platform */
+ assert(false);
+}
+
+/**
+ * Power on a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered on
+ */
+void spm_poweron_cluster(uint32_t cluster)
+{
+ /* No need to power on/off cluster on single cluster platform */
+ assert(false);
+}
diff --git a/plat/mediatek/mt8192/drivers/spmc/mtspmc.h b/plat/mediatek/mt8192/drivers/spmc/mtspmc.h
new file mode 100644
index 0000000..7ed2e62
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spmc/mtspmc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_H
+#define MTSPMC_H
+
+#include <stdint.h>
+
+int spmc_init(void);
+
+void spm_poweron_cpu(uint32_t cluster, uint32_t cpu);
+void spm_poweroff_cpu(uint32_t cluster, uint32_t cpu);
+
+void spm_poweroff_cluster(uint32_t cluster);
+void spm_poweron_cluster(uint32_t cluster);
+
+bool spm_get_cpu_powerstate(uint32_t cluster, uint32_t cpu);
+bool spm_get_cluster_powerstate(uint32_t cluster);
+bool spm_get_powerstate(uint32_t mask);
+
+void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64);
+void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr);
+uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu);
+
+void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu);
+void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu);
+
+#endif /* MTSPMC_H */
diff --git a/plat/mediatek/mt8192/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8192/drivers/spmc/mtspmc_private.h
new file mode 100644
index 0000000..ad78295
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spmc/mtspmc_private.h
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_PRIVATE_H
+#define MTSPMC_PRIVATE_H
+
+#include <lib/utils_def.h>
+#include <platform_def.h>
+
+unsigned long read_cpuectlr(void);
+void write_cpuectlr(unsigned long cpuectlr);
+
+unsigned long read_cpupwrctlr_el1(void);
+void write_cpupwrctlr_el1(unsigned long cpuectlr);
+
+/*
+ * per_cpu/cluster helper
+ */
+struct per_cpu_reg {
+ unsigned int cluster_addr;
+ unsigned int cpu_stride;
+};
+
+#define per_cpu(cluster, cpu, reg) \
+ (reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
+
+#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
+
+#define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
+#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
+#define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs))
+
+/* === SPMC related registers */
+#define SPM_POWERON_CONFIG_EN SPM_REG(0x000)
+/* bit-fields of SPM_POWERON_CONFIG_EN */
+#define PROJECT_CODE (U(0xb16) << 16)
+#define BCLK_CG_EN BIT(0)
+
+#define SPM_PWR_STATUS SPM_REG(0x16c)
+#define SPM_PWR_STATUS_2ND SPM_REG(0x170)
+#define SPM_CPU_PWR_STATUS SPM_REG(0x174)
+
+/* bit-fields of SPM_PWR_STATUS */
+#define MD BIT(0)
+#define CONN BIT(1)
+#define DDRPHY BIT(2)
+#define DISP BIT(3)
+#define MFG BIT(4)
+#define ISP BIT(5)
+#define INFRA BIT(6)
+#define VDEC BIT(7)
+#define MP0_CPUTOP BIT(8)
+#define MP0_CPU0 BIT(9)
+#define MP0_CPU1 BIT(10)
+#define MP0_CPU2 BIT(11)
+#define MP0_CPU3 BIT(12)
+#define MCUSYS BIT(14)
+#define MP0_CPU4 BIT(15)
+#define MP0_CPU5 BIT(16)
+#define MP0_CPU6 BIT(17)
+#define MP0_CPU7 BIT(18)
+#define VEN BIT(21)
+
+/* === SPMC related registers */
+#define SPM_MCUSYS_PWR_CON MCUCFG_REG(0xd200)
+#define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204)
+#define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208)
+#define SPM_MP0_CPU1_PWR_CON MCUCFG_REG(0xd20c)
+#define SPM_MP0_CPU2_PWR_CON MCUCFG_REG(0xd210)
+#define SPM_MP0_CPU3_PWR_CON MCUCFG_REG(0xd214)
+#define SPM_MP0_CPU4_PWR_CON MCUCFG_REG(0xd218)
+#define SPM_MP0_CPU5_PWR_CON MCUCFG_REG(0xd21c)
+#define SPM_MP0_CPU6_PWR_CON MCUCFG_REG(0xd220)
+#define SPM_MP0_CPU7_PWR_CON MCUCFG_REG(0xd224)
+
+/* bit fields of SPM_*_PWR_CON */
+#define PWR_ON_ACK BIT(31)
+#define VPROC_EXT_OFF BIT(7)
+#define DORMANT_EN BIT(6)
+#define RESETPWRON_CONFIG BIT(5)
+#define PWR_CLK_DIS BIT(4)
+#define PWR_ON BIT(2)
+#define PWR_RST_B BIT(0)
+
+/**** per_cpu registers for SPM_MP0_CPU?_PWR_CON */
+static const struct per_cpu_reg SPM_CPU_PWR[] = {
+ { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
+};
+
+/**** per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */
+static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
+ { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
+};
+
+/* === MCUCFG related registers */
+/* aa64naa32 */
+#define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4)
+/* reset vectors */
+#define MCUCFG_MP0_CLUSTER_CFG8 MCUCFG_REG(0xc900)
+#define MCUCFG_MP0_CLUSTER_CFG10 MCUCFG_REG(0xc908)
+#define MCUCFG_MP0_CLUSTER_CFG12 MCUCFG_REG(0xc910)
+#define MCUCFG_MP0_CLUSTER_CFG14 MCUCFG_REG(0xc918)
+#define MCUCFG_MP0_CLUSTER_CFG16 MCUCFG_REG(0xc920)
+#define MCUCFG_MP0_CLUSTER_CFG18 MCUCFG_REG(0xc928)
+#define MCUCFG_MP0_CLUSTER_CFG20 MCUCFG_REG(0xc930)
+#define MCUCFG_MP0_CLUSTER_CFG22 MCUCFG_REG(0xc938)
+
+/* MCUSYS DREQ BIG VPROC ISO control */
+#define DREQ20_BIG_VPROC_ISO MCUCFG_REG(0xad8c)
+
+/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG? */
+static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
+ { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
+};
+
+/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */
+static const struct per_cpu_reg MCUCFG_INITARCH[] = {
+ { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
+};
+
+#define MCUCFG_INITARCH_CPU_BIT(cpu) BIT(16U + cpu)
+#define LAST_PC_REG(cpu) (MCUCFG_REG(0x308) + (cpu * 0x800))
+
+/* === CPC control */
+#define MCUCFG_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
+#define MCUCFG_CPC_SPMC_PWR_STATUS MCUCFG_REG(0xa840)
+
+/* bit fields of CPC_FLOW_CTRL_CFG */
+#define CPC_CTRL_ENABLE BIT(16)
+#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
+#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu)
+
+/* bit fields of CPC_SPMC_PWR_STATUS */
+#define CORE_SPMC_PWR_ON_ACK GENMASK(15, 0)
+
+/* === APB Module infracfg_ao */
+#define INFRA_TOPAXI_PROTECTEN INFRACFG_AO_REG(0x0220)
+#define INFRA_TOPAXI_PROTECTEN_STA0 INFRACFG_AO_REG(0x0224)
+#define INFRA_TOPAXI_PROTECTEN_STA1 INFRACFG_AO_REG(0x0228)
+#define INFRA_TOPAXI_PROTECTEN_SET INFRACFG_AO_REG(0x02a0)
+#define INFRA_TOPAXI_PROTECTEN_CLR INFRACFG_AO_REG(0x02a4)
+#define INFRA_TOPAXI_PROTECTEN_1 INFRACFG_AO_REG(0x0250)
+#define INFRA_TOPAXI_PROTECTEN_STA0_1 INFRACFG_AO_REG(0x0254)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1 INFRACFG_AO_REG(0x0258)
+#define INFRA_TOPAXI_PROTECTEN_1_SET INFRACFG_AO_REG(0x02a8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR INFRACFG_AO_REG(0x02ac)
+
+/* bit fields of INFRA_TOPAXI_PROTECTEN */
+#define MP0_SPMC_PROT_STEP1_0_MASK BIT(12)
+#define MP0_SPMC_PROT_STEP1_1_MASK (BIT(26) | BIT(12))
+
+/* === SPARK */
+#define VOLTAGE_04 U(0x40)
+#define VOLTAGE_05 U(0x60)
+
+#define PTP3_CPU0_SPMC_SW_CFG MCUCFG_REG(0x200)
+#define CPU0_ILDO_CONTROL5 MCUCFG_REG(0x334)
+#define CPU0_ILDO_CONTROL8 MCUCFG_REG(0x340)
+
+/* bit fields of CPU0_ILDO_CONTROL5 */
+#define ILDO_RET_VOSEL GENMASK(7, 0)
+
+/* bit fields of PTP3_CPU_SPMC_SW_CFG */
+#define SW_SPARK_EN BIT(0)
+
+/* bit fields of CPU0_ILDO_CONTROL8 */
+#define ILDO_BYPASS_B BIT(0)
+
+static const struct per_cpu_reg MCUCFG_SPARK[] = {
+ { .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
+};
+
+static const struct per_cpu_reg ILDO_CONTROL5[] = {
+ { .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
+};
+
+static const struct per_cpu_reg ILDO_CONTROL8[] = {
+ { .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
+};
+
+#endif /* MTSPMC_PRIVATE_H */
diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.c b/plat/mediatek/mt8192/drivers/timer/mt_timer.c
new file mode 100644
index 0000000..0860885
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/timer/mt_timer.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <lib/mmio.h>
+#include <mt_timer.h>
+#include <platform_def.h>
+
+
+uint64_t normal_time_base;
+uint64_t atf_time_base;
+
+void sched_clock_init(uint64_t normal_base, uint64_t atf_base)
+{
+ normal_time_base += normal_base;
+ atf_time_base = atf_base;
+}
+
+uint64_t sched_clock(void)
+{
+ uint64_t cval;
+ uint64_t rel_base;
+
+ rel_base = read_cntpct_el0() - atf_time_base;
+ cval = ((rel_base * 1000U) / SYS_COUNTER_FREQ_IN_MHZ)
+ - normal_time_base;
+ return cval;
+}
+
+void mt_systimer_init(void)
+{
+ /* Enable access in NS mode */
+ mmio_write_32(CNTWACR_REG, CNT_WRITE_ACCESS_CTL_MASK);
+ mmio_write_32(CNTRACR_REG, CNT_READ_ACCESS_CTL_MASK);
+}
diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.h b/plat/mediatek/mt8192/drivers/timer/mt_timer.h
new file mode 100644
index 0000000..b353177
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/timer/mt_timer.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_TIMER_H
+#define MT_TIMER_H
+
+#define SYSTIMER_BASE (0x10017000)
+#define CNTCR_REG (SYSTIMER_BASE + 0x0)
+#define CNTSR_REG (SYSTIMER_BASE + 0x4)
+#define CNTSYS_L_REG (SYSTIMER_BASE + 0x8)
+#define CNTSYS_H_REG (SYSTIMER_BASE + 0xc)
+#define CNTWACR_REG (SYSTIMER_BASE + 0x10)
+#define CNTRACR_REG (SYSTIMER_BASE + 0x14)
+
+#define TIEO_EN (1 << 3)
+#define COMP_15_EN (1 << 10)
+#define COMP_20_EN (1 << 11)
+#define COMP_25_EN (1 << 12)
+
+#define COMP_FEATURE_MASK (COMP_15_EN | COMP_20_EN | COMP_25_EN | TIEO_EN)
+#define COMP_15_MASK (COMP_15_EN)
+#define COMP_20_MASK (COMP_20_EN | TIEO_EN)
+#define COMP_25_MASK (COMP_20_EN | COMP_25_EN)
+
+#define CNT_WRITE_ACCESS_CTL_MASK (0x3FFFFF0U)
+#define CNT_READ_ACCESS_CTL_MASK (0x3FFFFFFU)
+
+void sched_clock_init(uint64_t normal_base, uint64_t atf_base);
+uint64_t sched_clock(void);
+void mt_systimer_init(void);
+
+#endif /* MT_TIMER_H */
diff --git a/plat/mediatek/mt8192/drivers/uart/uart.h b/plat/mediatek/mt8192/drivers/uart/uart.h
new file mode 100644
index 0000000..ac8b94d
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/uart/uart.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UART_H
+#define UART_H
+
+#include <platform_def.h>
+
+/* UART HW information */
+#define HW_SUPPORT_UART_PORTS 2
+#define DRV_SUPPORT_UART_PORTS 2
+
+/* console UART clock cg */
+#define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80)
+#define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84)
+#define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90)
+#define UART0_CLOCK_GATE_BIT (1U<<22)
+#define UART1_CLOCK_GATE_BIT (1U<<23)
+
+/* UART registers */
+#define UART_RBR(_baseaddr) (_baseaddr + 0x0)
+#define UART_THR(_baseaddr) (_baseaddr + 0x0)
+#define UART_IER(_baseaddr) (_baseaddr + 0x4)
+#define UART_IIR(_baseaddr) (_baseaddr + 0x8)
+#define UART_FCR(_baseaddr) (_baseaddr + 0x8)
+#define UART_LCR(_baseaddr) (_baseaddr + 0xc)
+#define UART_MCR(_baseaddr) (_baseaddr + 0x10)
+#define UART_LSR(_baseaddr) (_baseaddr + 0x14)
+#define UART_MSR(_baseaddr) (_baseaddr + 0x18)
+#define UART_SCR(_baseaddr) (_baseaddr + 0x1c)
+#define UART_DLL(_baseaddr) (_baseaddr + 0x0)
+#define UART_DLH(_baseaddr) (_baseaddr + 0x4)
+#define UART_EFR(_baseaddr) (_baseaddr + 0x8)
+#define UART_XON1(_baseaddr) (_baseaddr + 0x10)
+#define UART_XON2(_baseaddr) (_baseaddr + 0x14)
+#define UART_XOFF1(_baseaddr) (_baseaddr + 0x18)
+#define UART_XOFF2(_baseaddr) (_baseaddr + 0x1c)
+#define UART_AUTOBAUD(_baseaddr) (_baseaddr + 0x20)
+#define UART_HIGHSPEED(_baseaddr) (_baseaddr + 0x24)
+#define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr + 0x28)
+#define UART_SAMPLE_POINT(_baseaddr) (_baseaddr + 0x2c)
+#define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr + 0x30)
+#define UART_RATE_FIX_REG(_baseaddr) (_baseaddr + 0x34)
+#define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr + 0x38)
+#define UART_GUARD(_baseaddr) (_baseaddr + 0x3c)
+#define UART_ESCAPE_DAT(_baseaddr) (_baseaddr + 0x40)
+#define UART_ESCAPE_EN(_baseaddr) (_baseaddr + 0x44)
+#define UART_SLEEP_EN(_baseaddr) (_baseaddr + 0x48)
+#define UART_DMA_EN(_baseaddr) (_baseaddr + 0x4c)
+#define UART_RXTRI_AD(_baseaddr) (_baseaddr + 0x50)
+#define UART_FRACDIV_L(_baseaddr) (_baseaddr + 0x54)
+#define UART_FRACDIV_M(_baseaddr) (_baseaddr + 0x58)
+#define UART_FCR_RD(_baseaddr) (_baseaddr + 0x5C)
+#define UART_USB_RX_SEL(_baseaddr) (_baseaddr + 0xB0)
+#define UART_SLEEP_REQ(_baseaddr) (_baseaddr + 0xB4)
+#define UART_SLEEP_ACK(_baseaddr) (_baseaddr + 0xB8)
+#define UART_SPM_SEL(_baseaddr) (_baseaddr + 0xBC)
+#define UART_LCR_DLAB 0x0080
+#define UART_LCR_MODE_B 0x00bf
+
+enum uart_port_ID {
+ UART_PORT0 = 0,
+ UART_PORT1
+};
+
+struct mt_uart_register {
+ uint32_t dll;
+ uint32_t dlh;
+ uint32_t ier;
+ uint32_t lcr;
+ uint32_t mcr;
+ uint32_t fcr;
+ uint32_t lsr;
+ uint32_t scr;
+ uint32_t efr;
+ uint32_t highspeed;
+ uint32_t sample_count;
+ uint32_t sample_point;
+ uint32_t fracdiv_l;
+ uint32_t fracdiv_m;
+ uint32_t escape_en;
+ uint32_t guard;
+ uint32_t rx_sel;
+};
+
+struct mt_uart {
+ unsigned long base;
+ struct mt_uart_register registers;
+};
+
+/* external API */
+void mt_uart_save(void);
+void mt_uart_restore(void);
+void mt_console_uart_cg(int on);
+uint32_t mt_console_uart_cg_status(void);
+
+#endif /* __UART_H__ */
diff --git a/plat/mediatek/mt8192/include/mcucfg.h b/plat/mediatek/mt8192/include/mcucfg.h
new file mode 100644
index 0000000..046cf73
--- /dev/null
+++ b/plat/mediatek/mt8192/include/mcucfg.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MCUCFG_H
+#define MCUCFG_H
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#endif /* __ASSEMBLER__ */
+
+#include <platform_def.h>
+
+#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
+
+#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8))
+#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8))
+
+#define MP2_CPUCFG MCUCFG_REG(0x2208)
+
+#define MP2_CPU0_STANDBYWFE BIT(4)
+#define MP2_CPU1_STANDBYWFE BIT(5)
+
+#define MP0_CPUTOP_SPMC_CTL MCUCFG_REG(0x788)
+#define MP1_CPUTOP_SPMC_CTL MCUCFG_REG(0x78C)
+#define MP1_CPUTOP_SPMC_SRAM_CTL MCUCFG_REG(0x790)
+
+#define sw_spark_en BIT(0)
+#define sw_no_wait_for_q_channel BIT(1)
+#define sw_fsm_override BIT(2)
+#define sw_logic_pre1_pdb BIT(3)
+#define sw_logic_pre2_pdb BIT(4)
+#define sw_logic_pdb BIT(5)
+#define sw_iso BIT(6)
+#define sw_sram_sleepb (U(0x3F) << 7)
+#define sw_sram_isointb BIT(13)
+#define sw_clk_dis BIT(14)
+#define sw_ckiso BIT(15)
+#define sw_pd (U(0x3F) << 16)
+#define sw_hot_plug_reset BIT(22)
+#define sw_pwr_on_override_en BIT(23)
+#define sw_pwr_on BIT(24)
+#define sw_coq_dis BIT(25)
+#define logic_pdbo_all_off_ack BIT(26)
+#define logic_pdbo_all_on_ack BIT(27)
+#define logic_pre2_pdbo_all_on_ack BIT(28)
+#define logic_pre1_pdbo_all_on_ack BIT(29)
+
+
+#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \
+ (MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4)
+
+#define CPUSYS0_CPU0_SPMC_CTL MCUCFG_REG(0x1c30)
+#define CPUSYS0_CPU1_SPMC_CTL MCUCFG_REG(0x1c34)
+#define CPUSYS0_CPU2_SPMC_CTL MCUCFG_REG(0x1c38)
+#define CPUSYS0_CPU3_SPMC_CTL MCUCFG_REG(0x1c3C)
+
+#define CPUSYS1_CPU0_SPMC_CTL MCUCFG_REG(0x3c30)
+#define CPUSYS1_CPU1_SPMC_CTL MCUCFG_REG(0x3c34)
+#define CPUSYS1_CPU2_SPMC_CTL MCUCFG_REG(0x3c38)
+#define CPUSYS1_CPU3_SPMC_CTL MCUCFG_REG(0x3c3C)
+
+#define cpu_sw_spark_en BIT(0)
+#define cpu_sw_no_wait_for_q_channel BIT(1)
+#define cpu_sw_fsm_override BIT(2)
+#define cpu_sw_logic_pre1_pdb BIT(3)
+#define cpu_sw_logic_pre2_pdb BIT(4)
+#define cpu_sw_logic_pdb BIT(5)
+#define cpu_sw_iso BIT(6)
+#define cpu_sw_sram_sleepb BIT(7)
+#define cpu_sw_sram_isointb BIT(8)
+#define cpu_sw_clk_dis BIT(9)
+#define cpu_sw_ckiso BIT(10)
+#define cpu_sw_pd (U(0x1F) << 11)
+#define cpu_sw_hot_plug_reset BIT(16)
+#define cpu_sw_powr_on_override_en BIT(17)
+#define cpu_sw_pwr_on BIT(18)
+#define cpu_spark2ldo_allswoff BIT(19)
+#define cpu_pdbo_all_on_ack BIT(20)
+#define cpu_pre2_pdbo_allon_ack BIT(21)
+#define cpu_pre1_pdbo_allon_ack BIT(22)
+
+/* CPC related registers */
+#define CPC_MCUSYS_CPC_OFF_THRES MCUCFG_REG(0xa714)
+#define CPC_MCUSYS_PWR_CTRL MCUCFG_REG(0xa804)
+#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
+#define CPC_MCUSYS_LAST_CORE_REQ MCUCFG_REG(0xa818)
+#define CPC_MCUSYS_MP_LAST_CORE_RESP MCUCFG_REG(0xa81c)
+#define CPC_MCUSYS_LAST_CORE_RESP MCUCFG_REG(0xa824)
+#define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828)
+#define CPC_MCUSYS_CPU_ON_SW_HINT_SET MCUCFG_REG(0xa8a8)
+#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR MCUCFG_REG(0xa8ac)
+#define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00)
+#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE MCUCFG_REG(0xab04)
+#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE MCUCFG_REG(0xab08)
+#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE MCUCFG_REG(0xab0c)
+#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE MCUCFG_REG(0xab10)
+#define CPC_MCUSYS_TRACE_SEL MCUCFG_REG(0xab14)
+#define CPC_MCUSYS_TRACE_DATA MCUCFG_REG(0xab20)
+#define CPC_MCUSYS_CLUSTER_COUNTER MCUCFG_REG(0xab70)
+#define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74)
+
+#define SPARK2LDO MCUCFG_REG(0x2700)
+/* APB Module mcucfg */
+#define MP0_CA7_CACHE_CONFIG MCUCFG_REG(0x000)
+#define MP0_AXI_CONFIG MCUCFG_REG(0x02C)
+#define MP0_MISC_CONFIG0 MCUCFG_REG(0x030)
+#define MP0_MISC_CONFIG1 MCUCFG_REG(0x034)
+#define MP0_MISC_CONFIG2 MCUCFG_REG(0x038)
+#define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8))
+#define MP0_MISC_CONFIG3 MCUCFG_REG(0x03C)
+#define MP0_MISC_CONFIG9 MCUCFG_REG(0x054)
+#define MP0_CA7_MISC_CONFIG MCUCFG_REG(0x064)
+
+#define MP0_RW_RSVD0 MCUCFG_REG(0x06C)
+
+
+#define MP1_CA7_CACHE_CONFIG MCUCFG_REG(0x200)
+#define MP1_AXI_CONFIG MCUCFG_REG(0x22C)
+#define MP1_MISC_CONFIG0 MCUCFG_REG(0x230)
+#define MP1_MISC_CONFIG1 MCUCFG_REG(0x234)
+#define MP1_MISC_CONFIG2 MCUCFG_REG(0x238)
+#define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8))
+#define MP1_MISC_CONFIG3 MCUCFG_REG(0x23C)
+#define MP1_MISC_CONFIG9 MCUCFG_REG(0x254)
+#define MP1_CA7_MISC_CONFIG MCUCFG_REG(0x264)
+
+#define CCI_ADB400_DCM_CONFIG MCUCFG_REG(0x740)
+#define SYNC_DCM_CONFIG MCUCFG_REG(0x744)
+
+#define MP0_CLUSTER_CFG0 MCUCFG_REG(0xC8D0)
+
+#define MP0_SPMC MCUCFG_REG(0x788)
+#define MP1_SPMC MCUCFG_REG(0x78C)
+#define MP2_AXI_CONFIG MCUCFG_REG(0x220C)
+#define MP2_AXI_CONFIG_ACINACTM BIT(0)
+#define MP2_AXI_CONFIG_AINACTS BIT(4)
+
+#define MPx_AXI_CONFIG_ACINACTM BIT(4)
+#define MPx_AXI_CONFIG_AINACTS BIT(5)
+
+#define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28)
+
+#define MP0_CPU0_STANDBYWFE BIT(20)
+#define MP0_CPU1_STANDBYWFE BIT(21)
+#define MP0_CPU2_STANDBYWFE BIT(22)
+#define MP0_CPU3_STANDBYWFE BIT(23)
+
+#define MP1_CPU0_STANDBYWFE BIT(20)
+#define MP1_CPU1_STANDBYWFE BIT(21)
+#define MP1_CPU2_STANDBYWFE BIT(22)
+#define MP1_CPU3_STANDBYWFE BIT(23)
+
+#define CPUSYS0_SPARKVRETCNTRL MCUCFG_REG(0x1c00)
+#define CPUSYS0_SPARKEN MCUCFG_REG(0x1c04)
+#define CPUSYS0_AMUXSEL MCUCFG_REG(0x1c08)
+#define CPUSYS1_SPARKVRETCNTRL MCUCFG_REG(0x3c00)
+#define CPUSYS1_SPARKEN MCUCFG_REG(0x3c04)
+#define CPUSYS1_AMUXSEL MCUCFG_REG(0x3c08)
+
+#define MP2_PWR_RST_CTL MCUCFG_REG(0x2008)
+#define MP2_PTP3_CPUTOP_SPMC0 MCUCFG_REG(0x22A0)
+#define MP2_PTP3_CPUTOP_SPMC1 MCUCFG_REG(0x22A4)
+
+#define MP2_COQ MCUCFG_REG(0x22BC)
+#define MP2_COQ_SW_DIS BIT(0)
+
+#define MP2_CA15M_MON_SEL MCUCFG_REG(0x2400)
+#define MP2_CA15M_MON_L MCUCFG_REG(0x2404)
+
+#define CPUSYS2_CPU0_SPMC_CTL MCUCFG_REG(0x2430)
+#define CPUSYS2_CPU1_SPMC_CTL MCUCFG_REG(0x2438)
+#define CPUSYS2_CPU0_SPMC_STA MCUCFG_REG(0x2434)
+#define CPUSYS2_CPU1_SPMC_STA MCUCFG_REG(0x243C)
+
+#define MP0_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x068)
+#define MP1_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x268)
+#define BIG_DBG_PWR_CTRL MCUCFG_REG(0x75C)
+
+#define MP2_SW_RST_B BIT(0)
+#define MP2_TOPAON_APB_MASK BIT(1)
+
+#define B_SW_HOT_PLUG_RESET BIT(30)
+
+#define B_SW_PD_OFFSET 18U
+#define B_SW_PD (U(0x3f) << B_SW_PD_OFFSET)
+
+#define B_SW_SRAM_SLEEPB_OFFSET 12U
+#define B_SW_SRAM_SLEEPB (U(0x3f) << B_SW_SRAM_SLEEPB_OFFSET)
+
+#define B_SW_SRAM_ISOINTB BIT(9)
+#define B_SW_ISO BIT(8)
+#define B_SW_LOGIC_PDB BIT(7)
+#define B_SW_LOGIC_PRE2_PDB BIT(6)
+#define B_SW_LOGIC_PRE1_PDB BIT(5)
+#define B_SW_FSM_OVERRIDE BIT(4)
+#define B_SW_PWR_ON BIT(3)
+#define B_SW_PWR_ON_OVERRIDE_EN BIT(2)
+
+#define B_FSM_STATE_OUT_OFFSET (6U)
+#define B_FSM_STATE_OUT_MASK (U(0x1f) << B_FSM_STATE_OUT_OFFSET)
+#define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5)
+#define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4)
+#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3)
+#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2)
+
+#define B_FSM_OFF (0U << B_FSM_STATE_OUT_OFFSET)
+#define B_FSM_ON (1U << B_FSM_STATE_OUT_OFFSET)
+#define B_FSM_RET (2U << B_FSM_STATE_OUT_OFFSET)
+
+#ifndef __ASSEMBLER__
+/* cpu boot mode */
+enum {
+ MP0_CPUCFG_64BIT_SHIFT = 12U,
+ MP1_CPUCFG_64BIT_SHIFT = 28U,
+ MP0_CPUCFG_64BIT = U(0xf) << MP0_CPUCFG_64BIT_SHIFT,
+ MP1_CPUCFG_64BIT = U(0xf) << MP1_CPUCFG_64BIT_SHIFT
+};
+
+enum {
+ MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0U,
+ MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4U,
+ MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8U,
+ MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12U,
+ MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16U,
+
+ MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
+};
+
+enum {
+ MP1_AINACTS_SHIFT = 4U,
+ MP1_AINACTS = 1U << MP1_AINACTS_SHIFT
+};
+
+enum {
+ MP1_SW_CG_GEN_SHIFT = 12U,
+ MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT
+};
+
+enum {
+ MP1_L2RSTDISABLE_SHIFT = 14U,
+ MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT
+};
+#endif /* __ASSEMBLER__ */
+
+#endif /* MCUCFG_H */
diff --git a/plat/mediatek/mt8192/include/mt_gic_v3.h b/plat/mediatek/mt8192/include/mt_gic_v3.h
index 34ba8a7..c4ab44f 100644
--- a/plat/mediatek/mt8192/include/mt_gic_v3.h
+++ b/plat/mediatek/mt8192/include/mt_gic_v3.h
@@ -21,4 +21,7 @@
void mt_gic_rdistif_restore_all(void);
void gic_sgi_save_all(void);
void gic_sgi_restore_all(void);
+uint32_t mt_irq_get_pending(uint32_t irq);
+void mt_irq_set_pending(uint32_t irq);
+
#endif /* MT_GIC_V3_H */
diff --git a/plat/mediatek/mt8192/include/plat_mt_cirq.h b/plat/mediatek/mt8192/include/plat_mt_cirq.h
new file mode 100644
index 0000000..bb8b457
--- /dev/null
+++ b/plat/mediatek/mt8192/include/plat_mt_cirq.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MT_CIRQ_H
+#define PLAT_MT_CIRQ_H
+
+#include <stdint.h>
+
+enum {
+ IRQ_MASK_HEADER = 0xF1F1F1F1,
+ IRQ_MASK_FOOTER = 0xF2F2F2F2
+};
+
+struct mtk_irq_mask {
+ uint32_t header; /* for error checking */
+ uint32_t mask0;
+ uint32_t mask1;
+ uint32_t mask2;
+ uint32_t mask3;
+ uint32_t mask4;
+ uint32_t mask5;
+ uint32_t mask6;
+ uint32_t mask7;
+ uint32_t mask8;
+ uint32_t mask9;
+ uint32_t mask10;
+ uint32_t mask11;
+ uint32_t mask12;
+ uint32_t footer; /* for error checking */
+};
+
+/*
+ * Define hardware register
+ */
+
+#define SYS_CIRQ_BASE U(0x10204000)
+#define CIRQ_REG_NUM U(14)
+#define CIRQ_IRQ_NUM U(439)
+#define CIRQ_SPI_START U(64)
+#define MD_WDT_IRQ_BIT_ID U(110)
+
+#define CIRQ_STA_BASE (SYS_CIRQ_BASE + U(0x000))
+#define CIRQ_ACK_BASE (SYS_CIRQ_BASE + U(0x080))
+#define CIRQ_MASK_BASE (SYS_CIRQ_BASE + U(0x100))
+#define CIRQ_MASK_SET_BASE (SYS_CIRQ_BASE + U(0x180))
+#define CIRQ_MASK_CLR_BASE (SYS_CIRQ_BASE + U(0x200))
+#define CIRQ_SENS_BASE (SYS_CIRQ_BASE + U(0x280))
+#define CIRQ_SENS_SET_BASE (SYS_CIRQ_BASE + U(0x300))
+#define CIRQ_SENS_CLR_BASE (SYS_CIRQ_BASE + U(0x380))
+#define CIRQ_POL_BASE (SYS_CIRQ_BASE + U(0x400))
+#define CIRQ_POL_SET_BASE (SYS_CIRQ_BASE + U(0x480))
+#define CIRQ_POL_CLR_BASE (SYS_CIRQ_BASE + U(0x500))
+#define CIRQ_CON (SYS_CIRQ_BASE + U(0x600))
+
+/*
+ * Register placement
+ */
+#define CIRQ_CON_EN_BITS U(0)
+#define CIRQ_CON_EDGE_ONLY_BITS U(1)
+#define CIRQ_CON_FLUSH_BITS U(2)
+#define CIRQ_CON_SW_RST_BITS U(20)
+#define CIRQ_CON_EVENT_BITS U(31)
+#define CIRQ_CON_BITS_MASK U(0x7)
+
+/*
+ * Register setting
+ */
+#define CIRQ_CON_EN U(0x1)
+#define CIRQ_CON_EDGE_ONLY U(0x1)
+#define CIRQ_CON_FLUSH U(0x1)
+#define CIRQ_SW_RESET U(0x1)
+
+/*
+ * Define constant
+ */
+#define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31U) / 32U)
+
+#define MT_CIRQ_POL_NEG U(0)
+#define MT_CIRQ_POL_POS U(1)
+
+#define IRQ_TO_CIRQ_NUM(irq) ((irq) - (32U + CIRQ_SPI_START))
+#define CIRQ_TO_IRQ_NUM(cirq) ((cirq) + (32U + CIRQ_SPI_START))
+
+/* GIC sensitive */
+#define SENS_EDGE U(0x2)
+#define SENS_LEVEL U(0x1)
+
+
+/*
+ * Define function prototypes.
+ */
+int mt_cirq_test(void);
+void mt_cirq_dump_reg(void);
+int mt_irq_mask_restore(struct mtk_irq_mask *mask);
+int mt_irq_mask_all(struct mtk_irq_mask *mask);
+void mt_cirq_clone_gic(void);
+void mt_cirq_enable(void);
+void mt_cirq_flush(void);
+void mt_cirq_disable(void);
+void mt_irq_unmask_for_sleep_ex(uint32_t irq);
+void set_wakeup_sources(uint32_t *list, uint32_t num_of_events);
+void mt_cirq_sw_reset(void);
+
+struct cirq_reg {
+ uint32_t reg_num;
+ uint32_t used;
+ uint32_t mask;
+ uint32_t pol;
+ uint32_t sen;
+ uint32_t pending;
+ uint32_t the_link;
+};
+
+struct cirq_events {
+ uint32_t num_reg;
+ uint32_t spi_start;
+ uint32_t num_of_events;
+ uint32_t *wakeup_events;
+ struct cirq_reg table[CIRQ_REG_NUM];
+ uint32_t dist_base;
+ uint32_t cirq_base;
+ uint32_t used_reg_head;
+};
+
+#endif /* PLAT_MT_CIRQ_H */
diff --git a/plat/mediatek/mt8192/include/plat_mtk_lpm.h b/plat/mediatek/mt8192/include/plat_mtk_lpm.h
new file mode 100644
index 0000000..8ba8b93
--- /dev/null
+++ b/plat/mediatek/mt8192/include/plat_mtk_lpm.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MTK_LPM_H
+#define PLAT_MTK_LPM_H
+
+#include <lib/psci/psci.h>
+#include <lib/utils_def.h>
+
+#define MT_IRQ_REMAIN_MAX U(8)
+#define MT_IRQ_REMAIN_CAT_LOG BIT(31)
+
+struct mt_irqremain {
+ unsigned int count;
+ unsigned int irqs[MT_IRQ_REMAIN_MAX];
+ unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX];
+ unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX];
+};
+
+#define PLAT_RC_STATUS_READY BIT(0)
+#define PLAT_RC_STATUS_FEATURE_EN BIT(1)
+#define PLAT_RC_STATUS_UART_NONSLEEP BIT(31)
+
+struct mt_lpm_tz {
+ int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
+ int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
+
+ int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
+ int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
+
+ int (*pwr_cluster_on)(unsigned int cpu,
+ const psci_power_state_t *state);
+ int (*pwr_cluster_dwn)(unsigned int cpu,
+ const psci_power_state_t *state);
+
+ int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
+ int (*pwr_mcusys_on_finished)(unsigned int cpu,
+ const psci_power_state_t *state);
+ int (*pwr_mcusys_dwn)(unsigned int cpu,
+ const psci_power_state_t *state);
+};
+
+const struct mt_lpm_tz *mt_plat_cpu_pm_init(void);
+
+#endif /* PLAT_MTK_LPM_H */
diff --git a/plat/mediatek/mt8192/include/plat_pm.h b/plat/mediatek/mt8192/include/plat_pm.h
new file mode 100644
index 0000000..a2881ce
--- /dev/null
+++ b/plat/mediatek/mt8192/include/plat_pm.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PM_H
+#define PLAT_PM_H
+
+#include <lib/utils_def.h>
+
+#define MT_PLAT_PWR_STATE_CPU U(1)
+#define MT_PLAT_PWR_STATE_CLUSTER U(2)
+#define MT_PLAT_PWR_STATE_MCUSYS U(3)
+#define MT_PLAT_PWR_STATE_SUSPEND2IDLE U(8)
+#define MT_PLAT_PWR_STATE_SYSTEM_SUSPEND U(9)
+
+#define MTK_LOCAL_STATE_RUN U(0)
+#define MTK_LOCAL_STATE_RET U(1)
+#define MTK_LOCAL_STATE_OFF U(2)
+
+#define MTK_AFFLVL_CPU U(0)
+#define MTK_AFFLVL_CLUSTER U(1)
+#define MTK_AFFLVL_MCUSYS U(2)
+#define MTK_AFFLVL_SYSTEM U(3)
+
+#define IS_CLUSTER_OFF_STATE(s) \
+ is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
+#define IS_MCUSYS_OFF_STATE(s) \
+ is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS])
+#define IS_SYSTEM_SUSPEND_STATE(s) \
+ is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
+
+#define IS_PLAT_SUSPEND_ID(stateid)\
+ ((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE) \
+ || (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+
+#endif /* PLAT_PM_H */
diff --git a/plat/mediatek/mt8192/include/plat_sip_calls.h b/plat/mediatek/mt8192/include/plat_sip_calls.h
new file mode 100644
index 0000000..0e42322
--- /dev/null
+++ b/plat/mediatek/mt8192/include/plat_sip_calls.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_SIP_CALLS_H
+#define PLAT_SIP_CALLS_H
+
+/*******************************************************************************
+ * Plat SiP function constants
+ ******************************************************************************/
+#define MTK_PLAT_SIP_NUM_CALLS 0
+
+#endif /* PLAT_SIP_CALLS_H */
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index 5ff013e..3e44414 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -23,7 +23,24 @@
#define MTK_DEV_RNG1_SIZE 0x10000000
#define MTK_DEV_RNG2_BASE 0x0c000000
#define MTK_DEV_RNG2_SIZE 0x600000
+#define MTK_MCDI_SRAM_BASE 0x11B000
+#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
+#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
+#define GPIO_BASE (IO_PHYS + 0x00005000)
+#define SPM_BASE (IO_PHYS + 0x00006000)
+#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
+#define EMI_BASE (IO_PHYS + 0x00219000)
+#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
+#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
+#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
+#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
+#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
+#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
+#define IOCFG_LB_BASE (IO_PHYS + 0x01E70000)
+#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
+#define IOCFG_LT_BASE (IO_PHYS + 0x01F20000)
+#define IOCFG_TL_BASE (IO_PHYS + 0x01F30000)
/*******************************************************************************
* UART related constants
******************************************************************************/
@@ -57,11 +74,12 @@
******************************************************************************/
#define PLATFORM_STACK_SIZE 0x800
-#define PLAT_MAX_PWR_LVL U(2)
+#define PLAT_MAX_PWR_LVL U(3)
#define PLAT_MAX_RET_STATE U(1)
-#define PLAT_MAX_OFF_STATE U(2)
+#define PLAT_MAX_OFF_STATE U(9)
#define PLATFORM_SYSTEM_COUNT U(1)
+#define PLATFORM_MCUSYS_COUNT U(1)
#define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
diff --git a/plat/mediatek/mt8192/plat_mt_cirq.c b/plat/mediatek/mt8192/plat_mt_cirq.c
new file mode 100644
index 0000000..9002b7e
--- /dev/null
+++ b/plat/mediatek/mt8192/plat_mt_cirq.c
@@ -0,0 +1,552 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gic_common.h>
+#include <lib/mmio.h>
+
+#include <mt_gic_v3.h>
+#include <plat_mt_cirq.h>
+#include <platform_def.h>
+
+static struct cirq_events cirq_all_events = {
+ .spi_start = CIRQ_SPI_START,
+};
+static uint32_t already_cloned;
+/*
+ * mt_irq_mask_restore: restore all interrupts
+ * @mask: pointer to struct mtk_irq_mask for storing the original mask value.
+ * Return 0 for success; return negative values for failure.
+ * (This is ONLY used for the idle current measurement by the factory mode.)
+ */
+int mt_irq_mask_restore(struct mtk_irq_mask *mask)
+{
+ if (mask == NULL) {
+ return -1;
+ }
+ if (mask->header != IRQ_MASK_HEADER) {
+ return -1;
+ }
+ if (mask->footer != IRQ_MASK_FOOTER) {
+ return -1;
+ }
+
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x4),
+ mask->mask1);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x8),
+ mask->mask2);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0xc),
+ mask->mask3);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x10),
+ mask->mask4);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x14),
+ mask->mask5);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x18),
+ mask->mask6);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x1c),
+ mask->mask7);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x20),
+ mask->mask8);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x24),
+ mask->mask9);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x28),
+ mask->mask10);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x2c),
+ mask->mask11);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x30),
+ mask->mask12);
+ /* make sure dist changes happen */
+ dsb();
+
+ return 0;
+}
+
+/*
+ * mt_irq_mask_all: disable all interrupts
+ * @mask: pointer to struct mtk_irq_mask for storing the original mask value.
+ * Return 0 for success; return negative values for failure.
+ * (This is ONLY used for the idle current measurement by the factory mode.)
+ */
+int mt_irq_mask_all(struct mtk_irq_mask *mask)
+{
+ if (mask != NULL) {
+ /* for SPI */
+ mask->mask1 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x4));
+ mask->mask2 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x8));
+ mask->mask3 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0xc));
+ mask->mask4 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x10));
+ mask->mask5 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x14));
+ mask->mask6 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x18));
+ mask->mask7 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x1c));
+ mask->mask8 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x20));
+ mask->mask9 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x24));
+ mask->mask10 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x28));
+ mask->mask11 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x2c));
+ mask->mask12 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x30));
+
+ /* for SPI */
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x4),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x8),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0xC),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x10),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x14),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x18),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x1C),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x20),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x24),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x28),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x2c),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x30),
+ 0xFFFFFFFF);
+ /* make sure distributor changes happen */
+ dsb();
+
+ mask->header = IRQ_MASK_HEADER;
+ mask->footer = IRQ_MASK_FOOTER;
+
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+static uint32_t mt_irq_get_pol(uint32_t irq)
+{
+#ifdef CIRQ_WITH_POLARITY
+ uint32_t reg;
+ uint32_t base = INT_POL_CTL0;
+
+ if (irq < 32U) {
+ return 0;
+ }
+
+ reg = ((irq - 32U) / 32U);
+
+ return mmio_read_32(base + reg * 4U);
+#else
+ return 0;
+#endif
+}
+
+unsigned int mt_irq_get_sens(unsigned int irq)
+{
+ unsigned int config;
+
+ /*
+ * 2'b10 edge
+ * 2'b01 level
+ */
+ config = mmio_read_32(MT_GIC_BASE + GICD_ICFGR + (irq / 16U) * 4U);
+ config = (config >> (irq % 16U) * 2U) & 0x3;
+
+ return config;
+}
+
+static void collect_all_wakeup_events(void)
+{
+ unsigned int i;
+ uint32_t gic_irq;
+ uint32_t cirq;
+ uint32_t cirq_reg;
+ uint32_t cirq_offset;
+ uint32_t mask;
+ uint32_t pol_mask;
+ uint32_t irq_offset;
+ uint32_t irq_mask;
+
+ if ((cirq_all_events.wakeup_events == NULL) ||
+ cirq_all_events.num_of_events == 0U) {
+ return;
+ }
+
+ for (i = 0U; i < cirq_all_events.num_of_events; i++) {
+ if (cirq_all_events.wakeup_events[i] > 0U) {
+ gic_irq = cirq_all_events.wakeup_events[i];
+ cirq = gic_irq - cirq_all_events.spi_start - 32U;
+ cirq_reg = cirq / 32U;
+ cirq_offset = cirq % 32U;
+ mask = 0x1 << cirq_offset;
+ irq_offset = gic_irq % 32U;
+ irq_mask = 0x1 << irq_offset;
+ /*
+ * CIRQ default masks all
+ */
+ cirq_all_events.table[cirq_reg].mask |= mask;
+ /*
+ * CIRQ default pol is low
+ */
+ pol_mask = mt_irq_get_pol(
+ cirq_all_events.wakeup_events[i])
+ & irq_mask;
+ /*
+ * 0 means rising
+ */
+ if (pol_mask == 0U) {
+ cirq_all_events.table[cirq_reg].pol |= mask;
+ }
+ /*
+ * CIRQ could monitor edge/level trigger
+ * cirq register (0: edge, 1: level)
+ */
+ if (mt_irq_get_sens(cirq_all_events.wakeup_events[i])
+ == SENS_EDGE) {
+ cirq_all_events.table[cirq_reg].sen |= mask;
+ }
+
+ cirq_all_events.table[cirq_reg].used = 1U;
+ cirq_all_events.table[cirq_reg].reg_num = cirq_reg;
+ }
+ }
+}
+
+/*
+ * mt_cirq_set_pol: Set the polarity for the specified SYS_CIRQ number.
+ * @cirq_num: the SYS_CIRQ number to set
+ * @pol: polarity to set
+ * @return:
+ * 0: set pol success
+ * -1: cirq num is out of range
+ */
+#ifdef CIRQ_WITH_POLARITY
+static int mt_cirq_set_pol(uint32_t cirq_num, uint32_t pol)
+{
+ uint32_t base;
+ uint32_t bit = 1U << (cirq_num % 32U);
+
+ if (cirq_num >= CIRQ_IRQ_NUM) {
+ return -1;
+ }
+
+ if (pol == MT_CIRQ_POL_NEG) {
+ base = (cirq_num / 32U) * 4U + CIRQ_POL_CLR_BASE;
+ } else if (pol == MT_CIRQ_POL_POS) {
+ base = (cirq_num / 32U) * 4U + CIRQ_POL_SET_BASE;
+ } else {
+ return -1;
+ }
+
+ mmio_write_32(base, bit);
+ return 0;
+}
+#endif
+
+/*
+ * mt_cirq_mask: Mask the specified SYS_CIRQ.
+ * @cirq_num: the SYS_CIRQ number to mask
+ * @return:
+ * 0: mask success
+ * -1: cirq num is out of range
+ */
+static int mt_cirq_mask(uint32_t cirq_num)
+{
+ uint32_t bit = 1U << (cirq_num % 32U);
+
+ if (cirq_num >= CIRQ_IRQ_NUM) {
+ return -1;
+ }
+
+ mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_SET_BASE, bit);
+
+ return 0;
+}
+
+/*
+ * mt_cirq_unmask: Unmask the specified SYS_CIRQ.
+ * @cirq_num: the SYS_CIRQ number to unmask
+ * @return:
+ * 0: umask success
+ * -1: cirq num is out of range
+ */
+static int mt_cirq_unmask(uint32_t cirq_num)
+{
+ uint32_t bit = 1U << (cirq_num % 32U);
+
+ if (cirq_num >= CIRQ_IRQ_NUM) {
+ return -1;
+ }
+
+ mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_CLR_BASE, bit);
+
+ return 0;
+}
+
+uint32_t mt_irq_get_en(uint32_t irq)
+{
+ uint32_t addr, st, val;
+
+ addr = BASE_GICD_BASE + GICD_ISENABLER + (irq / 32U) * 4U;
+ st = mmio_read_32(addr);
+
+ val = (st >> (irq % 32U)) & 1U;
+
+ return val;
+}
+
+static void __cirq_fast_clone(void)
+{
+ struct cirq_reg *reg;
+ unsigned int i;
+
+ for (i = 0U; i < CIRQ_REG_NUM ; ++i) {
+ uint32_t cirq_bit;
+
+ reg = &cirq_all_events.table[i];
+
+ if (reg->used == 0U) {
+ continue;
+ }
+
+ mmio_write_32(CIRQ_SENS_CLR_BASE + (reg->reg_num * 4U),
+ reg->sen);
+
+ for (cirq_bit = 0U; cirq_bit < 32U; ++cirq_bit) {
+ uint32_t val, cirq_id;
+ uint32_t gic_id;
+#ifdef CIRQ_WITH_POLARITY
+ uint32_t gic_bit, pol;
+#endif
+ uint32_t en;
+
+ val = ((1U << cirq_bit) & reg->mask);
+
+ if (val == 0U) {
+ continue;
+ }
+
+ cirq_id = (reg->reg_num << 5U) + cirq_bit;
+ gic_id = CIRQ_TO_IRQ_NUM(cirq_id);
+#ifdef CIRQ_WITH_POLARITY
+ gic_bit = (0x1U << ((gic_id - 32U) % 32U));
+ pol = mt_irq_get_pol(gic_id) & gic_bit;
+ if (pol != 0U) {
+ mt_cirq_set_pol(cirq_id, MT_CIRQ_POL_NEG);
+ } else {
+ mt_cirq_set_pol(cirq_id, MT_CIRQ_POL_POS);
+ }
+#endif
+ en = mt_irq_get_en(gic_id);
+ if (en == 1U) {
+ mt_cirq_unmask(cirq_id);
+ } else {
+ mt_cirq_mask(cirq_id);
+ }
+ }
+ }
+}
+
+static void cirq_fast_clone(void)
+{
+ if (already_cloned == 0U) {
+ collect_all_wakeup_events();
+ already_cloned = 1U;
+ }
+ __cirq_fast_clone();
+}
+
+void set_wakeup_sources(uint32_t *list, uint32_t num_of_events)
+{
+ cirq_all_events.num_of_events = num_of_events;
+ cirq_all_events.wakeup_events = list;
+}
+/*
+ * mt_cirq_clone_gic: Copy the setting from GIC to SYS_CIRQ
+ */
+void mt_cirq_clone_gic(void)
+{
+ cirq_fast_clone();
+}
+
+uint32_t mt_irq_get_pending_vec(uint32_t start_irq)
+{
+ uint32_t base = 0U;
+ uint32_t pending_vec = 0U;
+ uint32_t reg = start_irq / 32U;
+ uint32_t LSB_num, MSB_num;
+ uint32_t LSB_vec, MSB_vec;
+
+ base = BASE_GICD_BASE;
+
+ /* if start_irq is not aligned 32, do some assembling */
+ MSB_num = start_irq % 32U;
+ if (MSB_num != 0U) {
+ LSB_num = 32U - MSB_num;
+ LSB_vec = mmio_read_32(base + GICD_ISPENDR +
+ reg * 4U) >> MSB_num;
+ MSB_vec = mmio_read_32(base + GICD_ISPENDR +
+ (reg + 1U) * 4U) << LSB_num;
+ pending_vec = MSB_vec | LSB_vec;
+ } else {
+ pending_vec = mmio_read_32(base + GICD_ISPENDR + reg * 4);
+ }
+
+ return pending_vec;
+}
+
+static int mt_cirq_get_mask_vec(unsigned int i)
+{
+ return mmio_read_32((i * 4U) + CIRQ_MASK_BASE);
+}
+
+/*
+ * mt_cirq_ack_all: Ack all the interrupt on SYS_CIRQ
+ */
+void mt_cirq_ack_all(void)
+{
+ uint32_t ack_vec, pend_vec, mask_vec;
+ unsigned int i;
+
+ for (i = 0; i < CIRQ_CTRL_REG_NUM; i++) {
+ /*
+ * if a irq is pending & not masked, don't ack it
+ * , since cirq start irq might not be 32 aligned with gic,
+ * need an exotic API to get proper vector of pending irq
+ */
+ pend_vec = mt_irq_get_pending_vec(CIRQ_SPI_START
+ + (i + 1U) * 32U);
+ mask_vec = mt_cirq_get_mask_vec(i);
+ /* those should be acked are: "not (pending & not masked)",
+ */
+ ack_vec = (~pend_vec) | mask_vec;
+ mmio_write_32(CIRQ_ACK_BASE + (i * 4U), ack_vec);
+ }
+
+ /*
+ * make sure all cirq setting take effect
+ * before doing other things
+ */
+ dsb();
+}
+/*
+ * mt_cirq_enable: Enable SYS_CIRQ
+ */
+void mt_cirq_enable(void)
+{
+ uint32_t st;
+
+ /* level only */
+ mt_cirq_ack_all();
+
+ st = mmio_read_32(CIRQ_CON);
+ /*
+ * CIRQ could monitor edge/level trigger
+ */
+ st |= (CIRQ_CON_EN << CIRQ_CON_EN_BITS);
+
+ mmio_write_32(CIRQ_CON, (st & CIRQ_CON_BITS_MASK));
+}
+
+/*
+ * mt_cirq_disable: Disable SYS_CIRQ
+ */
+void mt_cirq_disable(void)
+{
+ uint32_t st;
+
+ st = mmio_read_32(CIRQ_CON);
+ st &= ~(CIRQ_CON_EN << CIRQ_CON_EN_BITS);
+ mmio_write_32(CIRQ_CON, (st & CIRQ_CON_BITS_MASK));
+}
+
+void mt_irq_unmask_for_sleep_ex(uint32_t irq)
+{
+ uint32_t mask;
+
+ mask = 1U << (irq % 32U);
+
+ mmio_write_32(BASE_GICD_BASE + GICD_ISENABLER +
+ ((irq / 32U) * 4U), mask);
+}
+
+void mt_cirq_mask_all(void)
+{
+ unsigned int i;
+
+ for (i = 0U; i < CIRQ_CTRL_REG_NUM; i++) {
+ mmio_write_32(CIRQ_MASK_SET_BASE + (i * 4U), 0xFFFFFFFF);
+ }
+ dsb();
+}
+
+static void cirq_fast_sw_flush(void)
+{
+ struct cirq_reg *reg;
+ unsigned int i;
+
+ for (i = 0U; i < CIRQ_REG_NUM ; ++i) {
+ uint32_t cirq_bit;
+
+ reg = &cirq_all_events.table[i];
+
+ if (reg->used == 0U) {
+ continue;
+ }
+
+ reg->pending = mmio_read_32(CIRQ_STA_BASE +
+ (reg->reg_num << 2U));
+ reg->pending &= reg->mask;
+
+ for (cirq_bit = 0U; cirq_bit < 32U; ++cirq_bit) {
+ uint32_t val, cirq_id;
+
+ val = (1U << cirq_bit) & reg->pending;
+ if (val == 0U) {
+ continue;
+ }
+
+ cirq_id = (reg->reg_num << 5U) + cirq_bit;
+ mt_irq_set_pending(CIRQ_TO_IRQ_NUM(cirq_id));
+ if (CIRQ_TO_IRQ_NUM(cirq_id) == MD_WDT_IRQ_BIT_ID) {
+ INFO("Set MD_WDT_IRQ pending in %s\n",
+ __func__);
+ }
+ }
+ }
+}
+
+/*
+ * mt_cirq_disable: Flush interrupt from SYS_CIRQ to GIC
+ */
+void mt_cirq_flush(void)
+{
+ cirq_fast_sw_flush();
+ mt_cirq_mask_all();
+ mt_cirq_ack_all();
+}
+
+void mt_cirq_sw_reset(void)
+{
+#ifdef CIRQ_NEED_SW_RESET
+ uint32_t st;
+
+ st = mmio_read_32(CIRQ_CON);
+ st |= (CIRQ_SW_RESET << CIRQ_CON_SW_RST_BITS);
+ mmio_write_32(CIRQ_CON, st);
+#endif
+}
diff --git a/plat/mediatek/mt8192/plat_mt_gic.c b/plat/mediatek/mt8192/plat_mt_gic.c
index 593f5d0..ae8d697 100644
--- a/plat/mediatek/mt8192/plat_mt_gic.c
+++ b/plat/mediatek/mt8192/plat_mt_gic.c
@@ -175,3 +175,22 @@
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
}
+
+uint32_t mt_irq_get_pending(uint32_t irq)
+{
+ uint32_t val;
+
+ val = mmio_read_32(BASE_GICD_BASE + GICD_ISPENDR +
+ irq / 32 * 4);
+ val = (val >> (irq % 32)) & 1U;
+ return val;
+}
+
+
+void mt_irq_set_pending(uint32_t irq)
+{
+ uint32_t bit = 1U << (irq % 32);
+
+ mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR +
+ irq / 32 * 4, bit);
+}
diff --git a/plat/mediatek/mt8192/plat_pm.c b/plat/mediatek/mt8192/plat_pm.c
index 81a170d..6a74c02 100644
--- a/plat/mediatek/mt8192/plat_pm.c
+++ b/plat/mediatek/mt8192/plat_pm.c
@@ -5,22 +5,393 @@
*/
/* common headers */
+#include <assert.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/gpio.h>
#include <lib/psci/psci.h>
-/* mediatek platform specific headers */
+/* platform specific headers */
+#include <mt_gic_v3.h>
+#include <mtk_ptp3_common.h>
+#include <mtspmc.h>
+#include <plat/common/platform.h>
+#include <plat_mtk_lpm.h>
+#include <plat_params.h>
+#include <plat_pm.h>
+#include <pmic.h>
+#include <rtc.h>
+/*
+ * Cluster state request:
+ * [0] : The CPU requires cluster power down
+ * [1] : The CPU requires cluster power on
+ */
+#define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff)
+#define coordinate_cluster_pwron() coordinate_cluster(1)
+#define coordinate_cluster_pwroff() coordinate_cluster(0)
-/*******************************************************************************
- * MTK_platform handler called when an affinity instance is about to be turned
- * on. The level and mpidr determine the affinity instance.
- ******************************************************************************/
-static const plat_psci_ops_t plat_plat_pm_ops = {
+/* platform secure entry point */
+static uintptr_t secure_entrypoint;
+/* per-CPU power state */
+static unsigned int plat_power_state[PLATFORM_CORE_COUNT];
+
+/* platform CPU power domain - ops */
+static const struct mt_lpm_tz *plat_mt_pm;
+
+#define plat_mt_pm_invoke(_name, _cpu, _state) ({ \
+ int ret = -1; \
+ if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
+ ret = plat_mt_pm->_name(_cpu, _state); \
+ } \
+ ret; })
+
+#define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \
+ if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
+ (void) plat_mt_pm->_name(_cpu, _state); \
+ } \
+ })
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_cpu_pwrdwn_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state);
+
+ if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) ||
+ (req_pstate == 0U)) { /* hotplug off */
+ coordinate_cluster_pwroff();
+ }
+
+ /* Prevent interrupts from spuriously waking up this CPU */
+ mt_gic_rdistif_save();
+ gicv3_cpuif_disable(cpu);
+ gicv3_rdistif_off(cpu);
+ /* PTP3 config */
+ ptp3_deinit(cpu);
+}
+
+static void plat_cpu_pwron_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state);
+
+ coordinate_cluster_pwron();
+
+ /* Enable the GIC CPU interface */
+ gicv3_rdistif_on(cpu);
+ gicv3_cpuif_enable(cpu);
+ mt_gic_rdistif_init();
+
+ /*
+ * If mcusys does power down before then restore
+ * all CPUs' GIC Redistributors
+ */
+ if (IS_MCUSYS_OFF_STATE(state)) {
+ mt_gic_rdistif_restore_all();
+ } else {
+ mt_gic_rdistif_restore();
+ }
+
+ /* PTP3 config */
+ ptp3_init(cpu);
+}
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_cluster_pwrdwn_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) {
+ coordinate_cluster_pwron();
+
+ /* TODO: return on fail.
+ * Add a 'return' here before adding any code following
+ * the if-block.
+ */
+ }
+}
+
+static void plat_cluster_pwron_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) {
+ /* TODO: return on fail.
+ * Add a 'return' here before adding any code following
+ * the if-block.
+ */
+ }
+}
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_mcusys_pwrdwn_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) {
+ return; /* return on fail */
+ }
+
+ mt_gic_distif_save();
+ gic_sgi_save_all();
+}
+
+static void plat_mcusys_pwron_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) {
+ return; /* return on fail */
+ }
+
+ mt_gic_init();
+ mt_gic_distif_restore();
+ gic_sgi_restore_all();
+
+ plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
+}
+
+/*
+ * plat_psci_ops implementation
+ */
+
+static void plat_cpu_standby(plat_local_state_t cpu_state)
+{
+ uint64_t scr;
+
+ scr = read_scr_el3();
+ write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
+
+ isb();
+ dsb();
+ wfi();
+
+ write_scr_el3(scr);
+}
+
+static int plat_power_domain_on(u_register_t mpidr)
+{
+ unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+ unsigned int cluster = 0U;
+
+ if (cpu >= PLATFORM_CORE_COUNT) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ if (!spm_get_cluster_powerstate(cluster)) {
+ spm_poweron_cluster(cluster);
+ }
+
+ /* init CPU reset arch as AARCH64 */
+ mcucfg_init_archstate(cluster, cpu, true);
+ mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+ spm_poweron_cpu(cluster, cpu);
+
+ return PSCI_E_SUCCESS;
+}
+
+static void plat_power_domain_on_finish(const psci_power_state_t *state)
+{
+ unsigned long mpidr = read_mpidr_el1();
+ unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+
+ assert(cpu < PLATFORM_CORE_COUNT);
+
+ /* Allow IRQs to wakeup this core in IDLE flow */
+ mcucfg_enable_gic_wakeup(0U, cpu);
+
+ if (IS_CLUSTER_OFF_STATE(state)) {
+ plat_cluster_pwron_common(cpu, state, 0U);
+ }
+
+ plat_cpu_pwron_common(cpu, state, 0U);
+}
+
+static void plat_power_domain_off(const psci_power_state_t *state)
+{
+ unsigned long mpidr = read_mpidr_el1();
+ unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+
+ assert(cpu < PLATFORM_CORE_COUNT);
+
+ plat_cpu_pwrdwn_common(cpu, state, 0U);
+ spm_poweroff_cpu(0U, cpu);
+
+ /* prevent unintended IRQs from waking up the hot-unplugged core */
+ mcucfg_disable_gic_wakeup(0U, cpu);
+
+ if (IS_CLUSTER_OFF_STATE(state)) {
+ plat_cluster_pwrdwn_common(cpu, state, 0U);
+ }
+}
+
+static void plat_power_domain_suspend(const psci_power_state_t *state)
+{
+ unsigned int cpu = plat_my_core_pos();
+
+ assert(cpu < PLATFORM_CORE_COUNT);
+
+ plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state);
+
+ /* Perform the common CPU specific operations */
+ plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+
+ if (IS_CLUSTER_OFF_STATE(state)) {
+ /* Perform the common cluster specific operations */
+ plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+ }
+
+ if (IS_MCUSYS_OFF_STATE(state)) {
+ /* Perform the common mcusys specific operations */
+ plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+ }
+}
+
+static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
+{
+ unsigned int cpu = plat_my_core_pos();
+
+ assert(cpu < PLATFORM_CORE_COUNT);
+
+ if (IS_MCUSYS_OFF_STATE(state)) {
+ /* Perform the common mcusys specific operations */
+ plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]);
+ }
+
+ if (IS_CLUSTER_OFF_STATE(state)) {
+ /* Perform the common cluster specific operations */
+ plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]);
+ }
+
+ /* Perform the common CPU specific operations */
+ plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]);
+
+ plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state);
+}
+
+static int plat_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ unsigned int pstate = psci_get_pstate_type(power_state);
+ unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
+ unsigned int cpu = plat_my_core_pos();
+
+ if (pstate == PSTATE_TYPE_STANDBY) {
+ req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
+ } else {
+ unsigned int i;
+ unsigned int pstate_id = psci_get_pstate_id(power_state);
+ plat_local_state_t s = MTK_LOCAL_STATE_OFF;
+
+ /* Use pstate_id to be power domain state */
+ if (pstate_id > s) {
+ s = (plat_local_state_t)pstate_id;
+ }
+
+ for (i = 0U; i <= aff_lvl; i++) {
+ req_state->pwr_domain_state[i] = s;
+ }
+ }
+
+ plat_power_state[cpu] = power_state;
+ return PSCI_E_SUCCESS;
+}
+
+static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+ unsigned int lv;
+ unsigned int cpu = plat_my_core_pos();
+
+ for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) {
+ req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE;
+ }
+
+ plat_power_state[cpu] =
+ psci_make_powerstate(
+ MT_PLAT_PWR_STATE_SYSTEM_SUSPEND,
+ PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
+
+ flush_dcache_range((uintptr_t)
+ &plat_power_state[cpu],
+ sizeof(plat_power_state[cpu]));
+}
+
+static void __dead2 plat_mtk_system_off(void)
+{
+ INFO("MTK System Off\n");
+
+ rtc_power_off_sequence();
+ pmic_power_off();
+
+ wfi();
+ ERROR("MTK System Off: operation not handled.\n");
+ panic();
+}
+
+static void __dead2 plat_mtk_system_reset(void)
+{
+ struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
+
+ INFO("MTK System Reset\n");
+
+ gpio_set_value(gpio_reset->index, gpio_reset->polarity);
+
+ wfi();
+ ERROR("MTK System Reset: operation not handled.\n");
+ panic();
+}
+
+static const plat_psci_ops_t plat_psci_ops = {
+ .system_reset = plat_mtk_system_reset,
+ .cpu_standby = plat_cpu_standby,
+ .pwr_domain_on = plat_power_domain_on,
+ .pwr_domain_on_finish = plat_power_domain_on_finish,
+ .pwr_domain_off = plat_power_domain_off,
+ .pwr_domain_suspend = plat_power_domain_suspend,
+ .pwr_domain_suspend_finish = plat_power_domain_suspend_finish,
+ .system_off = plat_mtk_system_off,
+ .validate_power_state = plat_validate_power_state,
+ .get_sys_suspend_power_state = plat_get_sys_suspend_power_state
};
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
- *psci_ops = &plat_plat_pm_ops;
+ *psci_ops = &plat_psci_ops;
+ secure_entrypoint = sec_entrypoint;
+
+ /*
+ * init the warm reset config for boot CPU
+ * reset arch as AARCH64
+ * reset addr as function bl31_warm_entrypoint()
+ */
+ mcucfg_init_archstate(0U, 0U, true);
+ mcucfg_set_bootaddr(0U, 0U, secure_entrypoint);
+
+ spmc_init();
+ plat_mt_pm = mt_plat_cpu_pm_init();
return 0;
}
diff --git a/plat/mediatek/mt8192/plat_sip_calls.c b/plat/mediatek/mt8192/plat_sip_calls.c
new file mode 100644
index 0000000..f97684f
--- /dev/null
+++ b/plat/mediatek/mt8192/plat_sip_calls.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+
+uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+
+ switch (smc_fid) {
+ default:
+ ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+ break;
+ }
+
+ SMC_RET1(handle, SMC_UNK);
+}
diff --git a/plat/mediatek/mt8192/plat_topology.c b/plat/mediatek/mt8192/plat_topology.c
index aa4975e..8c1231a 100644
--- a/plat/mediatek/mt8192/plat_topology.c
+++ b/plat/mediatek/mt8192/plat_topology.c
@@ -17,6 +17,8 @@
/* Number of root nodes */
PLATFORM_SYSTEM_COUNT,
/* Number of children for the root node */
+ PLATFORM_MCUSYS_COUNT,
+ /* Number of children for the mcusys node */
PLATFORM_CLUSTER_COUNT,
/* Number of children for the first cluster node */
PLATFORM_CLUSTER0_CORE_COUNT,
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index c972ac6..a5e7ee2 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -8,7 +8,18 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
- -I${MTK_PLAT_SOC}/include/
+ -I${MTK_PLAT_SOC}/include/ \
+ -I${MTK_PLAT_SOC}/drivers/ \
+ -I${MTK_PLAT_SOC}/drivers/dcm \
+ -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
+ -I${MTK_PLAT_SOC}/drivers/gpio/ \
+ -I${MTK_PLAT_SOC}/drivers/mcdi/ \
+ -I${MTK_PLAT_SOC}/drivers/pmic/ \
+ -I${MTK_PLAT_SOC}/drivers/ptp3/ \
+ -I${MTK_PLAT_SOC}/drivers/rtc/ \
+ -I${MTK_PLAT_SOC}/drivers/spmc/ \
+ -I${MTK_PLAT_SOC}/drivers/timer/ \
+ -I${MTK_PLAT_SOC}/drivers/uart/
GICV3_SUPPORT_GIC600 := 1
include drivers/arm/gic/v3/gicv3.mk
@@ -20,20 +31,40 @@
plat/common/plat_psci_common.c
BL31_SOURCES += common/desc_image_load.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
+ drivers/gpio/gpio.c \
lib/bl_aux_params/bl_aux_params.c \
lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_gicv3.c \
+ ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
+ ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
+ ${MTK_PLAT}/common/drivers/uart/uart.c \
${MTK_PLAT}/common/mtk_plat_common.c \
+ ${MTK_PLAT}/common/mtk_sip_svc.c \
${MTK_PLAT}/common/params_setup.c \
${MTK_PLAT_SOC}/aarch64/platform_common.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
+ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
+ ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_topology.c \
- ${MTK_PLAT_SOC}/plat_mt_gic.c
-
+ ${MTK_PLAT_SOC}/plat_mt_gic.c \
+ ${MTK_PLAT_SOC}/plat_mt_cirq.c \
+ ${MTK_PLAT_SOC}/plat_sip_calls.c \
+ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
+ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
+ ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
+ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
+ ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \
+ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
+ ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c
# Configs for A76 and A55
HW_ASSISTED_COHERENCY := 1
diff --git a/plat/nvidia/tegra/common/tegra_platform.c b/plat/nvidia/tegra/common/tegra_platform.c
index 7c73e8f..d45d988 100644
--- a/plat/nvidia/tegra/common/tegra_platform.c
+++ b/plat/nvidia/tegra/common/tegra_platform.c
@@ -297,14 +297,14 @@
}
/*****************************************************************************
- * plat_smccc_feature_available() - This function checks whether SMCCC feature
+ * plat_is_smccc_feature_available() - This function checks whether SMCCC feature
* is availabile for the platform or not.
* @fid: SMCCC function id
*
* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
* SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
*****************************************************************************/
-int32_t plat_smccc_feature_available(u_register_t fid)
+int32_t plat_is_smccc_feature_available(u_register_t fid)
{
switch (fid) {
case SMCCC_ARCH_SOC_ID:
diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c
index 7f8e4c4..7d2730d 100644
--- a/plat/qemu/common/qemu_common.c
+++ b/plat/qemu/common/qemu_common.c
@@ -94,6 +94,7 @@
MAP_DEVICE1,
#endif
#if SPM_MM
+ MAP_NS_DRAM0,
QEMU_SPM_BUF_EL3_MMAP,
#else
MAP_BL32_MEM,
diff --git a/plat/qemu/common/qemu_spm.c b/plat/qemu/common/qemu_spm.c
index e9ab1a5..93dd2b3 100644
--- a/plat/qemu/common/qemu_spm.c
+++ b/plat/qemu/common/qemu_spm.c
@@ -3,7 +3,12 @@
* Copyright (c) 2020, Linaro Limited and Contributors. All rights reserved.
*/
+#include <libfdt.h>
+
#include <bl31/ehf.h>
+#include <common/debug.h>
+#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
#include <lib/xlat_tables/xlat_tables_compat.h>
#include <services/spm_mm_partition.h>
@@ -14,12 +19,13 @@
DEVICE1_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-const mmap_region_t plat_qemu_secure_partition_mmap[] = {
- MAP_DEVICE1_EL0, /* for the UART */
+mmap_region_t plat_qemu_secure_partition_mmap[] = {
+ QEMU_SP_IMAGE_NS_BUF_MMAP, /* must be placed at first entry */
+ MAP_DEVICE1_EL0, /* for the UART */
QEMU_SP_IMAGE_MMAP,
QEMU_SPM_BUF_EL0_MMAP,
- QEMU_SP_IMAGE_NS_BUF_MMAP,
QEMU_SP_IMAGE_RW_MMAP,
+ MAP_SECURE_VARSTORE,
{0}
};
@@ -38,7 +44,7 @@
[7] = {0x80000007, 0}
};
-const spm_mm_boot_info_t plat_qemu_secure_partition_boot_info = {
+spm_mm_boot_info_t plat_qemu_secure_partition_boot_info = {
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
.h.version = VERSION_1,
.h.size = sizeof(spm_mm_boot_info_t),
@@ -65,12 +71,63 @@
EHF_PRI_DESC(QEMU_PRI_BITS, PLAT_SP_PRI)
};
+int dt_add_ns_buf_node(uintptr_t *base)
+{
+ uintptr_t addr;
+ size_t size;
+ uintptr_t ns_buf_addr;
+ int node;
+ int err;
+ void *fdt = (void *)ARM_PRELOADED_DTB_BASE;
+
+ err = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
+ if (err < 0) {
+ ERROR("Invalid Device Tree at %p: error %d\n", fdt, err);
+ return err;
+ }
+
+ /*
+ * reserved-memory for standaloneMM non-secure buffer
+ * is allocated at the top of the first system memory region.
+ */
+ node = fdt_path_offset(fdt, "/memory");
+
+ err = fdt_get_reg_props_by_index(fdt, node, 0, &addr, &size);
+ if (err < 0) {
+ ERROR("Failed to get the memory node information\n");
+ return err;
+ }
+ INFO("System RAM @ 0x%lx - 0x%lx\n", addr, addr + size - 1);
+
+ ns_buf_addr = addr + (size - PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE);
+ INFO("reserved-memory for spm-mm @ 0x%lx - 0x%llx\n", ns_buf_addr,
+ ns_buf_addr + PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE - 1);
+
+ err = fdt_add_reserved_memory(fdt, "ns-buf-spm-mm", ns_buf_addr,
+ PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE);
+ if (err < 0) {
+ ERROR("Failed to add the reserved-memory node\n");
+ return err;
+ }
+
+ *base = ns_buf_addr;
+ return 0;
+}
+
/* Plug in QEMU exceptions to Exception Handling Framework. */
EHF_REGISTER_PRIORITIES(qemu_exceptions, ARRAY_SIZE(qemu_exceptions),
QEMU_PRI_BITS);
const mmap_region_t *plat_get_secure_partition_mmap(void *cookie)
{
+ uintptr_t ns_buf_base;
+
+ dt_add_ns_buf_node(&ns_buf_base);
+
+ plat_qemu_secure_partition_mmap[0].base_pa = ns_buf_base;
+ plat_qemu_secure_partition_mmap[0].base_va = ns_buf_base;
+ plat_qemu_secure_partition_boot_info.sp_ns_comm_buf_base = ns_buf_base;
+
return plat_qemu_secure_partition_mmap;
}
diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h
index 7634005..db394c0 100644
--- a/plat/qemu/qemu_sbsa/include/platform_def.h
+++ b/plat/qemu/qemu_sbsa/include/platform_def.h
@@ -85,7 +85,7 @@
*/
#define SHARED_RAM_BASE SEC_SRAM_BASE
-#define SHARED_RAM_SIZE 0x00001000
+#define SHARED_RAM_SIZE 0x00002000
#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE
#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE)
@@ -300,10 +300,13 @@
/*
* Shared memory between Normal world and S-EL0 for
* passing data during service requests. It will be marked as RW and NS.
+ * This buffer is allocated at the top of NS_DRAM, the base address is
+ * overridden in SPM initialization.
*/
#define PLAT_QEMU_SP_IMAGE_NS_BUF_BASE (PLAT_QEMU_DT_BASE + \
PLAT_QEMU_DT_MAX_SIZE)
-#define PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
+#define PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE ULL(0x200000)
+
#define QEMU_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \
PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \
PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \
@@ -334,6 +337,19 @@
MT_USER, \
PAGE_SIZE)
+/*
+ * Secure variable storage is located at Secure Flash.
+ */
+#if SPM_MM
+#define QEMU_SECURE_VARSTORE_BASE 0x01000000
+#define QEMU_SECURE_VARSTORE_SIZE 0x00100000
+#define MAP_SECURE_VARSTORE MAP_REGION_FLAT( \
+ QEMU_SECURE_VARSTORE_BASE, \
+ QEMU_SECURE_VARSTORE_SIZE, \
+ MT_MEMORY | MT_RW | \
+ MT_SECURE | MT_USER)
+#endif
+
/* Total number of memory regions with distinct properties */
#define PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS 6
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 3aa7cbe..98d1347 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -47,9 +47,8 @@
${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
-BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S
+BL1_SOURCES += lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S
BL2_SOURCES += drivers/io/io_semihosting.c \
drivers/io/io_storage.c \
@@ -75,9 +74,8 @@
plat/common/plat_gicv3.c \
${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c
-BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
+BL31_SOURCES += lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \
@@ -85,6 +83,8 @@
${PLAT_QEMU_COMMON_PATH}/topology.c \
${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
+ common/fdt_fixup.c \
+ common/fdt_wrappers.c \
${QEMU_GIC_SOURCES}
ifeq (${SPM_MM},1)
BL31_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_spm.c
diff --git a/plat/qti/common/src/qti_common.c b/plat/qti/common/src/qti_common.c
index 9355eb7..da0eaec 100644
--- a/plat/qti/common/src/qti_common.c
+++ b/plat/qti/common/src/qti_common.c
@@ -176,14 +176,14 @@
}
/*****************************************************************************
- * plat_smccc_feature_available() - This function checks whether SMCCC feature
+ * plat_is_smccc_feature_available() - This function checks whether SMCCC feature
* is availabile for the platform or not.
* @fid: SMCCC function id
*
* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
* SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
*****************************************************************************/
-int32_t plat_smccc_feature_available(u_register_t fid)
+int32_t plat_is_smccc_feature_available(u_register_t fid)
{
switch (fid) {
case SMCCC_ARCH_SOC_ID:
diff --git a/plat/renesas/rcar/aarch64/plat_helpers.S b/plat/renesas/common/aarch64/plat_helpers.S
similarity index 100%
rename from plat/renesas/rcar/aarch64/plat_helpers.S
rename to plat/renesas/common/aarch64/plat_helpers.S
diff --git a/plat/renesas/rcar/aarch64/platform_common.c b/plat/renesas/common/aarch64/platform_common.c
similarity index 100%
rename from plat/renesas/rcar/aarch64/platform_common.c
rename to plat/renesas/common/aarch64/platform_common.c
diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/common/bl2_cpg_init.c
similarity index 97%
rename from plat/renesas/rcar/bl2_cpg_init.c
rename to plat/renesas/common/bl2_cpg_init.c
index c3ca9ea..1754344 100644
--- a/plat/renesas/rcar/bl2_cpg_init.c
+++ b/plat/renesas/common/bl2_cpg_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,8 @@
#include <common/debug.h>
#include <lib/mmio.h>
-#include "rcar_def.h"
#include "cpg_registers.h"
+#include "rcar_def.h"
#include "rcar_private.h"
static void bl2_secure_cpg_init(void);
@@ -77,7 +77,7 @@
stop_cr5 = 0xBFFFFFFFU;
#endif
- /** Secure Module Stop Control Registers */
+ /* Secure Module Stop Control Registers */
cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
cpg_write(SCMSTPCR2, stop_cr2);
@@ -91,7 +91,7 @@
cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
- /** Secure Software Reset Access Enable Control Registers */
+ /* Secure Software Reset Access Enable Control Registers */
cpg_write(SCSRSTECR0, 0x00000000U);
cpg_write(SCSRSTECR1, 0x00000000U);
cpg_write(SCSRSTECR2, reset_cr2);
@@ -152,7 +152,7 @@
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
static void bl2_realtime_cpg_init_m3(void)
{
- /** Realtime Module Stop Control Registers */
+ /* Realtime Module Stop Control Registers */
cpg_write(RMSTPCR0, 0x00200000U);
cpg_write(RMSTPCR1, 0xFFFFFFFFU);
cpg_write(RMSTPCR2, 0x040E0FDCU);
@@ -169,7 +169,7 @@
static void bl2_system_cpg_init_m3(void)
{
- /** System Module Stop Control Registers */
+ /* System Module Stop Control Registers */
cpg_write(SMSTPCR0, 0x00200000U);
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x040E2FDCU);
@@ -188,7 +188,7 @@
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
static void bl2_realtime_cpg_init_m3n(void)
{
- /** Realtime Module Stop Control Registers */
+ /* Realtime Module Stop Control Registers */
cpg_write(RMSTPCR0, 0x00210000U);
cpg_write(RMSTPCR1, 0xFFFFFFFFU);
cpg_write(RMSTPCR2, 0x040E0FDCU);
diff --git a/plat/renesas/rcar/bl2_interrupt_error.c b/plat/renesas/common/bl2_interrupt_error.c
similarity index 100%
rename from plat/renesas/rcar/bl2_interrupt_error.c
rename to plat/renesas/common/bl2_interrupt_error.c
diff --git a/plat/renesas/rcar/bl2_plat_mem_params_desc.c b/plat/renesas/common/bl2_plat_mem_params_desc.c
similarity index 100%
rename from plat/renesas/rcar/bl2_plat_mem_params_desc.c
rename to plat/renesas/common/bl2_plat_mem_params_desc.c
diff --git a/plat/renesas/common/bl2_secure_setting.c b/plat/renesas/common/bl2_secure_setting.c
new file mode 100644
index 0000000..095d1f6
--- /dev/null
+++ b/plat/renesas/common/bl2_secure_setting.c
@@ -0,0 +1,362 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include "axi_registers.h"
+#include "lifec_registers.h"
+#include "micro_delay.h"
+
+static void lifec_security_setting(void);
+static void axi_security_setting(void);
+
+static const struct {
+ uint32_t reg;
+ uint32_t val;
+} lifec[] = {
+ /*
+ * LIFEC0 (SECURITY) settings
+ * Security attribute setting for master ports
+ * Bit 0: ARM realtime core (Cortex-R7) master port
+ * 0: Non-Secure
+ */
+ { SEC_SRC, 0x0000001EU },
+ /*
+ * Security attribute setting for slave ports 0 to 15
+ * {SEC_SEL0, 0xFFFFFFFFU},
+ * {SEC_SEL1, 0xFFFFFFFFU},
+ * {SEC_SEL2, 0xFFFFFFFFU},
+ * Bit19: AXI-Bus (Main Memory domain AXI) slave ports
+ * 0: registers accessed from secure resource only
+ * Bit 9: DBSC4 register access slave ports.
+ * 0: registers accessed from secure resource only.
+ */
+#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
+ { SEC_SEL3, 0xFFF7FDFFU },
+#else /* LIFEC_DBSC_PROTECT_ENABLE == 1 */
+ { SEC_SEL3, 0xFFFFFFFFU },
+#endif /* LIFEC_DBSC_PROTECT_ENABLE == 1 */
+ /*
+ * {SEC_SEL4, 0xFFFFFFFFU},
+ * Bit 6: Boot ROM slave ports.
+ * 0: registers accessed from secure resource only
+ */
+ { SEC_SEL5, 0xFFFFFFBFU },
+ /*
+ * Bit13: SCEG PKA (secure APB) slave ports
+ * 0: registers accessed from secure resource only
+ * 1: Reserved[R-Car E3]
+ * Bit12: SCEG PKA (public APB) slave ports
+ * 0: registers accessed from secure resource only
+ * 1: Reserved[R-Car E3]
+ * Bit10: SCEG Secure Core slave ports
+ * 0: registers accessed from secure resource only
+ */
+#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
+ { SEC_SEL6, 0xFFFFFBFFU },
+#else /* (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) */
+ { SEC_SEL6, 0xFFFFCBFFU },
+#endif /* (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) */
+ /*
+ * {SEC_SEL7, 0xFFFFFFFFU},
+ * {SEC_SEL8, 0xFFFFFFFFU},
+ * {SEC_SEL9, 0xFFFFFFFFU},
+ * {SEC_SEL10, 0xFFFFFFFFU},
+ * {SEC_SEL11, 0xFFFFFFFFU},
+ * {SEC_SEL12, 0xFFFFFFFFU},
+ * Bit22: RPC slave ports.
+ * 0: registers accessed from secure resource only.
+ */
+#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
+ { SEC_SEL13, 0xFFBFFFFFU },
+#endif /* (RCAR_RPC_HYPERFLASH_LOCKED == 1) */
+ /*
+ * Bit27: System Timer (SCMT) slave ports
+ * 0: registers accessed from secure resource only
+ * Bit26: System Watchdog Timer (SWDT) slave ports
+ * 0: registers accessed from secure resource only
+ */
+ { SEC_SEL14, 0xF3FFFFFFU },
+ /*
+ * Bit13: RST slave ports.
+ * 0: registers accessed from secure resource only
+ * Bit 7: Life Cycle 0 slave ports
+ * 0: registers accessed from secure resource only
+ */
+ { SEC_SEL15, 0xFFFFFF3FU },
+ /*
+ * Security group 0 attribute setting for master ports 0
+ * Security group 1 attribute setting for master ports 0
+ * {SEC_GRP0CR0, 0x00000000U},
+ * {SEC_GRP1CR0, 0x00000000U},
+ * Security group 0 attribute setting for master ports 1
+ * Security group 1 attribute setting for master ports 1
+ * {SEC_GRP0CR1, 0x00000000U},
+ * {SEC_GRP1CR1, 0x00000000U},
+ * Security group 0 attribute setting for master ports 2
+ * Security group 1 attribute setting for master ports 2
+ * Bit17: SCEG Secure Core master ports.
+ * SecurityGroup3
+ */
+ { SEC_GRP0CR2, 0x00020000U },
+ { SEC_GRP1CR2, 0x00020000U },
+ /*
+ * Security group 0 attribute setting for master ports 3
+ * Security group 1 attribute setting for master ports 3
+ * {SEC_GRP0CR3, 0x00000000U},
+ * {SEC_GRP1CR3, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 0
+ * Security group 1 attribute setting for slave ports 0
+ * {SEC_GRP0COND0, 0x00000000U},
+ * {SEC_GRP1COND0, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 1
+ * Security group 1 attribute setting for slave ports 1
+ * {SEC_GRP0COND1, 0x00000000U},
+ * {SEC_GRP1COND1, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 2
+ * Security group 1 attribute setting for slave ports 2
+ * {SEC_GRP0COND2, 0x00000000U},
+ * {SEC_GRP1COND2, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 3
+ * Security group 1 attribute setting for slave ports 3
+ * Bit19: AXI-Bus (Main Memory domain AXI) slave ports.
+ * SecurityGroup3
+ * Bit 9: DBSC4 register access slave ports.
+ * SecurityGroup3
+ */
+#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
+ { SEC_GRP0COND3, 0x00080200U },
+ { SEC_GRP1COND3, 0x00080200U },
+#else /* (LIFEC_DBSC_PROTECT_ENABLE == 1) */
+ { SEC_GRP0COND3, 0x00000000U },
+ { SEC_GRP1COND3, 0x00000000U },
+#endif /* (LIFEC_DBSC_PROTECT_ENABLE == 1) */
+ /*
+ * Security group 0 attribute setting for slave ports 4
+ * Security group 1 attribute setting for slave ports 4
+ * {SEC_GRP0COND4, 0x00000000U},
+ * {SEC_GRP1COND4, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 5
+ * Security group 1 attribute setting for slave ports 5
+ * Bit 6: Boot ROM slave ports
+ * SecurityGroup3
+ */
+ { SEC_GRP0COND5, 0x00000040U },
+ { SEC_GRP1COND5, 0x00000040U },
+ /*
+ * Security group 0 attribute setting for slave ports 6
+ * Security group 1 attribute setting for slave ports 6
+ * Bit13: SCEG PKA (secure APB) slave ports
+ * SecurityGroup3
+ * Reserved[R-Car E3]
+ * Bit12: SCEG PKA (public APB) slave ports
+ * SecurityGroup3
+ * Reserved[R-Car E3]
+ * Bit10: SCEG Secure Core slave ports
+ * SecurityGroup3
+ */
+#if RCAR_LSI == RCAR_E3
+ { SEC_GRP0COND6, 0x00000400U },
+ { SEC_GRP1COND6, 0x00000400U },
+#else /* RCAR_LSI == RCAR_E3 */
+ { SEC_GRP0COND6, 0x00003400U },
+ { SEC_GRP1COND6, 0x00003400U },
+#endif /* RCAR_LSI == RCAR_E3 */
+ /*
+ * Security group 0 attribute setting for slave ports 7
+ * Security group 1 attribute setting for slave ports 7
+ * {SEC_GRP0COND7, 0x00000000U},
+ * {SEC_GRP1COND7, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 8
+ * Security group 1 attribute setting for slave ports 8
+ * {SEC_GRP0COND8, 0x00000000U},
+ * {SEC_GRP1COND8, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 9
+ * Security group 1 attribute setting for slave ports 9
+ * {SEC_GRP0COND9, 0x00000000U},
+ * {SEC_GRP1COND9, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 10
+ * Security group 1 attribute setting for slave ports 10
+ * {SEC_GRP0COND10, 0x00000000U},
+ * {SEC_GRP1COND10, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 11
+ * Security group 1 attribute setting for slave ports 11
+ * {SEC_GRP0COND11, 0x00000000U},
+ * {SEC_GRP1COND11, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 12
+ * Security group 1 attribute setting for slave ports 12
+ * {SEC_GRP0COND12, 0x00000000U},
+ * {SEC_GRP1COND12, 0x00000000U},
+ * Security group 0 attribute setting for slave ports 13
+ * Security group 1 attribute setting for slave ports 13
+ * Bit22: RPC slave ports.
+ * SecurityGroup3
+ */
+#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
+ { SEC_GRP0COND13, 0x00400000U },
+ { SEC_GRP1COND13, 0x00400000U },
+#endif /* (RCAR_RPC_HYPERFLASH_LOCKED == 1) */
+ /*
+ * Security group 0 attribute setting for slave ports 14
+ * Security group 1 attribute setting for slave ports 14
+ * Bit26: System Timer (SCMT) slave ports
+ * SecurityGroup3
+ * Bit27: System Watchdog Timer (SWDT) slave ports
+ * SecurityGroup3
+ */
+ { SEC_GRP0COND14, 0x0C000000U },
+ { SEC_GRP1COND14, 0x0C000000U },
+ /*
+ * Security group 0 attribute setting for slave ports 15
+ * Security group 1 attribute setting for slave ports 15
+ * Bit13: RST slave ports
+ * SecurityGroup3
+ * Bit 7: Life Cycle 0 slave ports
+ * SecurityGroup3
+ * Bit 6: TDBG slave ports
+ * SecurityGroup3
+ */
+ { SEC_GRP0COND15, 0x000000C0U },
+ { SEC_GRP1COND15, 0x000000C0U },
+ /*
+ * Security write protection attribute setting slave ports 0
+ * {SEC_READONLY0, 0x00000000U},
+ * Security write protection attribute setting slave ports 1
+ * {SEC_READONLY1, 0x00000000U},
+ * Security write protection attribute setting slave ports 2
+ * {SEC_READONLY2, 0x00000000U},
+ * Security write protection attribute setting slave ports 3
+ * {SEC_READONLY3, 0x00000000U},
+ * Security write protection attribute setting slave ports 4
+ * {SEC_READONLY4, 0x00000000U},
+ * Security write protection attribute setting slave ports 5
+ * {SEC_READONLY5, 0x00000000U},
+ * Security write protection attribute setting slave ports 6
+ * {SEC_READONLY6, 0x00000000U},
+ * Security write protection attribute setting slave ports 7
+ * {SEC_READONLY7, 0x00000000U},
+ * Security write protection attribute setting slave ports 8
+ * {SEC_READONLY8, 0x00000000U},
+ * Security write protection attribute setting slave ports 9
+ * {SEC_READONLY9, 0x00000000U},
+ * Security write protection attribute setting slave ports 10
+ * {SEC_READONLY10, 0x00000000U},
+ * Security write protection attribute setting slave ports 11
+ * {SEC_READONLY11, 0x00000000U},
+ * Security write protection attribute setting slave ports 12
+ * {SEC_READONLY12, 0x00000000U},
+ * Security write protection attribute setting slave ports 13
+ * {SEC_READONLY13, 0x00000000U},
+ * Security write protection attribute setting slave ports 14
+ * {SEC_READONLY14, 0x00000000U},
+ * Security write protection attribute setting slave ports 15
+ * {SEC_READONLY15, 0x00000000U}
+ */
+};
+
+/* AXI settings */
+static const struct {
+ uint32_t reg;
+ uint32_t val;
+} axi[] = {
+ /*
+ * DRAM protection
+ * AXI dram protected area division
+ */
+ {AXI_DPTDIVCR0, 0x0E0403F0U},
+ {AXI_DPTDIVCR1, 0x0E0407E0U},
+ {AXI_DPTDIVCR2, 0x0E080000U},
+ {AXI_DPTDIVCR3, 0x0E080000U},
+ {AXI_DPTDIVCR4, 0x0E080000U},
+ {AXI_DPTDIVCR5, 0x0E080000U},
+ {AXI_DPTDIVCR6, 0x0E080000U},
+ {AXI_DPTDIVCR7, 0x0E080000U},
+ {AXI_DPTDIVCR8, 0x0E080000U},
+ {AXI_DPTDIVCR9, 0x0E080000U},
+ {AXI_DPTDIVCR10, 0x0E080000U},
+ {AXI_DPTDIVCR11, 0x0E080000U},
+ {AXI_DPTDIVCR12, 0x0E080000U},
+ {AXI_DPTDIVCR13, 0x0E080000U},
+ {AXI_DPTDIVCR14, 0x0E080000U},
+ /* AXI dram protected area setting */
+ {AXI_DPTCR0, 0x0E000000U},
+ {AXI_DPTCR1, 0x0E000E0EU},
+ {AXI_DPTCR2, 0x0E000000U},
+ {AXI_DPTCR3, 0x0E000000U},
+ {AXI_DPTCR4, 0x0E000000U},
+ {AXI_DPTCR5, 0x0E000000U},
+ {AXI_DPTCR6, 0x0E000000U},
+ {AXI_DPTCR7, 0x0E000000U},
+ {AXI_DPTCR8, 0x0E000000U},
+ {AXI_DPTCR9, 0x0E000000U},
+ {AXI_DPTCR10, 0x0E000000U},
+ {AXI_DPTCR11, 0x0E000000U},
+ {AXI_DPTCR12, 0x0E000000U},
+ {AXI_DPTCR13, 0x0E000000U},
+ {AXI_DPTCR14, 0x0E000000U},
+ {AXI_DPTCR15, 0x0E000000U},
+ /*
+ * SRAM ptotection
+ * AXI sram protected area division
+ */
+ {AXI_SPTDIVCR0, 0x0E0E6304U},
+ {AXI_SPTDIVCR1, 0x0E0E6360U},
+ {AXI_SPTDIVCR2, 0x0E0E6360U},
+ {AXI_SPTDIVCR3, 0x0E0E6360U},
+ {AXI_SPTDIVCR4, 0x0E0E6360U},
+ {AXI_SPTDIVCR5, 0x0E0E6360U},
+ {AXI_SPTDIVCR6, 0x0E0E6360U},
+ {AXI_SPTDIVCR7, 0x0E0E6360U},
+ {AXI_SPTDIVCR8, 0x0E0E6360U},
+ {AXI_SPTDIVCR9, 0x0E0E6360U},
+ {AXI_SPTDIVCR10, 0x0E0E6360U},
+ {AXI_SPTDIVCR11, 0x0E0E6360U},
+ {AXI_SPTDIVCR12, 0x0E0E6360U},
+ {AXI_SPTDIVCR13, 0x0E0E6360U},
+ {AXI_SPTDIVCR14, 0x0E0E6360U},
+ /* AXI sram protected area setting */
+ {AXI_SPTCR0, 0x0E000E0EU},
+ {AXI_SPTCR1, 0x0E000000U},
+ {AXI_SPTCR2, 0x0E000000U},
+ {AXI_SPTCR3, 0x0E000000U},
+ {AXI_SPTCR4, 0x0E000000U},
+ {AXI_SPTCR5, 0x0E000000U},
+ {AXI_SPTCR6, 0x0E000000U},
+ {AXI_SPTCR7, 0x0E000000U},
+ {AXI_SPTCR8, 0x0E000000U},
+ {AXI_SPTCR9, 0x0E000000U},
+ {AXI_SPTCR10, 0x0E000000U},
+ {AXI_SPTCR11, 0x0E000000U},
+ {AXI_SPTCR12, 0x0E000000U},
+ {AXI_SPTCR13, 0x0E000000U},
+ {AXI_SPTCR14, 0x0E000000U},
+ {AXI_SPTCR15, 0x0E000000U}
+};
+
+static void lifec_security_setting(void)
+{
+ uint32_t i;
+
+ for (i = 0; i < ARRAY_SIZE(lifec); i++)
+ mmio_write_32(lifec[i].reg, lifec[i].val);
+}
+
+/* SRAM/DRAM protection setting */
+static void axi_security_setting(void)
+{
+ uint32_t i;
+
+ for (i = 0; i < ARRAY_SIZE(axi); i++)
+ mmio_write_32(axi[i].reg, axi[i].val);
+}
+
+void bl2_secure_setting(void)
+{
+ lifec_security_setting();
+ axi_security_setting();
+ rcar_micro_delay(10U);
+}
diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/common/bl31_plat_setup.c
similarity index 84%
rename from plat/renesas/rcar/bl31_plat_setup.c
rename to plat/renesas/common/bl31_plat_setup.c
index 7bc0d8e..93798ac 100644
--- a/plat/renesas/rcar/bl31_plat_setup.c
+++ b/plat/renesas/common/bl31_plat_setup.c
@@ -28,7 +28,7 @@
#if USE_COHERENT_MEM
static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
-#endif
+#endif /* USE_COHERENT_MEM */
extern void plat_rcar_gic_driver_init(void);
extern void plat_rcar_gic_init(void);
@@ -84,11 +84,11 @@
NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
#if RCAR_LSI != RCAR_D3
- if (RCAR_CLUSTER_A53A57 == rcar_pwrc_get_cluster()) {
+ if (rcar_pwrc_get_cluster() == RCAR_CLUSTER_A53A57) {
plat_cci_init();
plat_cci_enable();
}
-#endif
+#endif /* RCAR_LSI != RCAR_D3 */
}
void bl31_plat_arch_setup(void)
@@ -98,7 +98,7 @@
BL31_RO_BASE, BL31_RO_LIMIT
#if USE_COHERENT_MEM
, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
-#endif
+#endif /* USE_COHERENT_MEM */
);
rcar_pwrc_code_copy_to_system_ram();
}
@@ -113,17 +113,20 @@
rcar_pwrc_setup();
#if 0
- /* TODO: there is a broad number of rcar-gen3 SoC configurations; to
- support all of them, Renesas use the pwrc driver to discover what
- cores are on/off before announcing the topology.
- This code hasnt been ported yet
- */
+ /*
+ * TODO: there is a broad number of rcar-gen3 SoC configurations; to
+ * support all of them, Renesas use the pwrc driver to discover what
+ * cores are on/off before announcing the topology.
+ * This code hasnt been ported yet
+ */
rcar_setup_topology();
#endif
- /* mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
- identified during cpuhotplug (check the kernel's psci migrate set of
- functions */
+ /*
+ * mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
+ * identified during cpuhotplug (check the kernel's psci migrate set of
+ * functions
+ */
rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU;
}
diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk
new file mode 100644
index 0000000..cadb3d7
--- /dev/null
+++ b/plat/renesas/common/common.mk
@@ -0,0 +1,129 @@
+#
+# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PROGRAMMABLE_RESET_ADDRESS := 0
+COLD_BOOT_SINGLE_CPU := 1
+ARM_CCI_PRODUCT_ID := 500
+TRUSTED_BOARD_BOOT := 1
+RESET_TO_BL31 := 1
+GENERATE_COT := 1
+BL2_AT_EL3 := 1
+ENABLE_SVE_FOR_NS := 0
+MULTI_CONSOLE_API := 1
+
+CRASH_REPORTING := 1
+HANDLE_EA_EL3_FIRST := 1
+
+$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
+
+ifeq (${SPD},none)
+ SPD_NONE:=1
+ $(eval $(call add_define,SPD_NONE))
+endif
+
+# LSI setting common define
+RCAR_H3:=0
+RCAR_M3:=1
+RCAR_M3N:=2
+RCAR_E3:=3
+RCAR_H3N:=4
+RCAR_D3:=5
+RCAR_V3M:=6
+RCAR_AUTO:=99
+$(eval $(call add_define,RCAR_H3))
+$(eval $(call add_define,RCAR_M3))
+$(eval $(call add_define,RCAR_M3N))
+$(eval $(call add_define,RCAR_E3))
+$(eval $(call add_define,RCAR_H3N))
+$(eval $(call add_define,RCAR_D3))
+$(eval $(call add_define,RCAR_V3M))
+$(eval $(call add_define,RCAR_AUTO))
+RCAR_CUT_10:=0
+RCAR_CUT_11:=1
+RCAR_CUT_13:=3
+RCAR_CUT_20:=10
+RCAR_CUT_30:=20
+$(eval $(call add_define,RCAR_CUT_10))
+$(eval $(call add_define,RCAR_CUT_11))
+$(eval $(call add_define,RCAR_CUT_13))
+$(eval $(call add_define,RCAR_CUT_20))
+$(eval $(call add_define,RCAR_CUT_30))
+
+# Enable workarounds for selected Cortex-A53 erratas.
+ERRATA_A53_835769 := 1
+ERRATA_A53_843419 := 1
+ERRATA_A53_855873 := 1
+
+# Enable workarounds for selected Cortex-A57 erratas.
+ERRATA_A57_859972 := 1
+ERRATA_A57_813419 := 1
+
+PLAT_INCLUDES := -Iplat/renesas/common/include/registers \
+ -Iplat/renesas/common/include \
+ -Iplat/renesas/common
+
+PLAT_BL_COMMON_SOURCES := drivers/renesas/common/iic_dvfs/iic_dvfs.c \
+ plat/renesas/common/rcar_common.c
+
+RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
+ drivers/arm/gic/v2/gicv2_main.c \
+ drivers/arm/gic/v2/gicv2_helpers.c \
+ plat/common/plat_gicv2.c
+
+BL2_SOURCES += ${RCAR_GIC_SOURCES} \
+ lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S \
+ ${LIBFDT_SRCS} \
+ common/desc_image_load.c \
+ plat/renesas/common/aarch64/platform_common.c \
+ plat/renesas/common/aarch64/plat_helpers.S \
+ plat/renesas/common/bl2_interrupt_error.c \
+ plat/renesas/common/bl2_secure_setting.c \
+ plat/renesas/common/plat_storage.c \
+ plat/renesas/common/bl2_plat_mem_params_desc.c \
+ plat/renesas/common/plat_image_load.c \
+ plat/renesas/common/bl2_cpg_init.c \
+ drivers/renesas/common/console/rcar_printf.c \
+ drivers/renesas/common/scif/scif.S \
+ drivers/renesas/common/common.c \
+ drivers/renesas/common/io/io_emmcdrv.c \
+ drivers/renesas/common/io/io_memdrv.c \
+ drivers/renesas/common/io/io_rcar.c \
+ drivers/renesas/common/auth/auth_mod.c \
+ drivers/renesas/common/rpc/rpc_driver.c \
+ drivers/renesas/common/dma/dma_driver.c \
+ drivers/renesas/common/avs/avs_driver.c \
+ drivers/renesas/common/delay/micro_delay.c \
+ drivers/renesas/common/emmc/emmc_interrupt.c \
+ drivers/renesas/common/emmc/emmc_utility.c \
+ drivers/renesas/common/emmc/emmc_mount.c \
+ drivers/renesas/common/emmc/emmc_init.c \
+ drivers/renesas/common/emmc/emmc_read.c \
+ drivers/renesas/common/emmc/emmc_cmd.c \
+ drivers/renesas/common/watchdog/swdt.c \
+ drivers/renesas/common/rom/rom_api.c \
+ drivers/io/io_storage.c
+
+BL31_SOURCES += ${RCAR_GIC_SOURCES} \
+ lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S \
+ plat/common/plat_psci_common.c \
+ plat/renesas/common/plat_topology.c \
+ plat/renesas/common/aarch64/plat_helpers.S \
+ plat/renesas/common/aarch64/platform_common.c \
+ plat/renesas/common/bl31_plat_setup.c \
+ plat/renesas/common/plat_pm.c \
+ drivers/renesas/common/console/rcar_console.S \
+ drivers/renesas/common/console/rcar_printf.c \
+ drivers/renesas/common/delay/micro_delay.c \
+ drivers/renesas/common/pwrc/call_sram.S \
+ drivers/renesas/common/pwrc/pwrc.c \
+ drivers/renesas/common/common.c \
+ drivers/arm/cci/cci.c
+
+include lib/xlat_tables_v2/xlat_tables.mk
+include drivers/auth/mbedtls/mbedtls_crypto.mk
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
diff --git a/plat/renesas/rcar/include/plat.ld.S b/plat/renesas/common/include/plat.ld.S
similarity index 100%
rename from plat/renesas/rcar/include/plat.ld.S
rename to plat/renesas/common/include/plat.ld.S
diff --git a/plat/renesas/rcar/include/plat_macros.S b/plat/renesas/common/include/plat_macros.S
similarity index 100%
rename from plat/renesas/rcar/include/plat_macros.S
rename to plat/renesas/common/include/plat_macros.S
diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/common/include/platform_def.h
similarity index 85%
rename from plat/renesas/rcar/include/platform_def.h
rename to plat/renesas/common/include/platform_def.h
index b7f0ca1..7378714 100644
--- a/plat/renesas/rcar/include/platform_def.h
+++ b/plat/renesas/common/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,20 +29,20 @@
/* Size of cacheable stacks */
#if IMAGE_BL1
#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE U(0x1000)
+#define PLATFORM_STACK_SIZE U(0x1000)
#else
-#define PLATFORM_STACK_SIZE U(0x440)
+#define PLATFORM_STACK_SIZE U(0x440)
#endif
#elif IMAGE_BL2
#if TRUSTED_BOARD_BOOT
-#define PLATFORM_STACK_SIZE U(0x1000)
+#define PLATFORM_STACK_SIZE U(0x1000)
#else
-#define PLATFORM_STACK_SIZE U(0x400)
+#define PLATFORM_STACK_SIZE U(0x400)
#endif
#elif IMAGE_BL31
-#define PLATFORM_STACK_SIZE U(0x400)
+#define PLATFORM_STACK_SIZE U(0x400)
#elif IMAGE_BL32
-#define PLATFORM_STACK_SIZE U(0x440)
+#define PLATFORM_STACK_SIZE U(0x440)
#endif
#define BL332_IMAGE_ID (NS_BL2U_IMAGE_ID + 1)
@@ -97,11 +97,13 @@
#define MAX_IO_DEVICES U(3)
#define MAX_IO_HANDLES U(4)
-/*******************************************************************************
+/*
+ ******************************************************************************
* BL2 specific defines.
- ******************************************************************************/
-/* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
- * size plus a little space for growth. */
+ ******************************************************************************
+ * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth.
+ */
#define RCAR_SYSRAM_BASE U(0xE6300000)
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
#define BL2_LIMIT U(0xE6320000)
@@ -121,17 +123,19 @@
#endif
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
-/*******************************************************************************
+/*
+ ******************************************************************************
* BL31 specific defines.
- ******************************************************************************/
-/* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
- * current BL3-1 debug size plus a little space for growth. */
+ ******************************************************************************
+ * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
+ * current BL3-1 debug size plus a little space for growth.
+ */
#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE)
#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \
RCAR_TRUSTED_SRAM_SIZE)
-#define RCAR_BL31_LOG_BASE (0x44040000)
-#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000)
-#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
+#define RCAR_BL31_LOG_BASE (0x44040000)
+#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000)
+#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
#define BL31_SRAM_BASE (DEVICE_SRAM_BASE)
#define BL31_SRAM_LIMIT (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
@@ -176,7 +180,7 @@
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
- * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * caches. Such alignment ensures that two mailboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h
similarity index 60%
rename from plat/renesas/rcar/include/rcar_def.h
rename to plat/renesas/common/include/rcar_def.h
index 0ffbfe9..6c5b295 100644
--- a/plat/renesas/rcar/include/rcar_def.h
+++ b/plat/renesas/common/include/rcar_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,13 +33,13 @@
#define DRAM1_SIZE U(0x80000000)
#define DRAM1_NS_BASE (DRAM1_BASE + U(0x10000000))
#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE)
-#define DRAM_40BIT_BASE ULL(0x0400000000)
-#define DRAM_40BIT_SIZE ULL(0x0400000000)
-#define DRAM_PROTECTED_BASE ULL(0x43F00000)
-#define DRAM_40BIT_PROTECTED_BASE ULL(0x0403F00000)
-#define DRAM_PROTECTED_SIZE ULL(0x03F00000)
-#define RCAR_BL31_CRASH_BASE U(0x4403F000)
-#define RCAR_BL31_CRASH_SIZE U(0x00001000)
+#define DRAM_40BIT_BASE ULL(0x0400000000)
+#define DRAM_40BIT_SIZE ULL(0x0400000000)
+#define DRAM_PROTECTED_BASE ULL(0x43F00000)
+#define DRAM_40BIT_PROTECTED_BASE ULL(0x0403F00000)
+#define DRAM_PROTECTED_SIZE ULL(0x03F00000)
+#define RCAR_BL31_CRASH_BASE U(0x4403F000)
+#define RCAR_BL31_CRASH_SIZE U(0x00001000)
/* Entrypoint mailboxes */
#define MBOX_BASE RCAR_SHARED_MEM_BASE
#define MBOX_SIZE 0x200
@@ -47,15 +47,19 @@
#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
#define BOOT_KIND_BASE (RCAR_SHARED_MEM_BASE + \
RCAR_SHARED_MEM_SIZE - 0x100)
-/* The number of regions like RO(code), coherent and data required by
- * different BL stages which need to be mapped in the MMU */
+/*
+ * The number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU
+ */
#if USE_COHERENT_MEM
#define RCAR_BL_REGIONS (3)
#else
#define RCAR_BL_REGIONS (2)
#endif
-/* The RCAR_MAX_MMAP_REGIONS depend on the number of entries in rcar_mmap[]
- * defined for each BL stage in rcar_common.c. */
+/*
+ * The RCAR_MAX_MMAP_REGIONS depends on the number of entries in rcar_mmap[]
+ * defined for each BL stage in rcar_common.c.
+ */
#if IMAGE_BL2
#define RCAR_MMAP_ENTRIES (9)
#endif
@@ -73,24 +77,24 @@
/* BL33 */
#define NS_IMAGE_OFFSET (DRAM1_BASE + U(0x09000000))
/* BL31 */
-#define RCAR_DEVICE_BASE DEVICE_RCAR_BASE
-#define RCAR_DEVICE_SIZE (0x1A000000)
-#define RCAR_LOG_RES_SIZE (512/8)
-#define RCAR_LOG_HEADER_SIZE (16)
-#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \
+#define RCAR_DEVICE_BASE DEVICE_RCAR_BASE
+#define RCAR_DEVICE_SIZE (0x1A000000)
+#define RCAR_LOG_RES_SIZE (64)
+#define RCAR_LOG_HEADER_SIZE (16)
+#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \
RCAR_LOG_RES_SIZE)
-#define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \
+#define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \
RCAR_LOG_OTHER_SIZE)
-#define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE
-#define AARCH64_SPACE_BASE ULL(0x00000000000)
-#define AARCH64_SPACE_SIZE ULL(0x10000000000)
+#define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE
+#define AARCH64_SPACE_BASE ULL(0x00000000000)
+#define AARCH64_SPACE_SIZE ULL(0x10000000000)
/* CCI related constants */
#define CCI500_BASE U(0xF1200000)
#define CCI500_CLUSTER0_SL_IFACE_IX (2)
#define CCI500_CLUSTER1_SL_IFACE_IX (3)
#define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3 (1)
#define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 (2)
-#define RCAR_CCI_BASE CCI500_BASE
+#define RCAR_CCI_BASE CCI500_BASE
/* GIC */
#define RCAR_GICD_BASE U(0xF1010000)
#define RCAR_GICR_BASE U(0xF1010000)
@@ -106,47 +110,47 @@
#define ARM_IRQ_SEC_SGI_5 U(13)
#define ARM_IRQ_SEC_SGI_6 U(14)
#define ARM_IRQ_SEC_SGI_7 U(15)
-#define ARM_IRQ_SEC_RPC U(70)
-#define ARM_IRQ_SEC_TIMER U(166)
-#define ARM_IRQ_SEC_TIMER_UP U(171)
-#define ARM_IRQ_SEC_WDT U(173)
-#define ARM_IRQ_SEC_CRYPT U(102)
-#define ARM_IRQ_SEC_CRYPT_SecPKA U(97)
-#define ARM_IRQ_SEC_CRYPT_PubPKA U(98)
+#define ARM_IRQ_SEC_RPC U(70)
+#define ARM_IRQ_SEC_TIMER U(166)
+#define ARM_IRQ_SEC_TIMER_UP U(171)
+#define ARM_IRQ_SEC_WDT U(173)
+#define ARM_IRQ_SEC_CRYPT U(102)
+#define ARM_IRQ_SEC_CRYPT_SecPKA U(97)
+#define ARM_IRQ_SEC_CRYPT_PubPKA U(98)
/* Timer control */
-#define RCAR_CNTC_BASE U(0xE6080000)
+#define RCAR_CNTC_BASE U(0xE6080000)
/* Reset */
-#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */
-#define RCAR_MODEMR U(0xE6160060) /* Mode pin */
-#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
-#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
-#define RCAR_SRESCR U(0xE6160110) /* Soft Power On Reset */
-#define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */
-#define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */
-#define RCAR_CA53PSTR U(0xE6151040) /* Power status A53 */
-#define RCAR_CA57PSTR U(0xE6152040) /* Power status A57 */
-#define RCAR_CA53CPU0CR U(0xE6151100) /* CPU control A53 */
-#define RCAR_CA57CPU0CR U(0xE6152100) /* CPU control A57 */
-#define RCAR_CA53CPUCMCR U(0xE6151184) /* Common power A53 */
-#define RCAR_CA57CPUCMCR U(0xE6152184) /* Common power A57 */
-#define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */
-#define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */
+#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */
+#define RCAR_MODEMR U(0xE6160060) /* Mode pin */
+#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
+#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
+#define RCAR_SRESCR U(0xE6160110) /* Soft Power On Reset */
+#define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */
+#define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */
+#define RCAR_CA53PSTR U(0xE6151040) /* Power status A53 */
+#define RCAR_CA57PSTR U(0xE6152040) /* Power status A57 */
+#define RCAR_CA53CPU0CR U(0xE6151100) /* CPU control A53 */
+#define RCAR_CA57CPU0CR U(0xE6152100) /* CPU control A57 */
+#define RCAR_CA53CPUCMCR U(0xE6151184) /* Common power A53 */
+#define RCAR_CA57CPUCMCR U(0xE6152184) /* Common power A57 */
+#define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */
+#define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */
/* SYSC */
-#define RCAR_PWRSR3 U(0xE6180140) /* Power stat A53-SCU */
-#define RCAR_PWRSR5 U(0xE61801C0) /* Power stat A57-SCU */
-#define RCAR_SYSCIER U(0xE618000C) /* Interrupt enable */
-#define RCAR_SYSCIMR U(0xE6180010) /* Interrupt mask */
-#define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
-#define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
-#define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
-#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutof A53-SCU */
-#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutof A57-SCU */
-#define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
-#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
-#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
-#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
+#define RCAR_PWRSR3 U(0xE6180140) /* Power stat A53-SCU */
+#define RCAR_PWRSR5 U(0xE61801C0) /* Power stat A57-SCU */
+#define RCAR_SYSCIER U(0xE618000C) /* Interrupt enable */
+#define RCAR_SYSCIMR U(0xE6180010) /* Interrupt mask */
+#define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
+#define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
+#define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
+#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutoff A53-SCU */
+#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutoff A57-SCU */
+#define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
+#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
+#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
+#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
/* Product register */
-#define RCAR_PRR U(0xFFF00044)
+#define RCAR_PRR U(0xFFF00044)
#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
#define RCAR_MAJOR_MASK U(0x000000F0)
#define RCAR_MINOR_MASK U(0x0000000F)
@@ -198,39 +202,39 @@
/* Memory mapped Generic timer interfaces */
#define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE
/* MODEMR PLL masks and bitfield values */
-#define CHECK_MD13_MD14 U(0x6000)
-#define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */
-#define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */
-#define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */
-#define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */
+#define CHECK_MD13_MD14 U(0x6000)
+#define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */
+#define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */
+#define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */
+#define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */
/* Frequency of EXTAL(Hz) */
-#define EXTAL_MD14_MD13_TYPE_0 U(8333300) /* MD14=0 MD13=0 */
-#define EXTAL_MD14_MD13_TYPE_1 U(10000000) /* MD14=0 MD13=1 */
-#define EXTAL_MD14_MD13_TYPE_2 U(12500000) /* MD14=1 MD13=0 */
-#define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */
-#define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */
+#define EXTAL_MD14_MD13_TYPE_0 U(8333300) /* MD14=0 MD13=0 */
+#define EXTAL_MD14_MD13_TYPE_1 U(10000000) /* MD14=0 MD13=1 */
+#define EXTAL_MD14_MD13_TYPE_2 U(12500000) /* MD14=1 MD13=0 */
+#define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */
+#define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */
#define EXTAL_EBISU U(24000000) /* Ebisu */
#define EXTAL_DRAAK U(24000000) /* Draak */
-/* CPG write protect registers */
-#define CPGWPR_PASSWORD (0x5A5AFFFFU)
-#define CPGWPCR_PASSWORD (0xA5A50000U)
+/* CPG write protect registers */
+#define CPGWPR_PASSWORD (0x5A5AFFFFU)
+#define CPGWPCR_PASSWORD (0xA5A50000U)
/* CA5x Debug Resource control registers */
-#define CPG_CA57DBGRCR (CPG_BASE + 0x2180U)
-#define CPG_CA53DBGRCR (CPG_BASE + 0x1180U)
-#define DBGCPUPREN ((uint32_t)1U << 19U)
-#define CPG_PLL0CR (CPG_BASE + 0x00D8U)
-#define CPG_PLL2CR (CPG_BASE + 0x002CU)
-#define CPG_PLL4CR (CPG_BASE + 0x01F4U)
+#define CPG_CA57DBGRCR (CPG_BASE + 0x2180U)
+#define CPG_CA53DBGRCR (CPG_BASE + 0x1180U)
+#define DBGCPUPREN ((uint32_t)1U << 19U)
+#define CPG_PLL0CR (CPG_BASE + 0x00D8U)
+#define CPG_PLL2CR (CPG_BASE + 0x002CU)
+#define CPG_PLL4CR (CPG_BASE + 0x01F4U)
#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
/* RST Registers */
-#define RST_BASE (0xE6160000U)
-#define RST_WDTRSTCR (RST_BASE + 0x0054U)
+#define RST_BASE (0xE6160000U)
+#define RST_WDTRSTCR (RST_BASE + 0x0054U)
#define RST_MODEMR (RST_BASE + 0x0060U)
-#define WDTRSTCR_PASSWORD (0xA55A0000U)
-#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
+#define WDTRSTCR_PASSWORD (0xA55A0000U)
+#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
/* MFIS Registers */
-#define MFISWPCNTR_PASSWORD (0xACCE0000U)
-#define MFISWPCNTR (0xE6260900U)
+#define MFISWPCNTR_PASSWORD (0xACCE0000U)
+#define MFISWPCNTR (0xE6260900U)
/* IPMMU registers */
#define IPMMU_MM_BASE (0xE67B0000U)
#define IPMMUMM_IMSCTLR (IPMMU_MM_BASE + 0x0500U)
@@ -263,8 +267,8 @@
#define IPMMU_DS1_BASE (0xE7740000U)
#define IPMMUDS1_IMSCTLR (IPMMU_DS1_BASE + 0x0500U)
/* ARMREG registers */
-#define P_ARMREG_SEC_CTRL (0xE62711F0U)
-#define P_ARMREG_SEC_CTRL_PROT (0x00000001U)
+#define P_ARMREG_SEC_CTRL (0xE62711F0U)
+#define P_ARMREG_SEC_CTRL_PROT (0x00000001U)
/* MIDR */
#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
@@ -279,28 +283,28 @@
#define RCAR_COLD_BOOT (0x00U)
#define RCAR_WARM_BOOT (0x01U)
#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
-#define KEEP10_MAGIC (0x55U)
+#define KEEP10_MAGIC (0x55U)
#endif
/* lossy registers */
-#define LOSSY_PARAMS_BASE (0x47FD7000U)
-#define AXI_DCMPAREACRA0 (0xE6784100U)
-#define AXI_DCMPAREACRB0 (0xE6784104U)
+#define LOSSY_PARAMS_BASE (0x47FD7000U)
+#define AXI_DCMPAREACRA0 (0xE6784100U)
+#define AXI_DCMPAREACRB0 (0xE6784104U)
#define LOSSY_ENABLE (0x80000000U)
#define LOSSY_DISABLE (0x00000000U)
#define LOSSY_FMT_YUVPLANAR (0x00000000U)
#define LOSSY_FMT_YUV422INTLV (0x20000000U)
#define LOSSY_FMT_ARGB8888 (0x40000000U)
-#define LOSSY_ST_ADDR0 (0x54000000U)
-#define LOSSY_END_ADDR0 (0x57000000U)
-#define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR
-#define LOSSY_ENA_DIS0 LOSSY_ENABLE
-#define LOSSY_ST_ADDR1 0x0U
-#define LOSSY_END_ADDR1 0x0U
-#define LOSSY_FMT1 LOSSY_FMT_ARGB8888
-#define LOSSY_ENA_DIS1 LOSSY_DISABLE
-#define LOSSY_ST_ADDR2 0x0U
-#define LOSSY_END_ADDR2 0x0U
-#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV
-#define LOSSY_ENA_DIS2 LOSSY_DISABLE
+#define LOSSY_ST_ADDR0 (0x54000000U)
+#define LOSSY_END_ADDR0 (0x57000000U)
+#define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR
+#define LOSSY_ENA_DIS0 LOSSY_ENABLE
+#define LOSSY_ST_ADDR1 0x0U
+#define LOSSY_END_ADDR1 0x0U
+#define LOSSY_FMT1 LOSSY_FMT_ARGB8888
+#define LOSSY_ENA_DIS1 LOSSY_DISABLE
+#define LOSSY_ST_ADDR2 0x0U
+#define LOSSY_END_ADDR2 0x0U
+#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV
+#define LOSSY_ENA_DIS2 LOSSY_DISABLE
#endif /* RCAR_DEF_H */
diff --git a/plat/renesas/rcar/include/rcar_private.h b/plat/renesas/common/include/rcar_private.h
similarity index 90%
rename from plat/renesas/rcar/include/rcar_private.h
rename to plat/renesas/common/include/rcar_private.h
index a76c023..36f4ca5 100644
--- a/plat/renesas/rcar/include/rcar_private.h
+++ b/plat/renesas/common/include/rcar_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,12 +7,12 @@
#ifndef RCAR_PRIVATE_H
#define RCAR_PRIVATE_H
-#include <platform_def.h>
-
#include <common/bl_common.h>
#include <lib/bakery_lock.h>
#include <lib/el3_runtime/cpu_data.h>
+#include <platform_def.h>
+
typedef volatile struct mailbox {
unsigned long value __aligned(CACHE_WRITEBACK_GRANULE);
} mailbox_t;
@@ -62,17 +62,18 @@
*/
#define rcar_lock_init(_lock_arg)
-#define rcar_lock_get(_lock_arg) \
- bakery_lock_get(_lock_arg, \
+#define rcar_lock_get(_lock_arg) \
+ bakery_lock_get(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
#define rcar_lock_release(_lock_arg) \
- bakery_lock_release(_lock_arg, \
+ bakery_lock_release(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
-/* Ensure that the size of the RCAR specific per-cpu data structure and the size
+/*
+ * Ensure that the size of the RCAR specific per-cpu data structure and the size
* of the memory allocated in generic per-cpu data for the platform are the same
*/
-CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(rcar_cpu_data_t),
+CASSERT(sizeof(rcar_cpu_data_t) == PLAT_PCPU_DATA_SIZE,
rcar_pcpu_data_size_mismatch);
#endif
/*
@@ -84,7 +85,7 @@
#if USE_COHERENT_MEM
, unsigned long coh_start, unsigned long coh_limit
#endif
- );
+ );
void rcar_setup_topology(void);
void rcar_cci_disable(void);
diff --git a/plat/renesas/rcar/include/rcar_version.h b/plat/renesas/common/include/rcar_version.h
similarity index 100%
rename from plat/renesas/rcar/include/rcar_version.h
rename to plat/renesas/common/include/rcar_version.h
diff --git a/plat/renesas/rcar/include/registers/axi_registers.h b/plat/renesas/common/include/registers/axi_registers.h
similarity index 100%
rename from plat/renesas/rcar/include/registers/axi_registers.h
rename to plat/renesas/common/include/registers/axi_registers.h
diff --git a/plat/renesas/rcar/include/registers/cpg_registers.h b/plat/renesas/common/include/registers/cpg_registers.h
similarity index 100%
rename from plat/renesas/rcar/include/registers/cpg_registers.h
rename to plat/renesas/common/include/registers/cpg_registers.h
diff --git a/plat/renesas/common/include/registers/lifec_registers.h b/plat/renesas/common/include/registers/lifec_registers.h
new file mode 100644
index 0000000..5f49e52
--- /dev/null
+++ b/plat/renesas/common/include/registers/lifec_registers.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef LIFEC_REGISTERS_H
+#define LIFEC_REGISTERS_H
+
+#define LIFEC_SEC_BASE (0xE6110000U)
+
+#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
+#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
+#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
+#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
+#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
+#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
+#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
+#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
+#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
+#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
+#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
+#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
+#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
+#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
+#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
+#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
+#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
+#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
+#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
+#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
+#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
+#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
+#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
+#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
+#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
+#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
+#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
+#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
+#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
+#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
+#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
+#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
+#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
+#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
+#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
+#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
+#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
+#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
+#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
+#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
+#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
+#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
+#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
+#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
+#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
+#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
+#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
+#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
+#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
+#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
+#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
+#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
+#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
+#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
+#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
+#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
+#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
+#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
+#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
+#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
+#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
+#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
+#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
+#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
+#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
+#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
+#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
+#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
+#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
+#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
+#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
+#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
+#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
+
+#define LIFEC_SAFE_BASE (0xE6120000U)
+#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
+#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
+#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
+#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
+#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
+#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
+#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
+#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
+#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
+#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
+#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
+#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
+#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
+#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
+#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
+#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
+#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
+#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
+#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
+#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
+#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
+#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
+#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
+#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
+#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
+#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
+#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
+#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
+#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
+#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
+#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
+#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
+#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
+#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
+#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
+#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
+#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
+#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
+#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
+#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
+#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
+#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
+#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
+#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
+#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
+#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
+#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
+#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
+#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
+#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
+#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
+#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
+#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
+#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
+#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
+#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
+
+#endif /* LIFEC_REGISTERS_H */
diff --git a/plat/renesas/rcar/plat_image_load.c b/plat/renesas/common/plat_image_load.c
similarity index 100%
rename from plat/renesas/rcar/plat_image_load.c
rename to plat/renesas/common/plat_image_load.c
diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/common/plat_pm.c
similarity index 93%
rename from plat/renesas/rcar/plat_pm.c
rename to plat/renesas/common/plat_pm.c
index 6fc47b9..6a9ad45 100644
--- a/plat/renesas/rcar/plat_pm.c
+++ b/plat/renesas/common/plat_pm.c
@@ -6,8 +6,6 @@
#include <errno.h>
-#include <platform_def.h>
-
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -19,17 +17,20 @@
#include <plat/common/platform.h>
#include "iic_dvfs.h"
+#include "platform_def.h"
#include "pwrc.h"
#include "rcar_def.h"
#include "rcar_private.h"
+#if RCAR_GEN3_ULCB
#include "ulcb_cpld.h"
+#endif /* RCAR_GEN3_ULCB */
-#define DVFS_SET_VID_0V (0x00)
-#define P_ALL_OFF (0x80)
-#define KEEPON_DDR1C (0x08)
-#define KEEPON_DDR0C (0x04)
-#define KEEPON_DDR1 (0x02)
-#define KEEPON_DDR0 (0x01)
+#define DVFS_SET_VID_0V (0x00)
+#define P_ALL_OFF (0x80)
+#define KEEPON_DDR1C (0x08)
+#define KEEPON_DDR0C (0x04)
+#define KEEPON_DDR1 (0x02)
+#define KEEPON_DDR0 (0x01)
#define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
#define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
@@ -200,20 +201,20 @@
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
if (error) {
- ERROR("Failed send KEEP10 magic ret=%d \n", error);
+ ERROR("Failed send KEEP10 magic ret=%d\n", error);
goto done;
}
error = rcar_iic_dvfs_receive(PMIC, BKUP_MODE_CNT, &mode);
if (error) {
- ERROR("Failed recieve BKUP_Mode_Cnt ret=%d \n", error);
+ ERROR("Failed receive BKUP_Mode_Cnt ret=%d\n", error);
goto done;
}
mode |= KEEPON_DDR1C | KEEPON_DDR0C | KEEPON_DDR1 | KEEPON_DDR0;
error = rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, mode);
if (error) {
- ERROR("Failed send KEEPON_DDRx ret=%d \n", error);
+ ERROR("Failed send KEEPON_DDRx ret=%d\n", error);
goto done;
}
@@ -292,7 +293,7 @@
.system_reset = rcar_system_reset,
.validate_power_state = rcar_validate_power_state,
#if RCAR_SYSTEM_SUSPEND
- .get_sys_suspend_power_state = rcar_get_sys_suspend_power_state,
+ .get_sys_suspend_power_state = rcar_get_sys_suspend_power_state,
#endif
};
diff --git a/plat/renesas/rcar/plat_storage.c b/plat/renesas/common/plat_storage.c
similarity index 95%
rename from plat/renesas/rcar/plat_storage.c
rename to plat/renesas/common/plat_storage.c
index 05e3d9f..6524561 100644
--- a/plat/renesas/rcar/plat_storage.c
+++ b/plat/renesas/common/plat_storage.c
@@ -1,23 +1,22 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <string.h>
-#include <platform_def.h>
-
#include <common/debug.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_storage.h>
#include <drivers/io/io_semihosting.h>
#include "io_common.h"
-#include "io_rcar.h"
#include "io_memdrv.h"
#include "io_emmcdrv.h"
#include "io_private.h"
+#include "io_rcar.h"
+#include <platform_def.h>
static uintptr_t emmcdrv_dev_handle;
static uintptr_t memdrv_dev_handle;
@@ -167,7 +166,7 @@
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
- int32_t(*check) (const uintptr_t spec);
+ int32_t (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
@@ -305,7 +304,7 @@
(uintptr_t) &bl338_cert_file_spec,
&open_rcar}, {
#else
- {
+ {
#endif
0, 0, 0}
};
@@ -322,16 +321,11 @@
0,
};
-static struct plat_io_policy drv_policies[]
- __attribute__ ((section(".data"))) = {
+static struct plat_io_policy drv_policies[] __attribute__ ((section(".data"))) = {
/* FLASH_DEV_ID */
- {
- &memdrv_dev_handle,
- (uintptr_t) &io_drv_spec_memdrv, &open_memmap,},
- /* EMMC_DEV_ID */
- {
- &emmcdrv_dev_handle,
- (uintptr_t) &io_drv_spec_emmcdrv, &open_emmcdrv,}
+ { &memdrv_dev_handle, (uintptr_t) &io_drv_spec_memdrv, &open_memmap, },
+ /* EMMC_DEV_ID */
+ { &emmcdrv_dev_handle, (uintptr_t) &io_drv_spec_emmcdrv, &open_emmcdrv, }
};
static int32_t open_rcar(const uintptr_t spec)
diff --git a/plat/renesas/rcar/plat_topology.c b/plat/renesas/common/plat_topology.c
similarity index 100%
rename from plat/renesas/rcar/plat_topology.c
rename to plat/renesas/common/plat_topology.c
diff --git a/plat/renesas/rcar/rcar_common.c b/plat/renesas/common/rcar_common.c
similarity index 100%
rename from plat/renesas/rcar/rcar_common.c
rename to plat/renesas/common/rcar_common.c
diff --git a/plat/renesas/rcar/bl2_secure_setting.c b/plat/renesas/rcar/bl2_secure_setting.c
deleted file mode 100644
index 7473df5..0000000
--- a/plat/renesas/rcar/bl2_secure_setting.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <lib/utils_def.h>
-
-#include "axi_registers.h"
-#include "lifec_registers.h"
-#include "micro_delay.h"
-
-static void lifec_security_setting(void);
-static void axi_security_setting(void);
-
-static const struct {
- uint32_t reg;
- uint32_t val;
-} lifec[] = {
- /** LIFEC0 (SECURITY) settings */
- /* Security attribute setting for master ports */
- /* Bit 0: ARM realtime core (Cortex-R7) master port */
- /* 0: Non-Secure */
- {
- SEC_SRC, 0x0000001EU},
- /** Security attribute setting for slave ports 0 to 15 */
- /* {SEC_SEL0, 0xFFFFFFFFU}, */
- /* {SEC_SEL1, 0xFFFFFFFFU}, */
- /* {SEC_SEL2, 0xFFFFFFFFU}, */
- /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports */
- /* 0: registers accessed from secure resource only */
- /* Bit 9: DBSC4 register access slave ports. */
- /* 0: registers accessed from secure resource only. */
-#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
- {
- SEC_SEL3, 0xFFF7FDFFU},
-#else
- {
- SEC_SEL3, 0xFFFFFFFFU},
-#endif
- /* {SEC_SEL4, 0xFFFFFFFFU}, */
- /* Bit 6: Boot ROM slave ports. */
- /* 0: registers accessed from secure resource only */
- {
- SEC_SEL5, 0xFFFFFFBFU},
- /* Bit13: SCEG PKA (secure APB) slave ports */
- /* 0: registers accessed from secure resource only */
- /* 1: Reserved[R-Car E3] */
- /* Bit12: SCEG PKA (public APB) slave ports */
- /* 0: registers accessed from secure resource only */
- /* 1: Reserved[R-Car E3] */
- /* Bit10: SCEG Secure Core slave ports */
- /* 0: registers accessed from secure resource only */
-#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
- {
- SEC_SEL6, 0xFFFFFBFFU},
-#else
- {
- SEC_SEL6, 0xFFFFCBFFU},
-#endif
- /* {SEC_SEL7, 0xFFFFFFFFU}, */
- /* {SEC_SEL8, 0xFFFFFFFFU}, */
- /* {SEC_SEL9, 0xFFFFFFFFU}, */
- /* {SEC_SEL10, 0xFFFFFFFFU}, */
- /* {SEC_SEL11, 0xFFFFFFFFU}, */
- /* {SEC_SEL12, 0xFFFFFFFFU}, */
- /* Bit22: RPC slave ports. */
- /* 0: registers accessed from secure resource only. */
-#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
- {SEC_SEL13, 0xFFBFFFFFU},
-#endif
- /* Bit27: System Timer (SCMT) slave ports */
- /* 0: registers accessed from secure resource only */
- /* Bit26: System Watchdog Timer (SWDT) slave ports */
- /* 0: registers accessed from secure resource only */
- {
- SEC_SEL14, 0xF3FFFFFFU},
- /* Bit13: RST slave ports. */
- /* 0: registers accessed from secure resource only */
- /* Bit 7: Life Cycle 0 slave ports */
- /* 0: registers accessed from secure resource only */
- {
- SEC_SEL15, 0xFFFFFF3FU},
- /** Security group 0 attribute setting for master ports 0 */
- /** Security group 1 attribute setting for master ports 0 */
- /* {SEC_GRP0CR0, 0x00000000U}, */
- /* {SEC_GRP1CR0, 0x00000000U}, */
- /** Security group 0 attribute setting for master ports 1 */
- /** Security group 1 attribute setting for master ports 1 */
- /* {SEC_GRP0CR1, 0x00000000U}, */
- /* {SEC_GRP1CR1, 0x00000000U}, */
- /** Security group 0 attribute setting for master ports 2 */
- /** Security group 1 attribute setting for master ports 2 */
- /* Bit17: SCEG Secure Core master ports. */
- /* SecurityGroup3 */
- {
- SEC_GRP0CR2, 0x00020000U}, {
- SEC_GRP1CR2, 0x00020000U},
- /** Security group 0 attribute setting for master ports 3 */
- /** Security group 1 attribute setting for master ports 3 */
- /* {SEC_GRP0CR3, 0x00000000U}, */
- /* {SEC_GRP1CR3, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 0 */
- /** Security group 1 attribute setting for slave ports 0 */
- /* {SEC_GRP0COND0, 0x00000000U}, */
- /* {SEC_GRP1COND0, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 1 */
- /** Security group 1 attribute setting for slave ports 1 */
- /* {SEC_GRP0COND1, 0x00000000U}, */
- /* {SEC_GRP1COND1, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 2 */
- /** Security group 1 attribute setting for slave ports 2 */
- /* {SEC_GRP0COND2, 0x00000000U}, */
- /* {SEC_GRP1COND2, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 3 */
- /** Security group 1 attribute setting for slave ports 3 */
- /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports. */
- /* SecurityGroup3 */
- /* Bit 9: DBSC4 register access slave ports. */
- /* SecurityGroup3 */
-#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
- {
- SEC_GRP0COND3, 0x00080200U}, {
- SEC_GRP1COND3, 0x00080200U},
-#else
- {
- SEC_GRP0COND3, 0x00000000U}, {
- SEC_GRP1COND3, 0x00000000U},
-#endif
- /** Security group 0 attribute setting for slave ports 4 */
- /** Security group 1 attribute setting for slave ports 4 */
- /* {SEC_GRP0COND4, 0x00000000U}, */
- /* {SEC_GRP1COND4, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 5 */
- /** Security group 1 attribute setting for slave ports 5 */
- /* Bit 6: Boot ROM slave ports */
- /* SecurityGroup3 */
- {
- SEC_GRP0COND5, 0x00000040U}, {
- SEC_GRP1COND5, 0x00000040U},
- /** Security group 0 attribute setting for slave ports 6 */
- /** Security group 1 attribute setting for slave ports 6 */
- /* Bit13: SCEG PKA (secure APB) slave ports */
- /* SecurityGroup3 */
- /* Reserved[R-Car E3] */
- /* Bit12: SCEG PKA (public APB) slave ports */
- /* SecurityGroup3 */
- /* Reserved[R-Car E3] */
- /* Bit10: SCEG Secure Core slave ports */
- /* SecurityGroup3 */
-#if RCAR_LSI == RCAR_E3
- {
- SEC_GRP0COND6, 0x00000400U}, {
- SEC_GRP1COND6, 0x00000400U},
-#else
- {
- SEC_GRP0COND6, 0x00003400U}, {
- SEC_GRP1COND6, 0x00003400U},
-#endif
- /** Security group 0 attribute setting for slave ports 7 */
- /** Security group 1 attribute setting for slave ports 7 */
- /* {SEC_GRP0COND7, 0x00000000U}, */
- /* {SEC_GRP1COND7, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 8 */
- /** Security group 1 attribute setting for slave ports 8 */
- /* {SEC_GRP0COND8, 0x00000000U}, */
- /* {SEC_GRP1COND8, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 9 */
- /** Security group 1 attribute setting for slave ports 9 */
- /* {SEC_GRP0COND9, 0x00000000U}, */
- /* {SEC_GRP1COND9, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 10 */
- /** Security group 1 attribute setting for slave ports 10 */
- /* {SEC_GRP0COND10, 0x00000000U}, */
- /* {SEC_GRP1COND10, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 11 */
- /** Security group 1 attribute setting for slave ports 11 */
- /* {SEC_GRP0COND11, 0x00000000U}, */
- /* {SEC_GRP1COND11, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 12 */
- /** Security group 1 attribute setting for slave ports 12 */
- /* {SEC_GRP0COND12, 0x00000000U}, */
- /* {SEC_GRP1COND12, 0x00000000U}, */
- /** Security group 0 attribute setting for slave ports 13 */
- /** Security group 1 attribute setting for slave ports 13 */
- /* Bit22: RPC slave ports. */
- /* SecurityGroup3 */
-#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
- {SEC_GRP0COND13, 0x00400000U},
- {SEC_GRP1COND13, 0x00400000U},
-#endif
- /** Security group 0 attribute setting for slave ports 14 */
- /** Security group 1 attribute setting for slave ports 14 */
- /* Bit26: System Timer (SCMT) slave ports */
- /* SecurityGroup3 */
- /* Bit27: System Watchdog Timer (SWDT) slave ports */
- /* SecurityGroup3 */
- {
- SEC_GRP0COND14, 0x0C000000U}, {
- SEC_GRP1COND14, 0x0C000000U},
- /** Security group 0 attribute setting for slave ports 15 */
- /** Security group 1 attribute setting for slave ports 15 */
- /* Bit13: RST slave ports */
- /* SecurityGroup3 */
- /* Bit 7: Life Cycle 0 slave ports */
- /* SecurityGroup3 */
- /* Bit 6: TDBG slave ports */
- /* SecurityGroup3 */
- {
- SEC_GRP0COND15, 0x000000C0U}, {
- SEC_GRP1COND15, 0x000000C0U},
- /** Security write protection attribute setting slave ports 0 */
- /* {SEC_READONLY0, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 1 */
- /* {SEC_READONLY1, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 2 */
- /* {SEC_READONLY2, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 3 */
- /* {SEC_READONLY3, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 4 */
- /* {SEC_READONLY4, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 5 */
- /* {SEC_READONLY5, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 6 */
- /* {SEC_READONLY6, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 7 */
- /* {SEC_READONLY7, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 8 */
- /* {SEC_READONLY8, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 9 */
- /* {SEC_READONLY9, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 10 */
- /* {SEC_READONLY10, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 11 */
- /* {SEC_READONLY11, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 12 */
- /* {SEC_READONLY12, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 13 */
- /* {SEC_READONLY13, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 14 */
- /* {SEC_READONLY14, 0x00000000U}, */
- /** Security write protection attribute setting slave ports 15 */
- /* {SEC_READONLY15, 0x00000000U} */
-};
-
-/* AXI settings */
-static const struct {
- uint32_t reg;
- uint32_t val;
-} axi[] = {
- /* DRAM protection */
- /* AXI dram protected area division */
- {
- AXI_DPTDIVCR0, 0x0E0403F0U}, {
- AXI_DPTDIVCR1, 0x0E0407E0U}, {
- AXI_DPTDIVCR2, 0x0E080000U}, {
- AXI_DPTDIVCR3, 0x0E080000U}, {
- AXI_DPTDIVCR4, 0x0E080000U}, {
- AXI_DPTDIVCR5, 0x0E080000U}, {
- AXI_DPTDIVCR6, 0x0E080000U}, {
- AXI_DPTDIVCR7, 0x0E080000U}, {
- AXI_DPTDIVCR8, 0x0E080000U}, {
- AXI_DPTDIVCR9, 0x0E080000U}, {
- AXI_DPTDIVCR10, 0x0E080000U}, {
- AXI_DPTDIVCR11, 0x0E080000U}, {
- AXI_DPTDIVCR12, 0x0E080000U}, {
- AXI_DPTDIVCR13, 0x0E080000U}, {
- AXI_DPTDIVCR14, 0x0E080000U},
- /* AXI dram protected area setting */
- {
- AXI_DPTCR0, 0x0E000000U}, {
- AXI_DPTCR1, 0x0E000E0EU}, {
- AXI_DPTCR2, 0x0E000000U}, {
- AXI_DPTCR3, 0x0E000000U}, {
- AXI_DPTCR4, 0x0E000000U}, {
- AXI_DPTCR5, 0x0E000000U}, {
- AXI_DPTCR6, 0x0E000000U}, {
- AXI_DPTCR7, 0x0E000000U}, {
- AXI_DPTCR8, 0x0E000000U}, {
- AXI_DPTCR9, 0x0E000000U}, {
- AXI_DPTCR10, 0x0E000000U}, {
- AXI_DPTCR11, 0x0E000000U}, {
- AXI_DPTCR12, 0x0E000000U}, {
- AXI_DPTCR13, 0x0E000000U}, {
- AXI_DPTCR14, 0x0E000000U}, {
- AXI_DPTCR15, 0x0E000000U},
- /* SRAM ptotection */
- /* AXI sram protected area division */
- {
- AXI_SPTDIVCR0, 0x0E0E6304U}, {
- AXI_SPTDIVCR1, 0x0E0E6360U}, {
- AXI_SPTDIVCR2, 0x0E0E6360U}, {
- AXI_SPTDIVCR3, 0x0E0E6360U}, {
- AXI_SPTDIVCR4, 0x0E0E6360U}, {
- AXI_SPTDIVCR5, 0x0E0E6360U}, {
- AXI_SPTDIVCR6, 0x0E0E6360U}, {
- AXI_SPTDIVCR7, 0x0E0E6360U}, {
- AXI_SPTDIVCR8, 0x0E0E6360U}, {
- AXI_SPTDIVCR9, 0x0E0E6360U}, {
- AXI_SPTDIVCR10, 0x0E0E6360U}, {
- AXI_SPTDIVCR11, 0x0E0E6360U}, {
- AXI_SPTDIVCR12, 0x0E0E6360U}, {
- AXI_SPTDIVCR13, 0x0E0E6360U}, {
- AXI_SPTDIVCR14, 0x0E0E6360U},
- /* AXI sram protected area setting */
- {
- AXI_SPTCR0, 0x0E000E0EU}, {
- AXI_SPTCR1, 0x0E000000U}, {
- AXI_SPTCR2, 0x0E000000U}, {
- AXI_SPTCR3, 0x0E000000U}, {
- AXI_SPTCR4, 0x0E000000U}, {
- AXI_SPTCR5, 0x0E000000U}, {
- AXI_SPTCR6, 0x0E000000U}, {
- AXI_SPTCR7, 0x0E000000U}, {
- AXI_SPTCR8, 0x0E000000U}, {
- AXI_SPTCR9, 0x0E000000U}, {
- AXI_SPTCR10, 0x0E000000U}, {
- AXI_SPTCR11, 0x0E000000U}, {
- AXI_SPTCR12, 0x0E000000U}, {
- AXI_SPTCR13, 0x0E000000U}, {
- AXI_SPTCR14, 0x0E000000U}, {
- AXI_SPTCR15, 0x0E000000U}
-};
-
-static void lifec_security_setting(void)
-{
- uint32_t i;
-
- for (i = 0; i < ARRAY_SIZE(lifec); i++)
- mmio_write_32(lifec[i].reg, lifec[i].val);
-}
-
-/* SRAM/DRAM protection setting */
-static void axi_security_setting(void)
-{
- uint32_t i;
-
- for (i = 0; i < ARRAY_SIZE(axi); i++)
- mmio_write_32(axi[i].reg, axi[i].val);
-}
-
-void bl2_secure_setting(void)
-{
- const uint32_t delay = 10;
-
- lifec_security_setting();
- axi_security_setting();
- rcar_micro_delay(delay);
-
- return;
-}
diff --git a/plat/renesas/rcar/include/registers/lifec_registers.h b/plat/renesas/rcar/include/registers/lifec_registers.h
deleted file mode 100644
index de78760..0000000
--- a/plat/renesas/rcar/include/registers/lifec_registers.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef LIFEC_REGISTERS_H
-#define LIFEC_REGISTERS_H
-
-#define LIFEC_SEC_BASE (0xE6110000U)
-
-#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
-#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
-#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
-#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
-#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
-#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
-#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
-#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
-#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
-#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
-#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
-#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
-#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
-#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
-#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
-#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
-#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
-#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
-#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
-#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
-#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
-#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
-#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
-#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
-#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
-#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
-#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
-#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
-#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
-#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
-#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
-#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
-#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
-#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
-#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
-#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
-#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
-#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
-#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
-#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
-#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
-#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
-#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
-#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
-#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
-#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
-#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
-#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
-#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
-#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
-#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
-#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
-#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
-#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
-#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
-#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
-#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
-#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
-#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
-#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
-#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
-#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
-#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
-#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
-#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
-#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
-#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
-#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
-#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
-#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
-#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
-#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
-#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
-
-#define LIFEC_SAFE_BASE (0xE6120000U)
-#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
-#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
-#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
-#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
-#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
-#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
-#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
-#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
-#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
-#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
-#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
-#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
-#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
-#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
-#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
-#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
-#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
-#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
-#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
-#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
-#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
-#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
-#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
-#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
-#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
-#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
-#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
-#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
-#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
-#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
-#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
-#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
-#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
-#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
-#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
-#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
-#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
-#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
-#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
-#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
-#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
-#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
-#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
-#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
-#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
-#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
-#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
-#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
-#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
-#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
-#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
-#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
-#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
-#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
-#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
-#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
-
-#endif /* LIFEC_REGISTERS_H */
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 4c41dd3..5e4978c 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -1,56 +1,10 @@
#
-# Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-PROGRAMMABLE_RESET_ADDRESS := 0
-COLD_BOOT_SINGLE_CPU := 1
-ARM_CCI_PRODUCT_ID := 500
-TRUSTED_BOARD_BOOT := 1
-RESET_TO_BL31 := 1
-GENERATE_COT := 1
-BL2_AT_EL3 := 1
-ENABLE_SVE_FOR_NS := 0
-MULTI_CONSOLE_API := 1
-
-CRASH_REPORTING := 1
-HANDLE_EA_EL3_FIRST := 1
-
-$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
-
-ifeq (${SPD},none)
- SPD_NONE:=1
- $(eval $(call add_define,SPD_NONE))
-endif
-
-# LSI setting common define
-RCAR_H3:=0
-RCAR_M3:=1
-RCAR_M3N:=2
-RCAR_E3:=3
-RCAR_H3N:=4
-RCAR_D3:=5
-RCAR_V3M:=6
-RCAR_AUTO:=99
-$(eval $(call add_define,RCAR_H3))
-$(eval $(call add_define,RCAR_M3))
-$(eval $(call add_define,RCAR_M3N))
-$(eval $(call add_define,RCAR_E3))
-$(eval $(call add_define,RCAR_H3N))
-$(eval $(call add_define,RCAR_D3))
-$(eval $(call add_define,RCAR_V3M))
-$(eval $(call add_define,RCAR_AUTO))
-RCAR_CUT_10:=0
-RCAR_CUT_11:=1
-RCAR_CUT_13:=3
-RCAR_CUT_20:=10
-RCAR_CUT_30:=20
-$(eval $(call add_define,RCAR_CUT_10))
-$(eval $(call add_define,RCAR_CUT_11))
-$(eval $(call add_define,RCAR_CUT_13))
-$(eval $(call add_define,RCAR_CUT_20))
-$(eval $(call add_define,RCAR_CUT_30))
+include plat/renesas/common/common.mk
ifndef LSI
$(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI")
@@ -339,105 +293,32 @@
endif
endif
-# Enable workarounds for selected Cortex-A53 erratas.
-ERRATA_A53_835769 := 1
-ERRATA_A53_843419 := 1
-ERRATA_A53_855873 := 1
-
-# Enable workarounds for selected Cortex-A57 erratas.
-ERRATA_A57_859972 := 1
-ERRATA_A57_813419 := 1
-
include drivers/renesas/rcar/ddr/ddr.mk
include drivers/renesas/rcar/qos/qos.mk
include drivers/renesas/rcar/pfc/pfc.mk
include lib/libfdt/libfdt.mk
-PLAT_INCLUDES := -Idrivers/renesas/rcar/ddr \
+PLAT_INCLUDES += -Idrivers/renesas/rcar/ddr \
-Idrivers/renesas/rcar/qos \
- -Idrivers/renesas/rcar/iic_dvfs \
-Idrivers/renesas/rcar/board \
-Idrivers/renesas/rcar/cpld/ \
- -Idrivers/renesas/rcar/avs \
- -Idrivers/renesas/rcar/delay \
- -Idrivers/renesas/rcar/rom \
- -Idrivers/renesas/rcar/scif \
- -Idrivers/renesas/rcar/emmc \
- -Idrivers/renesas/rcar/pwrc \
- -Idrivers/renesas/rcar/io \
- -Iplat/renesas/rcar/include/registers \
- -Iplat/renesas/rcar/include \
- -Iplat/renesas/rcar
+ -Idrivers/renesas/common \
+ -Idrivers/renesas/common/iic_dvfs \
+ -Idrivers/renesas/common/avs \
+ -Idrivers/renesas/common/delay \
+ -Idrivers/renesas/common/rom \
+ -Idrivers/renesas/common/scif \
+ -Idrivers/renesas/common/emmc \
+ -Idrivers/renesas/common/pwrc \
+ -Idrivers/renesas/common/io
-PLAT_BL_COMMON_SOURCES := drivers/renesas/rcar/iic_dvfs/iic_dvfs.c \
- plat/renesas/rcar/rcar_common.c
-
-RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
- plat/common/plat_gicv2.c
-
-BL2_SOURCES += ${RCAR_GIC_SOURCES} \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
- ${LIBFDT_SRCS} \
- common/desc_image_load.c \
- plat/renesas/rcar/aarch64/platform_common.c \
- plat/renesas/rcar/aarch64/plat_helpers.S \
- plat/renesas/rcar/bl2_interrupt_error.c \
- plat/renesas/rcar/bl2_secure_setting.c \
- plat/renesas/rcar/bl2_plat_setup.c \
- plat/renesas/rcar/plat_storage.c \
- plat/renesas/rcar/bl2_plat_mem_params_desc.c \
- plat/renesas/rcar/plat_image_load.c \
- plat/renesas/rcar/bl2_cpg_init.c \
- drivers/renesas/rcar/console/rcar_printf.c \
- drivers/renesas/rcar/scif/scif.S \
- drivers/renesas/rcar/common.c \
- drivers/renesas/rcar/io/io_emmcdrv.c \
- drivers/renesas/rcar/io/io_memdrv.c \
- drivers/renesas/rcar/io/io_rcar.c \
- drivers/renesas/rcar/auth/auth_mod.c \
- drivers/renesas/rcar/rpc/rpc_driver.c \
- drivers/renesas/rcar/dma/dma_driver.c \
- drivers/renesas/rcar/avs/avs_driver.c \
- drivers/renesas/rcar/delay/micro_delay.c \
- drivers/renesas/rcar/emmc/emmc_interrupt.c \
- drivers/renesas/rcar/emmc/emmc_utility.c \
- drivers/renesas/rcar/emmc/emmc_mount.c \
- drivers/renesas/rcar/emmc/emmc_init.c \
- drivers/renesas/rcar/emmc/emmc_read.c \
- drivers/renesas/rcar/emmc/emmc_cmd.c \
- drivers/renesas/rcar/watchdog/swdt.c \
- drivers/renesas/rcar/rom/rom_api.c \
- drivers/renesas/rcar/board/board.c \
- drivers/io/io_storage.c
-
-BL31_SOURCES += ${RCAR_GIC_SOURCES} \
- lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S \
- plat/common/plat_psci_common.c \
- plat/renesas/rcar/plat_topology.c \
- plat/renesas/rcar/aarch64/plat_helpers.S \
- plat/renesas/rcar/aarch64/platform_common.c \
- plat/renesas/rcar/bl31_plat_setup.c \
- plat/renesas/rcar/plat_pm.c \
- drivers/renesas/rcar/console/rcar_console.S \
- drivers/renesas/rcar/console/rcar_printf.c \
- drivers/renesas/rcar/delay/micro_delay.c \
- drivers/renesas/rcar/pwrc/call_sram.S \
- drivers/renesas/rcar/pwrc/pwrc.c \
- drivers/renesas/rcar/common.c \
- drivers/arm/cci/cci.c
+BL2_SOURCES += plat/renesas/rcar/bl2_plat_setup.c \
+ drivers/renesas/rcar/board/board.c
ifeq (${RCAR_GEN3_ULCB},1)
BL31_SOURCES += drivers/renesas/rcar/cpld/ulcb_cpld.c
endif
-include lib/xlat_tables_v2/xlat_tables.mk
-include drivers/auth/mbedtls/mbedtls_crypto.mk
-PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
-
# build the layout images for the bootrom and the necessary srecords
rcar: rcar_layout_tool rcar_srecord
distclean realclean clean: clean_layout_tool clean_srecord
diff --git a/plat/rockchip/common/rockchip_stack_protector.c b/plat/rockchip/common/rockchip_stack_protector.c
new file mode 100644
index 0000000..1898977
--- /dev/null
+++ b/plat/rockchip/common/rockchip_stack_protector.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <plat/common/platform.h>
+
+#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
+
+u_register_t plat_get_stack_protector_canary(void)
+{
+ /*
+ * Ideally, a random number should be returned instead of the
+ * combination of a timer's value and a compile-time constant.
+ * As the virt platform does not have any random number generator,
+ * this is better than nothing but not necessarily really secure.
+ */
+ return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
+}
+
diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk
index 87cf187..b1bb807 100644
--- a/plat/rockchip/px30/platform.mk
+++ b/plat/rockchip/px30/platform.mk
@@ -36,6 +36,10 @@
lib/xlat_tables/aarch64/xlat_tables.c \
plat/common/plat_psci_common.c
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
+endif
+
BL31_SOURCES += ${RK_GIC_SOURCES} \
common/desc_image_load.c \
drivers/arm/cci/cci.c \
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 0219422..5a307e4 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -35,6 +35,10 @@
plat/common/aarch64/crash_console_helpers.S \
plat/common/plat_psci_common.c
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
+endif
+
BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/arm/cci/cci.c \
drivers/ti/uart/aarch64/16550_console.S \
diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index cb0cb89..e787293 100644
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -33,6 +33,10 @@
plat/common/aarch64/crash_console_helpers.S \
plat/common/plat_psci_common.c
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
+endif
+
BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/arm/cci/cci.c \
drivers/ti/uart/aarch64/16550_console.S \
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index a658fb2..aba67c2 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -38,6 +38,10 @@
plat/common/aarch64/crash_console_helpers.S \
plat/common/plat_psci_common.c
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += ${RK_PLAT_COMMON}/rockchip_stack_protector.c
+endif
+
BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/arm/cci/cci.c \
drivers/ti/uart/aarch64/16550_console.S \
diff --git a/plat/ti/k3/board/generic/board.mk b/plat/ti/k3/board/generic/board.mk
index a342214..ef74cd6 100644
--- a/plat/ti/k3/board/generic/board.mk
+++ b/plat/ti/k3/board/generic/board.mk
@@ -13,5 +13,12 @@
K3_HW_CONFIG_BASE ?= 0x82000000
$(eval $(call add_define,K3_HW_CONFIG_BASE))
+# Define sec_proxy usage as the full prioritized communication scheme
+K3_SEC_PROXY_LITE := 0
+$(eval $(call add_define,K3_SEC_PROXY_LITE))
+
+# System coherency is managed in hardware
+USE_COHERENT_MEM := 1
+
PLAT_INCLUDES += \
-Iplat/ti/k3/board/generic/include \
diff --git a/plat/ti/k3/board/lite/board.mk b/plat/ti/k3/board/lite/board.mk
new file mode 100644
index 0000000..76246be
--- /dev/null
+++ b/plat/ti/k3/board/lite/board.mk
@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL32_BASE ?= 0x9e800000
+$(eval $(call add_define,BL32_BASE))
+
+PRELOADED_BL33_BASE ?= 0x80080000
+$(eval $(call add_define,PRELOADED_BL33_BASE))
+
+K3_HW_CONFIG_BASE ?= 0x82000000
+$(eval $(call add_define,K3_HW_CONFIG_BASE))
+
+# Define sec_proxy usage as the lite version
+K3_SEC_PROXY_LITE := 1
+$(eval $(call add_define,K3_SEC_PROXY_LITE))
+
+# We dont have system level coherency capability
+USE_COHERENT_MEM := 0
+
+PLAT_INCLUDES += \
+ -Iplat/ti/k3/board/lite/include \
diff --git a/plat/ti/k3/board/lite/include/board_def.h b/plat/ti/k3/board/lite/include/board_def.h
new file mode 100644
index 0000000..7c7ea62
--- /dev/null
+++ b/plat/ti/k3/board/lite/include/board_def.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOARD_DEF_H
+#define BOARD_DEF_H
+
+#include <lib/utils_def.h>
+
+/* The ports must be in order and contiguous */
+#define K3_CLUSTER0_CORE_COUNT U(4)
+#define K3_CLUSTER1_CORE_COUNT U(0)
+#define K3_CLUSTER2_CORE_COUNT U(0)
+#define K3_CLUSTER3_CORE_COUNT U(0)
+
+/*
+ * This RAM will be used for the bootloader including code, bss, and stacks.
+ * It may need to be increased if BL31 grows in size.
+ * Current computation assumes data structures necessary for GIC and ARM for
+ * a single cluster of 4 processor.
+ */
+#define SEC_SRAM_BASE 0x70000000 /* Base of SRAM */
+#define SEC_SRAM_SIZE 0x0001a000 /* 104k */
+
+#define PLAT_MAX_OFF_STATE U(2)
+#define PLAT_MAX_RET_STATE U(1)
+
+#define PLAT_PROC_START_ID 32
+#define PLAT_PROC_DEVICE_START_ID 135
+#define PLAT_CLUSTER_DEVICE_START_ID 134
+
+#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
index ee1eecf..a0bfdee 100644
--- a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
+++ b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
@@ -97,11 +97,16 @@
.data_end_offset = 0x3C,
},
.threads = {
+#if !K3_SEC_PROXY_LITE
SP_THREAD(SP_NOTIFY),
SP_THREAD(SP_RESPONSE),
SP_THREAD(SP_HIGH_PRIORITY),
SP_THREAD(SP_LOW_PRIORITY),
SP_THREAD(SP_NOTIFY_RESP),
+#else
+ SP_THREAD(SP_RESPONSE),
+ SP_THREAD(SP_HIGH_PRIORITY),
+#endif /* K3_SEC_PROXY_LITE */
},
};
@@ -261,9 +266,14 @@
/*
* 'data_reg' indicates next register to write. If we did not already
* write on tx complete reg(last reg), we must do so for transmit
+ * In addition, we also need to make sure all intermediate data
+ * registers(if any required), are reset to 0 for TISCI backward
+ * compatibility to be maintained.
*/
- if (data_reg <= spm.desc.data_end_offset)
- mmio_write_32(spt->data + spm.desc.data_end_offset, 0);
+ while (data_reg <= spm.desc.data_end_offset) {
+ mmio_write_32(spt->data + data_reg, 0);
+ data_reg += sizeof(uint32_t);
+ }
VERBOSE("Message successfully sent on thread %s\n", spt->name);
diff --git a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
index 6c4f5df..f4b0b4b 100644
--- a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
+++ b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
@@ -16,13 +16,28 @@
* enum k3_sec_proxy_chan_id - Secure Proxy thread IDs
*
* These the available IDs used in k3_sec_proxy_{send,recv}()
+ * There are two schemes we use:
+ * * if K3_SEC_PROXY_LITE = 1, we just have two threads to talk
+ * * if K3_SEC_PROXY_LITE = 0, we have the full fledged
+ * communication scheme available.
*/
enum k3_sec_proxy_chan_id {
+#if !K3_SEC_PROXY_LITE
SP_NOTIFY = 0,
SP_RESPONSE,
SP_HIGH_PRIORITY,
SP_LOW_PRIORITY,
SP_NOTIFY_RESP,
+#else
+ SP_RESPONSE = 8,
+ /*
+ * Note: TISCI documentation indicates "low priority", but in reality
+ * with a single thread, there is no low or high priority.. This usage
+ * is more appropriate for TF-A since we can reduce the churn as a
+ * result.
+ */
+ SP_HIGH_PRIORITY,
+#endif /* K3_SEC_PROXY_LITE */
};
/**
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
index e390efe..2c3313c43 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
@@ -1163,6 +1163,7 @@
ERROR("Message alloc failed (%d)\n", ret);
return ret;
}
+ req.domain = TI_SCI_DOMAIN_FULL_SOC_RESET;
ret = ti_sci_do_xfer(&xfer);
if (ret) {
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
index 2d23f9a..310bf45 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
@@ -95,12 +95,15 @@
/**
* struct ti_sci_msg_req_reboot - Reboot the SoC
* @hdr: Generic Header
+ * @domain: Domain to be reset, 0 for full SoC reboot
*
* Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
* ACK/NACK message.
*/
struct ti_sci_msg_req_reboot {
struct ti_sci_msg_hdr hdr;
+#define TI_SCI_DOMAIN_FULL_SOC_RESET 0x0
+ uint8_t domain;
} __packed;
/**
diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c
index 8bd7362..ac4e60e 100644
--- a/plat/ti/k3/common/k3_bl31_setup.c
+++ b/plat/ti/k3/common/k3_bl31_setup.c
@@ -13,6 +13,7 @@
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
+#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <k3_console.h>
@@ -23,6 +24,7 @@
const mmap_region_t plat_k3_mmap[] = {
MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_RT_BASE, SEC_PROXY_RT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_SCFG_BASE, SEC_PROXY_SCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SEC_PROXY_DATA_BASE, SEC_PROXY_DATA_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
@@ -127,6 +129,38 @@
unsigned int plat_get_syscnt_freq2(void)
{
+ uint32_t gtc_freq;
+ uint32_t gtc_ctrl;
+
+ /* Lets try and provide basic diagnostics - cost is low */
+ gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET);
+ /* Did the bootloader fail to enable timer and OS guys are confused? */
+ if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) {
+ ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n");
+ }
+ /*
+ * If debug will not pause time, we will have issues like
+ * drivers timing out while debugging, in cases of OS like Linux,
+ * RCU stall errors, which can be hard to differentiate vs real issues.
+ */
+ if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) {
+ WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n");
+ }
+
+ gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET);
+ /* Many older bootloaders may have missed programming FID0 register */
+ if (gtc_freq != 0U) {
+ return gtc_freq;
+ }
+
+ /*
+ * We could have just warned about this, but this can have serious
+ * hard to debug side effects if we are NOT sure what the actual
+ * frequency is. Lets make sure people don't miss this.
+ */
+ ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n",
+ SYS_COUNTER_FREQ_IN_TICKS);
+
return SYS_COUNTER_FREQ_IN_TICKS;
}
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index c00262b..ab7366b 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -11,9 +11,8 @@
# We can choose where a core starts executing
PROGRAMMABLE_RESET_ADDRESS:= 1
-# System coherency is managed in hardware
+# ARM coherency is managed in hardware
WARMBOOT_ENABLE_DCACHE_EARLY := 1
-USE_COHERENT_MEM := 1
# A53 erratum for SoC. (enable them all)
ERRATA_A53_826319 := 1
@@ -21,9 +20,11 @@
ERRATA_A53_836870 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+ERRATA_A53_1530924 := 1
# A72 Erratum for SoC
ERRATA_A72_859971 := 1
+ERRATA_A72_1319367 := 1
CRASH_REPORTING := 1
HANDLE_EA_EL3_FIRST := 1
diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index 98db626..f12fb0b 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -150,15 +150,33 @@
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE)
+
+#define K3_GTC_BASE 0x00A90000
+/* We just need 20 byte offset, but simpler to just remap the 64K page in */
+#define K3_GTC_SIZE 0x10000
+#define K3_GTC_CNTCR_OFFSET 0x00
+#define K3_GTC_CNTCR_EN_MASK 0x01
+#define K3_GTC_CNTCR_HDBG_MASK 0x02
+#define K3_GTC_CNTFID0_OFFSET 0x20
+
#define K3_GIC_BASE 0x01800000
#define K3_GIC_SIZE 0x200000
+#if !K3_SEC_PROXY_LITE
#define SEC_PROXY_DATA_BASE 0x32C00000
#define SEC_PROXY_DATA_SIZE 0x80000
#define SEC_PROXY_SCFG_BASE 0x32800000
#define SEC_PROXY_SCFG_SIZE 0x80000
#define SEC_PROXY_RT_BASE 0x32400000
#define SEC_PROXY_RT_SIZE 0x80000
+#else
+#define SEC_PROXY_DATA_BASE 0x4D000000
+#define SEC_PROXY_DATA_SIZE 0x80000
+#define SEC_PROXY_SCFG_BASE 0x4A400000
+#define SEC_PROXY_SCFG_SIZE 0x80000
+#define SEC_PROXY_RT_BASE 0x4A600000
+#define SEC_PROXY_RT_SIZE 0x80000
+#endif /* K3_SEC_PROXY_LITE */
#define SEC_PROXY_TIMEOUT_US 1000000
#define SEC_PROXY_MAX_MESSAGE_SIZE 56
diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index c83d25b..5dcceae 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c
@@ -18,6 +18,8 @@
#include "pm_ipi.h"
+#define ERROR_CODE_MASK 0xFFFFU
+
DEFINE_BAKERY_LOCK(pm_secure_lock);
/**
@@ -230,7 +232,7 @@
if (ret != PM_RET_SUCCESS)
goto unlock;
- ret = pm_ipi_buff_read(proc, value, count);
+ ret = ERROR_CODE_MASK & (pm_ipi_buff_read(proc, value, count));
unlock:
bakery_lock_release(&pm_secure_lock);
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 03b7fbb..5e870ff 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -34,8 +34,9 @@
{
assert(sec_state_is_valid(type));
- if (type == NON_SECURE)
+ if (type == NON_SECURE) {
return &bl33_image_ep_info;
+ }
return &bl32_image_ep_info;
}
@@ -68,8 +69,9 @@
VERSAL_UART_CLOCK,
VERSAL_UART_BAUDRATE,
&versal_runtime_console);
- if (rc == 0)
+ if (rc == 0) {
panic();
+ }
console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME);
@@ -97,7 +99,7 @@
enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
&bl33_image_ep_info,
atf_handoff_addr);
- if (ret == FSBL_HANDOFF_NO_STRUCT) {
+ if (ret == FSBL_HANDOFF_NO_STRUCT || ret == FSBL_HANDOFF_INVAL_STRUCT) {
bl31_set_default_config();
} else if (ret != FSBL_HANDOFF_SUCCESS) {
panic();
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 3955085..fda42df 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -59,7 +59,9 @@
plat_versal_gic_cpuif_disable();
- plat_versal_gic_save();
+ if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
+ plat_versal_gic_save();
+ }
state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ?
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
@@ -99,11 +101,9 @@
/* APU was turned off, so restore GIC context */
if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
plat_versal_gic_resume();
- plat_versal_gic_cpuif_enable();
- } else {
- plat_versal_gic_cpuif_enable();
- plat_versal_gic_pcpu_init();
}
+
+ plat_versal_gic_cpuif_enable();
}
void versal_pwr_domain_on_finish(const psci_power_state_t *target_state)
diff --git a/plat/xilinx/versal/plat_versal.c b/plat/xilinx/versal/plat_versal.c
index a080a76..107eae6 100644
--- a/plat/xilinx/versal/plat_versal.c
+++ b/plat/xilinx/versal/plat_versal.c
@@ -9,11 +9,13 @@
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
- if (mpidr & MPIDR_CLUSTER_MASK)
+ if (mpidr & MPIDR_CLUSTER_MASK) {
return -1;
+ }
- if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT)
+ if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT) {
return -1;
+ }
return versal_calc_core_pos(mpidr);
}
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c
index dbe94e6..eae881e 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.c
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2020, Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <plat/common/platform.h>
#include "pm_api_sys.h"
#include "pm_client.h"
+#include "pm_defs.h"
/*********************************************************************
* Target module IDs macros
@@ -84,6 +85,22 @@
}
/**
+ * pm_init_finalize() - Call to notify PMC PM firmware that master has power
+ * management enabled and that it has finished its
+ * initialization
+ *
+ * @return Status returned by the PMU firmware
+ */
+enum pm_ret_status pm_init_finalize(void)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, PM_INIT_FINALIZE);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
+}
+
+/**
* pm_self_suspend() - PM call for processor to suspend itself
* @nid Node id of the processor or subsystem
* @latency Requested maximum wakeup latency (not supported)
@@ -554,6 +571,22 @@
return pm_ipi_send_sync(primary_proc, payload, parent, 1);
}
+/**
+ * pm_clock_get_rate() - Get the rate value for the clock
+ * @clk_id Clock ID
+ * @rate: Buffer to store clock rate value
+ *
+ * @return Returns status, either success or error+reason
+ */
+enum pm_ret_status pm_clock_get_rate(uint32_t clk_id, uint32_t *clk_rate)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMC */
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_GETRATE, clk_id);
+
+ return pm_ipi_send_sync(primary_proc, payload, clk_rate, 2);
+}
/**
* pm_pll_set_param() - Set PLL parameter
@@ -689,12 +722,31 @@
enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2,
uint32_t arg3, uint32_t *data)
{
+ uint32_t ret;
+ uint32_t version;
uint32_t payload[PAYLOAD_ARG_CNT];
+ uint32_t fw_api_version;
/* Send request to the PMC */
PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_QUERY_DATA, qid, arg1,
arg2, arg3);
- return pm_ipi_send_sync(primary_proc, payload, data, 4);
+
+ ret = pm_feature_check(PM_QUERY_DATA, &version);
+ if (PM_RET_SUCCESS == ret) {
+ fw_api_version = version & 0xFFFF ;
+ if ((2U == fw_api_version) &&
+ ((XPM_QID_CLOCK_GET_NAME == qid) ||
+ (XPM_QID_PINCTRL_GET_FUNCTION_NAME == qid))) {
+ ret = pm_ipi_send_sync(primary_proc, payload, data, 8);
+ ret = data[0];
+ data[0] = data[1];
+ data[1] = data[2];
+ data[2] = data[3];
+ } else {
+ ret = pm_ipi_send_sync(primary_proc, payload, data, 4);
+ }
+ }
+ return ret;
}
/**
* pm_api_ioctl() - PM IOCTL API for device control and configs
@@ -780,7 +832,6 @@
switch (api_id) {
case PM_GET_CALLBACK_DATA:
case PM_GET_TRUSTZONE_VERSION:
- case PM_INIT_FINALIZE:
*version = (PM_API_BASE_VERSION << 16);
return PM_RET_SUCCESS;
case PM_GET_API_VERSION:
@@ -798,6 +849,7 @@
case PM_SET_REQUIREMENT:
case PM_RESET_ASSERT:
case PM_RESET_GET_STATUS:
+ case PM_GET_CHIPID:
case PM_PINCTRL_REQUEST:
case PM_PINCTRL_RELEASE:
case PM_PINCTRL_GET_FUNCTION:
@@ -805,7 +857,11 @@
case PM_PINCTRL_CONFIG_PARAM_GET:
case PM_PINCTRL_CONFIG_PARAM_SET:
case PM_IOCTL:
+ *version = (PM_API_BASE_VERSION << 16);
+ break;
case PM_QUERY_DATA:
+ *version = (PM_API_QUERY_DATA_VERSION << 16);
+ break;
case PM_CLOCK_ENABLE:
case PM_CLOCK_DISABLE:
case PM_CLOCK_GETSTATE:
@@ -813,11 +869,15 @@
case PM_CLOCK_GETDIVIDER:
case PM_CLOCK_SETPARENT:
case PM_CLOCK_GETPARENT:
+ case PM_CLOCK_GETRATE:
case PM_PLL_SET_PARAMETER:
case PM_PLL_GET_PARAMETER:
case PM_PLL_SET_MODE:
case PM_PLL_GET_MODE:
case PM_FEATURE_CHECK:
+ case PM_INIT_FINALIZE:
+ case PM_SET_MAX_LATENCY:
+ case PM_REGISTER_NOTIFIER:
*version = (PM_API_BASE_VERSION << 16);
break;
case PM_LOAD_PDI:
@@ -883,3 +943,45 @@
device_id, type);
return pm_ipi_send_sync(primary_proc, payload, result, 1);
}
+
+/**
+ * pm_set_max_latency() - PM call to change in the maximum wake-up latency
+ * requirements for a specific device currently
+ * used by that CPU.
+ * @device_id Device ID
+ * @latency Latency value
+ *
+ * @return Returns status, either success or error+reason
+ */
+enum pm_ret_status pm_set_max_latency(uint32_t device_id, uint32_t latency)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMC */
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_SET_MAX_LATENCY,
+ device_id, latency);
+
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
+}
+
+/**
+ * pm_register_notifier() - PM call to register a subsystem to be notified
+ * about the device event
+ * @device_id Device ID for the Node to which the event is related
+ * @event Event in question
+ * @wake Wake subsystem upon capturing the event if value 1
+ * @enable Enable the registration for value 1, disable for value 0
+ *
+ * @return Returns status, either success or error+reason
+ */
+enum pm_ret_status pm_register_notifier(uint32_t device_id, uint32_t event,
+ uint32_t wake, uint32_t enable)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMC */
+ PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_REGISTER_NOTIFIER,
+ device_id, event, wake, enable);
+
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
+}
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h
index 4de592a..84867b6 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.h
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2020, Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,6 +15,7 @@
**********************************************************/
enum pm_ret_status pm_get_api_version(unsigned int *version);
+enum pm_ret_status pm_init_finalize(void);
enum pm_ret_status pm_self_suspend(uint32_t nid,
unsigned int latency,
unsigned int state,
@@ -52,6 +53,7 @@
enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider);
enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent);
enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent);
+enum pm_ret_status pm_clock_get_rate(uint32_t clk_id, uint32_t *clk_rate);
enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param,
uint32_t value);
enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param,
@@ -72,4 +74,7 @@
enum pm_ret_status pm_get_op_characteristic(uint32_t device_id,
enum pm_opchar_type type,
uint32_t *result);
+enum pm_ret_status pm_set_max_latency(uint32_t device_id, uint32_t latency);
+enum pm_ret_status pm_register_notifier(uint32_t device_id, uint32_t event,
+ uint32_t wake, uint32_t enable);
#endif /* PM_API_SYS_H */
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index 5b47838..9ab921e 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2020, Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -113,8 +113,9 @@
/**
* pm_client_set_wakeup_sources - Set all devices with enabled interrupts as
* wake sources in the LibPM.
+ * @node_id: Node id of processor
*/
-static void pm_client_set_wakeup_sources(void)
+static void pm_client_set_wakeup_sources(uint32_t node_id)
{
uint32_t reg_num;
uint32_t device_id;
@@ -147,7 +148,7 @@
(!pm_wakeup_nodes_set[node_idx])) {
/* Get device ID from node index */
device_id = PERIPH_DEVID(node_idx);
- ret = pm_set_wakeup_source(XPM_DEVID_ACPU_0,
+ ret = pm_set_wakeup_source(node_id,
device_id, 1);
pm_wakeup_nodes_set[node_idx] = !ret;
}
@@ -167,7 +168,7 @@
bakery_lock_get(&pm_client_secure_lock);
if (state == PM_STATE_SUSPEND_TO_RAM)
- pm_client_set_wakeup_sources();
+ pm_client_set_wakeup_sources(proc->node_id);
/* Set powerdown request */
mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) |
diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h
index 966b00b..793f750 100644
--- a/plat/xilinx/versal/pm_service/pm_defs.h
+++ b/plat/xilinx/versal/pm_service/pm_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2020, Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -39,10 +39,13 @@
/* PM API Versions */
#define PM_API_BASE_VERSION 1U
+#define PM_API_QUERY_DATA_VERSION 2U
+
/* PM API ids */
#define PM_GET_API_VERSION 1U
#define PM_GET_DEVICE_STATUS 3U
#define PM_GET_OP_CHARACTERISTIC 4U
+#define PM_REGISTER_NOTIFIER 5U
#define PM_REQ_SUSPEND 6U
#define PM_SELF_SUSPEND 7U
#define PM_FORCE_POWERDOWN 8U
@@ -53,6 +56,7 @@
#define PM_REQUEST_DEVICE 13U
#define PM_RELEASE_DEVICE 14U
#define PM_SET_REQUIREMENT 15U
+#define PM_SET_MAX_LATENCY 16U
#define PM_RESET_ASSERT 17U
#define PM_RESET_GET_STATUS 18U
#define PM_INIT_FINALIZE 21U
@@ -163,4 +167,25 @@
PM_RET_ERROR_TIMEOUT = 2006,
PM_RET_ERROR_NODE_USED = 2007
};
+
+/**
+ * Qids
+ */
+enum pm_query_id {
+ XPM_QID_INVALID,
+ XPM_QID_CLOCK_GET_NAME,
+ XPM_QID_CLOCK_GET_TOPOLOGY,
+ XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
+ XPM_QID_CLOCK_GET_MUXSOURCES,
+ XPM_QID_CLOCK_GET_ATTRIBUTES,
+ XPM_QID_PINCTRL_GET_NUM_PINS,
+ XPM_QID_PINCTRL_GET_NUM_FUNCTIONS,
+ XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
+ XPM_QID_PINCTRL_GET_FUNCTION_NAME,
+ XPM_QID_PINCTRL_GET_FUNCTION_GROUPS,
+ XPM_QID_PINCTRL_GET_PIN_GROUPS,
+ XPM_QID_CLOCK_GET_NUM_CLOCKS,
+ XPM_QID_CLOCK_GET_MAX_DIVISOR,
+ XPM_QID_PLD_GET_PARENT,
+};
#endif /* PM_DEFS_H */
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c
index 45b2803..2ed6d27 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.c
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.c
@@ -159,7 +159,8 @@
}
case PM_INIT_FINALIZE:
- SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS);
+ ret = pm_init_finalize();
+ SMC_RET1(handle, (uint64_t)ret);
case PM_GET_CALLBACK_DATA:
{
@@ -214,14 +215,15 @@
case PM_QUERY_DATA:
{
- uint32_t data[4] = { 0 };
+ uint32_t data[8] = { 0 };
ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
- pm_arg[3], data);
- SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32),
- (uint64_t)data[1] | ((uint64_t)data[2] << 32));
- }
+ pm_arg[3], data);
+ SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32),
+ (uint64_t)data[1] | ((uint64_t)data[2] << 32));
+
+ }
case PM_CLOCK_ENABLE:
ret = pm_clock_enable(pm_arg[0]);
SMC_RET1(handle, (uint64_t)ret);
@@ -262,6 +264,15 @@
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
+ case PM_CLOCK_GETRATE:
+ {
+ uint32_t rate[2] = { 0 };
+
+ ret = pm_clock_get_rate(pm_arg[0], rate);
+ SMC_RET2(handle, (uint64_t)ret | ((uint64_t)rate[0] << 32),
+ rate[1]);
+ }
+
case PM_PLL_SET_PARAMETER:
ret = pm_pll_set_param(pm_arg[0], pm_arg[1], pm_arg[2]);
SMC_RET1(handle, (uint64_t)ret);
@@ -321,6 +332,18 @@
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)result << 32));
}
+ case PM_SET_MAX_LATENCY:
+ {
+ ret = pm_set_max_latency(pm_arg[0], pm_arg[1]);
+ SMC_RET1(handle, (uint64_t)ret);
+ }
+
+ case PM_REGISTER_NOTIFIER:
+ {
+ ret = pm_register_notifier(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
+ SMC_RET1(handle, (uint64_t)ret);
+ }
+
default:
WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index b6d8770..d4cd7f6 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -32,8 +32,9 @@
{
assert(sec_state_is_valid(type));
- if (type == NON_SECURE)
+ if (type == NON_SECURE) {
return &bl33_image_ep_info;
+ }
return &bl32_image_ep_info;
}
@@ -99,14 +100,18 @@
enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
&bl33_image_ep_info,
atf_handoff_addr);
- if (ret == FSBL_HANDOFF_NO_STRUCT)
+ if (ret == FSBL_HANDOFF_NO_STRUCT) {
bl31_set_default_config();
- else if (ret != FSBL_HANDOFF_SUCCESS)
+ } else if (ret != FSBL_HANDOFF_SUCCESS) {
panic();
+ }
}
-
- NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
- NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
+ if (bl32_image_ep_info.pc) {
+ VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
+ }
+ if (bl33_image_ep_info.pc) {
+ VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
+ }
}
/* Enable the test setup */
@@ -134,12 +139,14 @@
int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
{
/* Validate 'handler' and 'id' parameters */
- if (!handler || id >= MAX_INTR_EL3)
+ if (!handler || id >= MAX_INTR_EL3) {
return -EINVAL;
+ }
/* Check if a handler has already been registered */
- if (type_el3_interrupt_table[id])
+ if (type_el3_interrupt_table[id]) {
return -EALREADY;
+ }
type_el3_interrupt_table[id] = handler;
@@ -154,8 +161,9 @@
intr_id = plat_ic_get_pending_interrupt_id();
handler = type_el3_interrupt_table[intr_id];
- if (handler != NULL)
+ if (handler != NULL) {
handler(intr_id, flags, handle, cookie);
+ }
return 0;
}
@@ -178,8 +186,9 @@
set_interrupt_rm_flag(flags, NON_SECURE);
rc = register_interrupt_type_handler(INTR_TYPE_EL3,
rdo_el3_interrupt_handler, flags);
- if (rc)
+ if (rc) {
panic();
+ }
#endif
}
diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index 5e7254e..f474630 100644
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -341,12 +341,22 @@
#define PGGS_BASEADDR (0xFFD80050U)
#define PGGS_NUM_REGS U(4)
-/* Warm restart boot health status register and mask */
-#define PM_BOOT_HEALTH_STATUS_REG (GGS_BASEADDR + U(0x10))
+/* PMU GGS4 register 4 is used for warm restart boot health status */
+#define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10)
+/* Warm restart boot health status mask */
#define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
+/* WDT restart scope shift and mask */
+#define RESTART_SCOPE_SHIFT (3)
+#define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT)
/*AFI registers */
#define AFIFM6_WRCTRL U(13)
#define FABRIC_WIDTH U(3)
+/* CSUDMA Module Base Address*/
+#define CSUDMA_BASE 0xFFC80000
+
+/* RSA-CORE Module Base Address*/
+#define RSA_CORE_BASE 0xFFCE0000
+
#endif /* ZYNQMP_DEF_H */
diff --git a/plat/xilinx/zynqmp/plat_zynqmp.c b/plat/xilinx/zynqmp/plat_zynqmp.c
index 906ce1b..58a52a3 100644
--- a/plat/xilinx/zynqmp/plat_zynqmp.c
+++ b/plat/xilinx/zynqmp/plat_zynqmp.c
@@ -9,11 +9,13 @@
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
- if (mpidr & MPIDR_CLUSTER_MASK)
+ if (mpidr & MPIDR_CLUSTER_MASK) {
return -1;
+ }
- if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT)
+ if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT) {
return -1;
+ }
return zynqmp_calc_core_pos(mpidr);
}
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 44f20f6..1cd168f 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -59,13 +59,14 @@
-Iplat/xilinx/zynqmp/include/ \
-Iplat/xilinx/zynqmp/pm_service/ \
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
+ ${GICV2_SOURCES} \
drivers/cadence/uart/aarch64/cdns_console.S \
plat/arm/common/arm_cci.c \
plat/arm/common/arm_common.c \
@@ -95,6 +96,8 @@
plat/xilinx/zynqmp/pm_service/pm_api_clock.c \
plat/xilinx/zynqmp/pm_service/pm_client.c
+BL31_CPPFLAGS += -fno-jump-tables
+
ifneq (${RESET_TO_BL31},1)
$(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.")
endif
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index 852f927..0cc517e 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -129,11 +129,11 @@
.div = NA_DIV, \
}
-#define GENERIC_DIV(id) \
+#define GENERIC_DIV1 \
{ \
- .type = TYPE_DIV##id, \
- .offset = PERIPH_DIV##id##_SHIFT, \
- .width = PERIPH_DIV##id##_WIDTH, \
+ .type = TYPE_DIV1, \
+ .offset = PERIPH_DIV1_SHIFT, \
+ .width = PERIPH_DIV1_WIDTH, \
.clkflags = CLK_SET_RATE_NO_REPARENT | \
CLK_IS_BASIC, \
.typeflags = CLK_DIVIDER_ONE_BASED | \
@@ -142,6 +142,20 @@
.div = NA_DIV, \
}
+#define GENERIC_DIV2 \
+ { \
+ .type = TYPE_DIV2, \
+ .offset = PERIPH_DIV2_SHIFT, \
+ .width = PERIPH_DIV2_WIDTH, \
+ .clkflags = CLK_SET_RATE_NO_REPARENT | \
+ CLK_SET_RATE_PARENT | \
+ CLK_IS_BASIC, \
+ .typeflags = CLK_DIVIDER_ONE_BASED | \
+ CLK_DIVIDER_ALLOW_ZERO, \
+ .mult = NA_MULT, \
+ .div = NA_DIV, \
+ }
+
#define IGNORE_UNUSED_DIV(id) \
{ \
.type = TYPE_DIV##id, \
@@ -340,25 +354,25 @@
static struct pm_clock_node generic_mux_div_nodes[] = {
GENERIC_MUX,
- GENERIC_DIV(1),
+ GENERIC_DIV1,
};
static struct pm_clock_node generic_mux_div_gate_nodes[] = {
GENERIC_MUX,
- GENERIC_DIV(1),
+ GENERIC_DIV1,
GENERIC_GATE,
};
static struct pm_clock_node generic_mux_div_unused_gate_nodes[] = {
GENERIC_MUX,
- GENERIC_DIV(1),
+ GENERIC_DIV1,
IGNORE_UNUSED_GATE,
};
static struct pm_clock_node generic_mux_div_div_gate_nodes[] = {
GENERIC_MUX,
- GENERIC_DIV(1),
- GENERIC_DIV(2),
+ GENERIC_DIV1,
+ GENERIC_DIV2,
GENERIC_GATE,
};
@@ -410,8 +424,8 @@
static struct pm_clock_node usb_nodes[] = {
GENERIC_MUX,
- GENERIC_DIV(1),
- GENERIC_DIV(2),
+ GENERIC_DIV1,
+ GENERIC_DIV2,
{
.type = TYPE_GATE,
.offset = USB_GATE_SHIFT,
@@ -2432,10 +2446,11 @@
*
* @return Returns success. In case of error, name data is 0.
*/
-enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name)
+void pm_api_clock_get_name(unsigned int clock_id, char *name)
{
if (clock_id == CLK_MAX)
- memcpy(name, END_OF_CLK, CLK_NAME_LEN);
+ memcpy(name, END_OF_CLK, sizeof(END_OF_CLK) > CLK_NAME_LEN ?
+ CLK_NAME_LEN : sizeof(END_OF_CLK));
else if (!pm_clock_valid(clock_id))
memset(name, 0, CLK_NAME_LEN);
else if (clock_id < CLK_MAX_OUTPUT_CLK)
@@ -2443,8 +2458,6 @@
else
memcpy(name, ext_clocks[clock_id - CLK_MAX_OUTPUT_CLK].name,
CLK_NAME_LEN);
-
- return PM_RET_SUCCESS;
}
/**
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
index 301ed24..5efd63f 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -294,7 +294,7 @@
struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id);
uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id);
-enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
+void pm_api_clock_get_name(unsigned int clock_id, char *name);
enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks);
enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
unsigned int index,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index 60e80d9..f165fb0 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -282,17 +282,29 @@
{
unsigned int shift;
enum pm_ret_status ret;
+ unsigned int val, mask;
- if (nid == NODE_SD_0)
+ if (nid == NODE_SD_0) {
shift = 0;
- else if (nid == NODE_SD_1)
+ mask = ZYNQMP_SD0_DLL_RST_MASK;
+ } else if (nid == NODE_SD_1) {
shift = ZYNQMP_SD_TAP_OFFSET;
- else
+ mask = ZYNQMP_SD1_DLL_RST_MASK;
+ } else {
return PM_RET_ERROR_ARGS;
+ }
- ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
- if (ret != PM_RET_SUCCESS)
+ ret = pm_mmio_read(ZYNQMP_SD_DLL_CTRL, &val);
+ if (ret != PM_RET_SUCCESS) {
return ret;
+ }
+
+ if ((val & mask) == 0) {
+ ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
+ if (ret != PM_RET_SUCCESS) {
+ return ret;
+ }
+ }
if (type == PM_TAPDELAY_INPUT) {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
@@ -300,9 +312,15 @@
(ZYNQMP_SD_ITAPCHGWIN << shift));
if (ret != PM_RET_SUCCESS)
goto reset_release;
- ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
- (ZYNQMP_SD_ITAPDLYENA_MASK << shift),
- (ZYNQMP_SD_ITAPDLYENA << shift));
+ if (value == 0)
+ ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
+ (ZYNQMP_SD_ITAPDLYENA_MASK <<
+ shift), 0);
+ else
+ ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
+ (ZYNQMP_SD_ITAPDLYENA_MASK <<
+ shift), (ZYNQMP_SD_ITAPDLYENA <<
+ shift));
if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
@@ -314,8 +332,7 @@
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
} else if (type == PM_TAPDELAY_OUTPUT) {
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
- (ZYNQMP_SD_OTAPDLYENA_MASK << shift),
- (ZYNQMP_SD_OTAPDLYENA << shift));
+ (ZYNQMP_SD_OTAPDLYENA_MASK << shift), 0);
if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
@@ -326,7 +343,10 @@
}
reset_release:
- pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
+ if ((val & mask) == 0) {
+ (void)pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
+ }
+
return ret;
}
@@ -575,7 +595,7 @@
*/
static enum pm_ret_status pm_ioctl_set_boot_health_status(unsigned int value)
{
- return pm_mmio_write(PM_BOOT_HEALTH_STATUS_REG,
+ return pm_mmio_write(PMU_GLOBAL_GEN_STORAGE4,
PM_BOOT_HEALTH_STATUS_MASK, value);
}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index 4b8dfb6..9a6b497 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -19,39 +19,6 @@
#include "pm_common.h"
#include "pm_ipi.h"
-#define PINCTRL_FUNCTION_MASK U(0xFE)
-#define PINCTRL_VOLTAGE_STATUS_MASK U(0x01)
-#define NFUNCS_PER_PIN U(13)
-#define PINCTRL_NUM_MIOS U(78)
-#define MAX_PIN_PER_REG U(26)
-#define PINCTRL_BANK_ADDR_STEP U(28)
-
-#define PINCTRL_DRVSTRN0_REG_OFFSET U(0)
-#define PINCTRL_DRVSTRN1_REG_OFFSET U(4)
-#define PINCTRL_SCHCMOS_REG_OFFSET U(8)
-#define PINCTRL_PULLCTRL_REG_OFFSET U(12)
-#define PINCTRL_PULLSTAT_REG_OFFSET U(16)
-#define PINCTRL_SLEWCTRL_REG_OFFSET U(20)
-#define PINCTRL_VOLTAGE_STAT_REG_OFFSET U(24)
-
-#define IOU_SLCR_BANK1_CTRL5 U(0XFF180164)
-
-#define PINCTRL_CFG_ADDR_OFFSET(addr, reg, miopin) \
- ((addr) + 4 * PINCTRL_NUM_MIOS + PINCTRL_BANK_ADDR_STEP * \
- ((miopin) / MAX_PIN_PER_REG) + (reg))
-
-#define PINCTRL_PIN_OFFSET(_miopin) \
- ((_miopin) - (MAX_PIN_PER_REG * ((_miopin) / MAX_PIN_PER_REG)))
-
-#define PINCTRL_REGVAL_TO_PIN_CONFIG(_pin, _val) \
- (((_val) >> PINCTRL_PIN_OFFSET(_pin)) & 0x1)
-
-static uint8_t pm_pinctrl_mux[NFUNCS_PER_PIN] = {
- 0x02, 0x04, 0x08, 0x10, 0x18,
- 0x00, 0x20, 0x40, 0x60, 0x80,
- 0xA0, 0xC0, 0xE0
-};
-
struct pinctrl_function {
char name[FUNCTION_NAME_LEN];
uint16_t (*groups)[];
@@ -2604,18 +2571,13 @@
*
* This function is used by master to get name of function specified
* by given function ID.
- *
- * @return Returns success. In case of error, name data is 0.
*/
-enum pm_ret_status pm_api_pinctrl_get_function_name(unsigned int fid,
- char *name)
+void pm_api_pinctrl_get_function_name(unsigned int fid, char *name)
{
if (fid >= MAX_FUNCTION)
memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN);
else
memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN);
-
- return PM_RET_SUCCESS;
}
/**
@@ -2713,330 +2675,3 @@
return PM_RET_SUCCESS;
}
-
-/**
- * pm_api_pinctrl_get_function() - Read function id set for the given pin
- * @pin Pin number
- * @nid Node ID of function currently set for given pin
- *
- * This function provides the function currently set for the given pin.
- *
- * @return Returns status, either success or error+reason
- */
-enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
- unsigned int *id)
-{
- unsigned int i = 0, j = 0;
- enum pm_ret_status ret = PM_RET_SUCCESS;
- unsigned int ctrlreg, val, gid;
- uint16_t *grps;
-
- ctrlreg = IOU_SLCR_BASEADDR + 4U * pin;
- ret = pm_mmio_read(ctrlreg, &val);
- if (ret != PM_RET_SUCCESS)
- return ret;
-
- val &= PINCTRL_FUNCTION_MASK;
-
- for (i = 0; i < NFUNCS_PER_PIN; i++)
- if (val == pm_pinctrl_mux[i])
- break;
-
- if (i == NFUNCS_PER_PIN)
- return PM_RET_ERROR_NOTSUPPORTED;
-
- gid = *(*zynqmp_pin_groups[pin].groups + i);
-
- for (i = 0; i < MAX_FUNCTION; i++) {
- grps = *pinctrl_functions[i].groups;
- if (grps == NULL)
- continue;
- if (val != pinctrl_functions[i].regval)
- continue;
-
- for (j = 0; grps[j] != (uint16_t)END_OF_GROUPS; j++) {
- if (gid == grps[j]) {
- *id = i;
- goto done;
- }
- }
- }
- if (i == MAX_FUNCTION)
- ret = PM_RET_ERROR_ARGS;
-done:
- return ret;
-}
-
-/**
- * pm_api_pinctrl_set_function() - Set function id set for the given pin
- * @pin Pin number
- * @nid Node ID of function to set for given pin
- *
- * This function provides the function currently set for the given pin.
- *
- * @return Returns status, either success or error+reason
- */
-enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin,
- unsigned int fid)
-{
- int i, j;
- unsigned int ctrlreg, val;
- uint16_t *pgrps, *fgrps;
-
- ctrlreg = IOU_SLCR_BASEADDR + 4U * pin;
- val = pinctrl_functions[fid].regval;
-
- for (i = 0; i < NFUNCS_PER_PIN; i++)
- if (val == pm_pinctrl_mux[i])
- break;
-
- if (i == NFUNCS_PER_PIN)
- return PM_RET_ERROR_NOTSUPPORTED;
-
- pgrps = *zynqmp_pin_groups[pin].groups;
- if (!pgrps)
- return PM_RET_ERROR_NOTSUPPORTED;
-
- fgrps = *pinctrl_functions[fid].groups;
- if (!fgrps)
- return PM_RET_ERROR_NOTSUPPORTED;
-
- for (i = 0; fgrps[i] != (uint16_t)END_OF_GROUPS; i++)
- for (j = 0; pgrps[j] != (uint16_t)END_OF_GROUPS; j++)
- if (fgrps[i] == pgrps[j])
- goto match;
-
- return PM_RET_ERROR_NOTSUPPORTED;
-
-match:
- return pm_mmio_write(ctrlreg, PINCTRL_FUNCTION_MASK, val);
-}
-
-/**
- * pm_api_pinctrl_set_config() - Set configuration parameter for given pin
- * @pin: Pin for which configuration is to be set
- * @param: Configuration parameter to be set
- * @value: Value to be set for configuration parameter
- *
- * This function sets value of requested configuration parameter for given pin.
- *
- * @return Returns status, either success or error+reason
- */
-enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin,
- unsigned int param,
- unsigned int value)
-{
- enum pm_ret_status ret;
- unsigned int ctrlreg, mask, val, offset;
-
- if (param >= PINCTRL_CONFIG_MAX)
- return PM_RET_ERROR_NOTSUPPORTED;
-
- if (pin >= PINCTRL_NUM_MIOS)
- return PM_RET_ERROR_ARGS;
-
- mask = 1 << PINCTRL_PIN_OFFSET(pin);
-
- switch (param) {
- case PINCTRL_CONFIG_SLEW_RATE:
- if (value != PINCTRL_SLEW_RATE_FAST &&
- value != PINCTRL_SLEW_RATE_SLOW)
- return PM_RET_ERROR_ARGS;
-
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_SLEWCTRL_REG_OFFSET,
- pin);
- val = value << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(ctrlreg, mask, val);
- break;
- case PINCTRL_CONFIG_BIAS_STATUS:
- if (value != PINCTRL_BIAS_ENABLE &&
- value != PINCTRL_BIAS_DISABLE)
- return PM_RET_ERROR_ARGS;
-
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_PULLSTAT_REG_OFFSET,
- pin);
-
- offset = PINCTRL_PIN_OFFSET(pin);
- if (ctrlreg == IOU_SLCR_BANK1_CTRL5)
- offset = (offset < 12U) ?
- (offset + 14U) : (offset - 12U);
-
- val = value << offset;
- mask = 1 << offset;
- ret = pm_mmio_write(ctrlreg, mask, val);
- break;
- case PINCTRL_CONFIG_PULL_CTRL:
-
- if (value != PINCTRL_BIAS_PULL_DOWN &&
- value != PINCTRL_BIAS_PULL_UP)
- return PM_RET_ERROR_ARGS;
-
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_PULLSTAT_REG_OFFSET,
- pin);
-
- offset = PINCTRL_PIN_OFFSET(pin);
- if (ctrlreg == IOU_SLCR_BANK1_CTRL5)
- offset = (offset < 12U) ?
- (offset + 14U) : (offset - 12U);
-
- val = PINCTRL_BIAS_ENABLE << offset;
- ret = pm_mmio_write(ctrlreg, 1 << offset, val);
- if (ret != PM_RET_SUCCESS)
- return ret;
-
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_PULLCTRL_REG_OFFSET,
- pin);
- val = value << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(ctrlreg, mask, val);
- break;
- case PINCTRL_CONFIG_SCHMITT_CMOS:
- if (value != PINCTRL_INPUT_TYPE_CMOS &&
- value != PINCTRL_INPUT_TYPE_SCHMITT)
- return PM_RET_ERROR_ARGS;
-
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_SCHCMOS_REG_OFFSET,
- pin);
-
- val = value << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(ctrlreg, mask, val);
- break;
- case PINCTRL_CONFIG_DRIVE_STRENGTH:
- if (value > PINCTRL_DRIVE_STRENGTH_12MA)
- return PM_RET_ERROR_ARGS;
-
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_DRVSTRN0_REG_OFFSET,
- pin);
- val = (value >> 1) << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(ctrlreg, mask, val);
- if (ret)
- return ret;
-
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_DRVSTRN1_REG_OFFSET,
- pin);
- val = (value & 0x01U) << PINCTRL_PIN_OFFSET(pin);
- ret = pm_mmio_write(ctrlreg, mask, val);
- break;
- default:
- ERROR("Invalid parameter %u\n", param);
- ret = PM_RET_ERROR_NOTSUPPORTED;
- break;
- }
-
- return ret;
-}
-
-/**
- * pm_api_pinctrl_get_config() - Get configuration parameter value for given pin
- * @pin: Pin for which configuration is to be read
- * @param: Configuration parameter to be read
- * @value: buffer to store value of configuration parameter
- *
- * This function reads value of requested configuration parameter for given pin.
- *
- * @return Returns status, either success or error+reason
- */
-enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin,
- unsigned int param,
- unsigned int *value)
-{
- enum pm_ret_status ret;
- unsigned int ctrlreg, val;
-
- if (param >= PINCTRL_CONFIG_MAX)
- return PM_RET_ERROR_NOTSUPPORTED;
-
- if (pin >= PINCTRL_NUM_MIOS)
- return PM_RET_ERROR_ARGS;
-
- switch (param) {
- case PINCTRL_CONFIG_SLEW_RATE:
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_SLEWCTRL_REG_OFFSET,
- pin);
-
- ret = pm_mmio_read(ctrlreg, &val);
- if (ret != PM_RET_SUCCESS)
- return ret;
-
- *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
- break;
- case PINCTRL_CONFIG_BIAS_STATUS:
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_PULLSTAT_REG_OFFSET,
- pin);
-
- ret = pm_mmio_read(ctrlreg, &val);
- if (ret)
- return ret;
-
- if (ctrlreg == IOU_SLCR_BANK1_CTRL5)
- val = ((val & 0x3FFF) << 12) | ((val >> 14) & 0xFFF);
-
- *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
- break;
- case PINCTRL_CONFIG_PULL_CTRL:
-
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_PULLCTRL_REG_OFFSET,
- pin);
-
- ret = pm_mmio_read(ctrlreg, &val);
- if (ret)
- return ret;
-
- *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
- break;
- case PINCTRL_CONFIG_SCHMITT_CMOS:
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_SCHCMOS_REG_OFFSET,
- pin);
-
- ret = pm_mmio_read(ctrlreg, &val);
- if (ret)
- return ret;
-
- *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
- break;
- case PINCTRL_CONFIG_DRIVE_STRENGTH:
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_DRVSTRN0_REG_OFFSET,
- pin);
- ret = pm_mmio_read(ctrlreg, &val);
- if (ret)
- return ret;
-
- *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val) << 1;
-
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_DRVSTRN1_REG_OFFSET,
- pin);
- ret = pm_mmio_read(ctrlreg, &val);
- if (ret)
- return ret;
-
- *value |= PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val);
- break;
- case PINCTRL_CONFIG_VOLTAGE_STATUS:
- ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR,
- PINCTRL_VOLTAGE_STAT_REG_OFFSET,
- pin);
-
- ret = pm_mmio_read(ctrlreg, &val);
- if (ret)
- return ret;
-
- *value = val & PINCTRL_VOLTAGE_STATUS_MASK;
- break;
- default:
- return PM_RET_ERROR_NOTSUPPORTED;
- }
-
- return PM_RET_SUCCESS;
-}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
index 9923c00..2b8fca3 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -709,18 +709,7 @@
#define PINCTRL_DRIVE_STRENGTH_8MA 2U
#define PINCTRL_DRIVE_STRENGTH_12MA 3U
-enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin,
- unsigned int fid);
-enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin,
- unsigned int *id);
-enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin,
- unsigned int param,
- unsigned int value);
-enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin,
- unsigned int param,
- unsigned int *value);
-enum pm_ret_status pm_api_pinctrl_get_function_name(unsigned int fid,
- char *name);
+void pm_api_pinctrl_get_function_name(unsigned int fid, char *name);
enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid,
unsigned int index,
uint16_t *groups);
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
index b1720d9..9a53408 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
@@ -65,6 +65,10 @@
PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4); \
}
+#define EM_PACK_PAYLOAD1(pl, arg0) { \
+ pl[0] = (uint16_t)(0xE) << 16 | (uint16_t)arg0; \
+}
+
/**
* pm_self_suspend() - PM call for processor to suspend itself
* @nid Node id of the processor or subsystem
@@ -655,7 +659,11 @@
*/
enum pm_ret_status pm_pinctrl_request(unsigned int pin)
{
- return PM_RET_SUCCESS;
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ PM_PACK_PAYLOAD2(payload, PM_PINCTRL_REQUEST, pin);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
@@ -668,37 +676,44 @@
*/
enum pm_ret_status pm_pinctrl_release(unsigned int pin)
{
- return PM_RET_SUCCESS;
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ PM_PACK_PAYLOAD2(payload, PM_PINCTRL_RELEASE, pin);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
* pm_pinctrl_get_function() - Read function id set for the given pin
* @pin Pin number
- * @nid Node ID of function currently set for given pin
+ * @fid ID of function currently set for given pin
*
* This function provides the function currently set for the given pin.
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_pinctrl_get_function(unsigned int pin,
- enum pm_node_id *nid)
+enum pm_ret_status pm_pinctrl_get_function(unsigned int pin, unsigned int *fid)
{
- return pm_api_pinctrl_get_function(pin, nid);
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ PM_PACK_PAYLOAD2(payload, PM_PINCTRL_GET_FUNCTION, pin);
+ return pm_ipi_send_sync(primary_proc, payload, fid, 1);
}
/**
* pm_pinctrl_set_function() - Set function id set for the given pin
* @pin Pin number
- * @nid Node ID of function to set for given pin
- *
- * This function provides the function currently set for the given pin.
+ * @fid ID of function to set for given pin
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_pinctrl_set_function(unsigned int pin,
- enum pm_node_id nid)
+enum pm_ret_status pm_pinctrl_set_function(unsigned int pin, unsigned int fid)
{
- return pm_api_pinctrl_set_function(pin, (unsigned int)nid);
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ PM_PACK_PAYLOAD3(payload, PM_PINCTRL_SET_FUNCTION, pin, fid);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
@@ -715,24 +730,30 @@
unsigned int param,
unsigned int *value)
{
- return pm_api_pinctrl_get_config(pin, param, value);
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ PM_PACK_PAYLOAD3(payload, PM_PINCTRL_CONFIG_PARAM_GET, pin, param);
+ return pm_ipi_send_sync(primary_proc, payload, value, 1);
}
/**
- * pm_pinctrl_set_config() - Read value of requested config param for given pin
+ * pm_pinctrl_set_config() - Set value of requested config param for given pin
* @pin Pin number
* @param Parameter to set
* @value Parameter value to set
*
- * This function provides the configuration parameter value for the given pin.
- *
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_pinctrl_set_config(unsigned int pin,
unsigned int param,
unsigned int value)
{
- return pm_api_pinctrl_set_config(pin, param, value);
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ PM_PACK_PAYLOAD4(payload, PM_PINCTRL_CONFIG_PARAM_SET, pin, param,
+ value);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
@@ -793,12 +814,10 @@
*
* This function is used by master to get nmae of clock specified
* by given clock ID.
- *
- * @return Returns status, either success or error+reason
*/
-static enum pm_ret_status pm_clock_get_name(unsigned int clock_id, char *name)
+static void pm_clock_get_name(unsigned int clock_id, char *name)
{
- return pm_api_clock_get_name(clock_id, name);
+ pm_api_clock_get_name(clock_id, name);
}
/**
@@ -907,7 +926,13 @@
/* Send request to the PMU */
PM_PACK_PAYLOAD2(payload, api_id, clock_id);
- return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
+ status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
+
+ /* If action fails due to the lack of permissions filter the error */
+ if (status == PM_RET_ERROR_ACCESS)
+ status = PM_RET_SUCCESS;
+
+ return status;
}
/**
@@ -1229,13 +1254,10 @@
*
* This function is used by master to get name of function specified
* by given function Id
- *
- * Return: Returns status, either success or error+reason.
*/
-static enum pm_ret_status pm_pinctrl_get_function_name(unsigned int fid,
- char *name)
+static void pm_pinctrl_get_function_name(unsigned int fid, char *name)
{
- return pm_api_pinctrl_get_function_name(fid, name);
+ pm_api_pinctrl_get_function_name(fid, name);
}
/**
@@ -1295,78 +1317,58 @@
* @data Returned output data
*
* This function returns requested data.
- *
- * @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_query_data(enum pm_query_id qid,
- unsigned int arg1,
- unsigned int arg2,
- unsigned int arg3,
- unsigned int *data)
+void pm_query_data(enum pm_query_id qid, unsigned int arg1, unsigned int arg2,
+ unsigned int arg3, unsigned int *data)
{
- enum pm_ret_status ret;
-
switch (qid) {
case PM_QID_CLOCK_GET_NAME:
- ret = pm_clock_get_name(arg1, (char *)data);
+ pm_clock_get_name(arg1, (char *)data);
break;
case PM_QID_CLOCK_GET_TOPOLOGY:
- ret = pm_clock_get_topology(arg1, arg2, &data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_clock_get_topology(arg1, arg2, &data[1]);
break;
case PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS:
- ret = pm_clock_get_fixedfactor_params(arg1, &data[1], &data[2]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_clock_get_fixedfactor_params(arg1, &data[1],
+ &data[2]);
break;
case PM_QID_CLOCK_GET_PARENTS:
- ret = pm_clock_get_parents(arg1, arg2, &data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_clock_get_parents(arg1, arg2, &data[1]);
break;
case PM_QID_CLOCK_GET_ATTRIBUTES:
- ret = pm_clock_get_attributes(arg1, &data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_clock_get_attributes(arg1, &data[1]);
break;
case PM_QID_PINCTRL_GET_NUM_PINS:
- ret = pm_pinctrl_get_num_pins(&data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_pinctrl_get_num_pins(&data[1]);
break;
case PM_QID_PINCTRL_GET_NUM_FUNCTIONS:
- ret = pm_pinctrl_get_num_functions(&data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_pinctrl_get_num_functions(&data[1]);
break;
case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS:
- ret = pm_pinctrl_get_num_function_groups(arg1, &data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_pinctrl_get_num_function_groups(arg1, &data[1]);
break;
case PM_QID_PINCTRL_GET_FUNCTION_NAME:
- ret = pm_pinctrl_get_function_name(arg1, (char *)data);
+ pm_pinctrl_get_function_name(arg1, (char *)data);
break;
case PM_QID_PINCTRL_GET_FUNCTION_GROUPS:
- ret = pm_pinctrl_get_function_groups(arg1, arg2,
- (uint16_t *)&data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_pinctrl_get_function_groups(arg1, arg2,
+ (uint16_t *)&data[1]);
break;
case PM_QID_PINCTRL_GET_PIN_GROUPS:
- ret = pm_pinctrl_get_pin_groups(arg1, arg2,
- (uint16_t *)&data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_pinctrl_get_pin_groups(arg1, arg2,
+ (uint16_t *)&data[1]);
break;
case PM_QID_CLOCK_GET_NUM_CLOCKS:
- ret = pm_clock_get_num_clocks(&data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_clock_get_num_clocks(&data[1]);
break;
case PM_QID_CLOCK_GET_MAX_DIVISOR:
- ret = pm_clock_get_max_divisor(arg1, arg2, &data[1]);
- data[0] = (unsigned int)ret;
+ data[0] = pm_clock_get_max_divisor(arg1, arg2, &data[1]);
break;
default:
- ret = PM_RET_ERROR_ARGS;
+ data[0] = PM_RET_ERROR_ARGS;
WARN("Unimplemented query service call: 0x%x\n", qid);
- break;
}
-
- return ret;
}
enum pm_ret_status pm_sha_hash(uint32_t address_high,
@@ -1548,3 +1550,101 @@
PM_PACK_PAYLOAD2(payload, PM_PLL_GET_MODE, nid);
return pm_ipi_send_sync(primary_proc, payload, mode, 1);
}
+
+/**
+ * pm_register_access() - PM API for register read/write access data
+ *
+ * @register_access_id Register_access_id which says register read/write
+ *
+ * @address Address of the register to be accessed
+ *
+ * @mask Mask value to be used while writing value
+ *
+ * @value Value to be written to register
+ *
+ * @out Returned output data
+ *
+ * This function returns requested data.
+ *
+ * @return Returns status, either success or error+reason
+ */
+enum pm_ret_status pm_register_access(unsigned int register_access_id,
+ unsigned int address,
+ unsigned int mask,
+ unsigned int value,
+ unsigned int *out)
+{
+ enum pm_ret_status ret;
+
+ if (((ZYNQMP_CSU_BASEADDR & address) != ZYNQMP_CSU_BASEADDR) &&
+ ((CSUDMA_BASE & address) != CSUDMA_BASE) &&
+ ((RSA_CORE_BASE & address) != RSA_CORE_BASE) &&
+ ((PMU_GLOBAL_BASE & address) != PMU_GLOBAL_BASE))
+ return PM_RET_ERROR_ACCESS;
+
+ switch (register_access_id) {
+ case CONFIG_REG_WRITE:
+ ret = pm_mmio_write(address, mask, value);
+ break;
+ case CONFIG_REG_READ:
+ ret = pm_mmio_read(address, out);
+ break;
+ default:
+ ret = PM_RET_ERROR_ARGS;
+ WARN("Unimplemented register_access call\n\r");
+ }
+ return ret;
+}
+
+/**
+ * pm_efuse_access() - To program or read efuse bits.
+ *
+ * This function provides access to the xilskey library to program/read
+ * efuse bits.
+ *
+ * address_low: lower 32-bit Linear memory space address
+ * address_high: higher 32-bit Linear memory space address
+ *
+ * value: Returned output value
+ *
+ * @return Returns status, either success or error+reason
+ *
+ */
+enum pm_ret_status pm_efuse_access(uint32_t address_high,
+ uint32_t address_low,
+ uint32_t *value)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ PM_PACK_PAYLOAD3(payload, PM_EFUSE_ACCESS, address_high, address_low);
+
+ return pm_ipi_send_sync(primary_proc, payload, value, 1);
+}
+
+enum pm_ret_status em_set_action(unsigned int *value)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ EM_PACK_PAYLOAD1(payload, EM_SET_ACTION);
+ return pm_ipi_send_sync(primary_proc, payload, value, 1);
+}
+
+enum pm_ret_status em_remove_action(unsigned int *value)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ EM_PACK_PAYLOAD1(payload, EM_REMOVE_ACTION);
+ return pm_ipi_send_sync(primary_proc, payload, value, 1);
+}
+
+enum pm_ret_status em_send_errors(unsigned int *value)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ EM_PACK_PAYLOAD1(payload, EM_SEND_ERRORS);
+ return pm_ipi_send_sync(primary_proc, payload, value, 1);
+}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
index ff66d3f..b0c2652 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
@@ -28,6 +28,11 @@
PM_QID_CLOCK_GET_MAX_DIVISOR,
};
+enum pm_register_access_id {
+ CONFIG_REG_WRITE,
+ CONFIG_REG_READ,
+};
+
/**********************************************************
* System-level API function declarations
**********************************************************/
@@ -151,11 +156,8 @@
unsigned int parent_id);
enum pm_ret_status pm_clock_getparent(unsigned int clock_id,
unsigned int *parent_id);
-enum pm_ret_status pm_query_data(enum pm_query_id qid,
- unsigned int arg1,
- unsigned int arg2,
- unsigned int arg3,
- unsigned int *data);
+void pm_query_data(enum pm_query_id qid, unsigned int arg1, unsigned int arg2,
+ unsigned int arg3, unsigned int *data);
enum pm_ret_status pm_sha_hash(uint32_t address_high,
uint32_t address_low,
uint32_t size,
@@ -178,6 +180,11 @@
enum pm_ret_status pm_aes_engine(uint32_t address_high,
uint32_t address_low,
uint32_t *value);
+enum pm_ret_status pm_register_access(unsigned int register_access_id,
+ unsigned int address,
+ unsigned int mask,
+ unsigned int value,
+ unsigned int *out);
enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid,
enum pm_pll_param param_id,
@@ -189,5 +196,10 @@
enum pm_ret_status pm_pll_set_mode(enum pm_node_id nid, enum pm_pll_mode mode);
enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode);
+enum pm_ret_status pm_efuse_access(uint32_t address_high,
+ uint32_t address_low, uint32_t *value);
+enum pm_ret_status em_set_action(unsigned int *value);
+enum pm_ret_status em_remove_action(unsigned int *value);
+enum pm_ret_status em_send_errors(unsigned int *value);
#endif /* PM_API_SYS_H */
diff --git a/plat/xilinx/zynqmp/pm_service/pm_defs.h b/plat/xilinx/zynqmp/pm_service/pm_defs.h
index cae36c9..3324431 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,7 +18,7 @@
* (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
*/
#define PM_VERSION_MAJOR 1
-#define PM_VERSION_MINOR 0
+#define PM_VERSION_MINOR 1
#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
@@ -33,6 +33,7 @@
#define PM_STATE_CPU_IDLE 0x0U
#define PM_STATE_SUSPEND_TO_RAM 0xFU
+#define EM_FUNID_NUM_MASK 0xF0000U
/*********************************************************************
* Enum definitions
********************************************************************/
@@ -97,6 +98,9 @@
PM_PLL_GET_PARAMETER,
PM_PLL_SET_MODE,
PM_PLL_GET_MODE,
+ /* PM Register Access API */
+ PM_REGISTER_ACCESS,
+ PM_EFUSE_ACCESS,
PM_API_MAX
};
@@ -215,26 +219,29 @@
/**
* @PM_RET_SUCCESS: success
- * @PM_RET_ERROR_ARGS: illegal arguments provided
+ * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated)
+ * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated)
+ * @PM_RET_ERROR_INTERNAL: internal error
+ * @PM_RET_ERROR_CONFLICT: conflict
* @PM_RET_ERROR_ACCESS: access rights violation
+ * @PM_RET_ERROR_INVALID_NODE: invalid node
+ * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node
+ * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted
* @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU
- * @PM_RET_ERROR_NOTSUPPORTED: feature not supported
- * @PM_RET_ERROR_PROC: node is not a processor node
- * @PM_RET_ERROR_API_ID: illegal API ID
- * @PM_RET_ERROR_OTHER: other error
+ * @PM_RET_ERROR_NODE_USED: node is already in use
*/
enum pm_ret_status {
PM_RET_SUCCESS,
- PM_RET_ERROR_ARGS,
- PM_RET_ERROR_ACCESS,
- PM_RET_ERROR_TIMEOUT,
- PM_RET_ERROR_NOTSUPPORTED,
- PM_RET_ERROR_PROC,
- PM_RET_ERROR_API_ID,
- PM_RET_ERROR_FAILURE,
- PM_RET_ERROR_COMMUNIC,
- PM_RET_ERROR_DOUBLEREQ,
- PM_RET_ERROR_OTHER,
+ PM_RET_ERROR_ARGS = 1,
+ PM_RET_ERROR_NOTSUPPORTED = 4,
+ PM_RET_ERROR_INTERNAL = 2000,
+ PM_RET_ERROR_CONFLICT = 2001,
+ PM_RET_ERROR_ACCESS = 2002,
+ PM_RET_ERROR_INVALID_NODE = 2003,
+ PM_RET_ERROR_DOUBLE_REQ = 2004,
+ PM_RET_ERROR_ABORT_SUSPEND = 2005,
+ PM_RET_ERROR_TIMEOUT = 2006,
+ PM_RET_ERROR_NODE_USED = 2007
};
/**
@@ -317,4 +324,13 @@
PM_CLOCK_DIV1_ID,
};
+/**
+ * EM API IDs
+ */
+enum em_api_id {
+ EM_SET_ACTION = 1,
+ EM_REMOVE_ACTION,
+ EM_SEND_ERRORS,
+};
+
#endif /* PM_DEFS_H */
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
index 3f4f069..a49bda8 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.c
@@ -29,8 +29,8 @@
#define PM_SET_SUSPEND_MODE 0xa02
#define PM_GET_TRUSTZONE_VERSION 0xa03
-/* !0 - UP, 0 - DOWN */
-static int32_t pm_up = 0;
+/* pm_up = !0 - UP, pm_up = 0 - DOWN */
+static int32_t pm_up, ipi_irq_flag;
#if ZYNQMP_WDT_RESTART
static spinlock_t inc_lock;
@@ -142,6 +142,8 @@
void *handle, void *cookie)
{
int i;
+ uint32_t value;
+
/* enter wfi and stay there */
INFO("Entering wfi\n");
@@ -156,8 +158,9 @@
spin_unlock(&inc_lock);
if (active_cores == 0) {
- pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
- PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM);
+ pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value);
+ value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT;
+ pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value);
}
/* enter wfi and stay there */
@@ -210,6 +213,15 @@
status = pm_ipi_init(primary_proc);
+ ret = pm_get_api_version(&pm_ctx.api_version);
+ if (pm_ctx.api_version < PM_VERSION) {
+ ERROR("BL31: Platform Management API version error. Expected: "
+ "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR,
+ PM_VERSION_MINOR, pm_ctx.api_version >> 16,
+ pm_ctx.api_version & 0xFFFF);
+ return -EINVAL;
+ }
+
#if ZYNQMP_WDT_RESTART
status = pm_wdt_restart_setup();
if (status)
@@ -321,22 +333,21 @@
case PM_GET_API_VERSION:
/* Check is PM API version already verified */
- if (pm_ctx.api_version == PM_VERSION) {
+ if (pm_ctx.api_version >= PM_VERSION) {
+ if (!ipi_irq_flag) {
+ /*
+ * Enable IPI IRQ
+ * assume the rich OS is OK to handle callback IRQs now.
+ * Even if we were wrong, it would not enable the IRQ in
+ * the GIC.
+ */
+ pm_ipi_irq_enable(primary_proc);
+ ipi_irq_flag = 1;
+ }
SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
- ((uint64_t)PM_VERSION << 32));
+ ((uint64_t)pm_ctx.api_version << 32));
}
- ret = pm_get_api_version(&pm_ctx.api_version);
- /*
- * Enable IPI IRQ
- * assume the rich OS is OK to handle callback IRQs now.
- * Even if we were wrong, it would not enable the IRQ in
- * the GIC.
- */
- pm_ipi_irq_enable(primary_proc);
- SMC_RET1(handle, (uint64_t)ret |
- ((uint64_t)pm_ctx.api_version << 32));
-
case PM_SET_CONFIGURATION:
ret = pm_set_configuration(pm_arg[0]);
SMC_RET1(handle, (uint64_t)ret);
@@ -474,8 +485,8 @@
{
uint32_t data[4] = { 0 };
- ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
- pm_arg[3], data);
+ pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
+ pm_arg[3], data);
SMC_RET2(handle, (uint64_t)data[0] | ((uint64_t)data[1] << 32),
(uint64_t)data[2] | ((uint64_t)data[3] << 32));
}
@@ -606,8 +617,78 @@
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32));
}
+ case PM_REGISTER_ACCESS:
+ {
+ uint32_t value;
+
+ ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2],
+ pm_arg[3], &value);
+ SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ }
+
+ case PM_EFUSE_ACCESS:
+ {
+ uint32_t value;
+
+ ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value);
+ SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ }
+
default:
WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
}
+
+/**
+ * em_smc_handler() - SMC handler for EM-API calls coming from EL1/EL2.
+ * @smc_fid - Function Identifier
+ * @x1 - x4 - Arguments
+ * @cookie - Unused
+ * @handler - Pointer to caller's context structure
+ *
+ * @return - Unused
+ *
+ * Determines that smc_fid is valid and supported EM SMC Function ID from the
+ * list of em_api_ids, otherwise completes the request with
+ * the unknown SMC Function ID
+ *
+ * The SMC calls for EM service are forwarded from SIP Service SMC handler
+ * function with rt_svc_handle signature
+ */
+uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
+ uint64_t x4, void *cookie, void *handle, uint64_t flags)
+{
+ enum pm_ret_status ret;
+
+ switch (smc_fid & FUNCID_NUM_MASK) {
+ /* EM API Functions */
+ case EM_SET_ACTION:
+ {
+ uint32_t value;
+
+ ret = em_set_action(&value);
+ SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ }
+
+ case EM_REMOVE_ACTION:
+ {
+ uint32_t value;
+
+ ret = em_remove_action(&value);
+ SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ }
+
+ case EM_SEND_ERRORS:
+ {
+ uint32_t value;
+
+ ret = em_send_errors(&value);
+ SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ }
+
+ default:
+ WARN("Unimplemented EM Service Call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+ }
+}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_svc_main.h b/plat/xilinx/zynqmp/pm_service/pm_svc_main.h
index 0968f64..abadd40 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_svc_main.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_svc_main.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,4 +14,7 @@
uint64_t x4, void *cookie, void *handle,
uint64_t flags);
+uint64_t em_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
+ uint64_t x4, void *cookie, void *handle,
+ uint64_t flags);
#endif /* PM_SVC_MAIN_H */
diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c
index 9b18274..114da33 100644
--- a/plat/xilinx/zynqmp/sip_svc_setup.c
+++ b/plat/xilinx/zynqmp/sip_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,6 +25,9 @@
#define PM_FID_MASK 0xf000u
#define PM_FID_VALUE 0u
#define IPI_FID_VALUE 0x1000u
+#define EM_FID_MASK 0xf0000u
+#define EM_FID_VALUE 0xE0000u
+#define is_em_fid(_fid) (((_fid) & EM_FID_MASK) == EM_FID_VALUE)
#define is_pm_fid(_fid) (((_fid) & PM_FID_MASK) == PM_FID_VALUE)
#define is_ipi_fid(_fid) (((_fid) & PM_FID_MASK) == IPI_FID_VALUE)
@@ -41,9 +44,7 @@
static int32_t sip_svc_setup(void)
{
/* PM implementation as SiP Service */
- pm_setup();
-
- return 0;
+ return pm_setup();
}
/**
@@ -61,8 +62,12 @@
void *handle,
u_register_t flags)
{
+ /* Let EM SMC handler deal with EM-related requests */
+ if (is_em_fid(smc_fid)) {
+ return em_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
+ flags);
+ } else if (is_pm_fid(smc_fid)) {
/* Let PM SMC handler deal with PM-related requests */
- if (is_pm_fid(smc_fid)) {
return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
flags);
}
diff --git a/services/std_svc/spm_mm/spm_mm_setup.c b/services/std_svc/spm_mm/spm_mm_setup.c
index 468e5b3..32562c3 100644
--- a/services/std_svc/spm_mm/spm_mm_setup.c
+++ b/services/std_svc/spm_mm/spm_mm_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -142,6 +142,8 @@
SCTLR_DZE_BIT |
/* Enable SP Alignment check for EL0 */
SCTLR_SA0_BIT |
+ /* Don't change PSTATE.PAN on taking an exception to EL1 */
+ SCTLR_SPAN_BIT |
/* Allow cacheable data and instr. accesses to normal memory. */
SCTLR_C_BIT | SCTLR_I_BIT |
/* Enable MMU. */
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index 0ec08b0..c3c8bcf 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -59,7 +59,7 @@
.PHONY: all clean realclean
-all: clean ${BINARY}
+all: ${BINARY}
${BINARY}: ${OBJECTS} Makefile
@echo " HOSTLD $@"
diff --git a/tools/encrypt_fw/Makefile b/tools/encrypt_fw/Makefile
index 6eb6fae..96dff23 100644
--- a/tools/encrypt_fw/Makefile
+++ b/tools/encrypt_fw/Makefile
@@ -46,7 +46,7 @@
.PHONY: all clean realclean
-all: clean ${BINARY}
+all: ${BINARY}
${BINARY}: ${OBJECTS} Makefile
@echo " HOSTLD $@"