Tegra: init normal/crash console for platforms
The BL2 fills in the UART controller ID to be used as the normal as
well as the crash console on Tegra platforms. The controller ID to
UART controller base address mapping is handled by each Tegra SoC
the base addresses might change across Tegra chips.
This patch adds the handler to parse the platform params to get the
UART ID for the per-soc handlers.
Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index 9e66023..75416ec 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -47,6 +47,8 @@
uint64_t tzdram_size;
/* TZ memory base */
uint64_t tzdram_base;
+ /* UART port ID */
+ int uart_id;
} plat_params_from_bl2_t;
/* Declarations for plat_psci_handlers.c */
@@ -55,6 +57,7 @@
/* Declarations for plat_setup.c */
const mmap_region_t *plat_get_mmio_map(void);
+uint32_t plat_get_console_from_id(int id);
/* Declarations for plat_secondary.c */
void plat_secondary_setup(void);