fix(errata): workaround for Cortex X2 erratum 2058056

Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.
It applies to revisions r0p0, r1p0, and r2p0 and is still open.

There are 2 ways this workaround can be accomplished, the first of
which involves executing a few additional instructions around MSR
writes to CPUECTLR when disabling the prefetcher. (see SDEN for

However, this patch implements the 2nd possible workaround which sets
the prefetcher into its most conservative mode, since this workaround
is generic.

SDEN can be found here:

Signed-off-by: John Powell <>
Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3
4 files changed