fvp_r: load, auth, and transfer from BL1 to BL33
Adding load, authentication, and transfer functionality from FVP R BL1 to
BL33, which will be the partner runtime code.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40
diff --git a/include/plat/arm/board/fvp_r/fvp_r_bl1.h b/include/plat/arm/board/fvp_r/fvp_r_bl1.h
new file mode 100644
index 0000000..0b41e67
--- /dev/null
+++ b/include/plat/arm/board/fvp_r/fvp_r_bl1.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FVP_R_BL1_H
+#define FVP_R_BL1_H
+
+void bl1_load_bl33(void);
+void bl1_transfer_bl33(void);
+
+#endif /* FVP_R_BL1_H */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 08f7ff9..7cc215f 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -321,31 +321,31 @@
/* Memory mapped Generic timer interfaces */
#ifdef PLAT_ARM_SYS_CNTCTL_BASE
-#define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE
+#define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE
#else
#define ARM_SYS_CNTCTL_BASE UL(0x2a430000)
#endif
#ifdef PLAT_ARM_SYS_CNTREAD_BASE
-#define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE
+#define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE
#else
#define ARM_SYS_CNTREAD_BASE UL(0x2a800000)
#endif
#ifdef PLAT_ARM_SYS_TIMCTL_BASE
-#define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE
+#define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE
#else
#define ARM_SYS_TIMCTL_BASE UL(0x2a810000)
#endif
#ifdef PLAT_ARM_SYS_CNT_BASE_S
-#define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S
+#define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S
#else
#define ARM_SYS_CNT_BASE_S UL(0x2a820000)
#endif
#ifdef PLAT_ARM_SYS_CNT_BASE_NS
-#define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS
+#define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS
#else
#define ARM_SYS_CNT_BASE_NS UL(0x2a830000)
#endif
@@ -354,7 +354,7 @@
/* Trusted Watchdog constants */
#ifdef PLAT_ARM_SP805_TWDG_BASE
-#define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE
+#define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE
#else
#define ARM_SP805_TWDG_BASE UL(0x2a490000)
#endif
@@ -415,9 +415,14 @@
* addresses.
******************************************************************************/
#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
+#ifdef PLAT_BL1_RO_LIMIT
+#define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT
+#else
#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
+ (PLAT_ARM_TRUSTED_ROM_SIZE - \
PLAT_ARM_MAX_ROMLIB_RO_SIZE))
+#endif
+
/*
* Put BL1 RW at the top of the Trusted SRAM.
*/