tree 3cd3bfd27c25a4251b957b31aded9bd6f4e9502e
parent 5897e135445e2bf3345297fbe9971a113506d714
author Tanmay Shah <tanmay.shah@amd.com> 1661551560 -0700
committer Joanna Farley <joanna.farley@arm.com> 1663053767 +0200

feat(versal): add infrastructure to handle multiple interrupts

Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e