| commit | e60bedd5e134e2ad996a0d21a8170caec12c2dd2 | [log] [tgz] |
|---|---|---|
| author | Sieu Mun Tang <sieu.mun.tang@intel.com> | Fri Oct 25 09:22:00 2024 +0800 |
| committer | Sieu Mun Tang <sieu.mun.tang@intel.com> | Fri Oct 25 09:29:20 2024 +0800 |
| tree | b79e87fdb9b436c890e921fb0cf487b348048277 | |
| parent | 5d23325e6b3ebf5caabc5db763b328ea818abd79 [diff] |
feat(intel): clock manager PLL configuration for Agilex5 platform Read the hand-off data and configure the clock manager main and peripheral PLL and few other misc updates. Change-Id: I3c5cbaf7a677a022ef24b0e679860e6ee195f16a Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>